JPH0450927U - - Google Patents
Info
- Publication number
- JPH0450927U JPH0450927U JP9170490U JP9170490U JPH0450927U JP H0450927 U JPH0450927 U JP H0450927U JP 9170490 U JP9170490 U JP 9170490U JP 9170490 U JP9170490 U JP 9170490U JP H0450927 U JPH0450927 U JP H0450927U
- Authority
- JP
- Japan
- Prior art keywords
- counter
- signal
- value
- output
- preset value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 4
- 230000003321 amplification Effects 0.000 claims description 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 4
- 239000000470 constituent Substances 0.000 description 1
Description
第１図は、本考案による信号振幅制御回路の構
成を示すブロツク図。第２図は、第１図に示す本
考案による信号振幅制御回路の構成を示すブロツ
ク毎の出力の概略波形を示す波形図。第３図は、
従来の信号振幅制御回路の構成を示すブロツク図
。第４図は、従来の信号振幅制御回路の構成ブロ
ツクの出力概略波形を示す波形図。
１……開始信号発生回路、２……開始信号、３
……基準信号発生回路、４……基準信号、５……
カウンタ、６……カウンタ出力信号、７……プリ
セツト設定回路、８……プリセツト信号、９……
ラツチ回路、１０……カウンタプリセツト入力信
号、１１……ラツチ信号、１２……振幅変調回路
、１３……振幅変調信号、１４……アナログ入力
信号、１５，２２……増幅回路、１６……アナロ
グ出力信号、１７……オン・オフ信号発生回路、
１８……オン・オフ信号、１９……振幅変調回路
、２０……振幅変調信号、２１……アナログ入力
信号、２３……アナログ出力信号。
FIG. 1 is a block diagram showing the configuration of a signal amplitude control circuit according to the present invention. FIG. 2 is a waveform diagram showing a schematic waveform of the output of each block showing the configuration of the signal amplitude control circuit according to the present invention shown in FIG. Figure 3 shows
1 is a block diagram showing the configuration of a conventional signal amplitude control circuit. FIG. 4 is a waveform diagram showing a schematic output waveform of the constituent blocks of a conventional signal amplitude control circuit. 1...Start signal generation circuit, 2...Start signal, 3
...Reference signal generation circuit, 4...Reference signal, 5...
Counter, 6... Counter output signal, 7... Preset setting circuit, 8... Preset signal, 9...
Latch circuit, 10...Counter preset input signal, 11...Latch signal, 12...Amplitude modulation circuit, 13...Amplitude modulation signal, 14...Analog input signal, 15, 22...Amplification circuit, 16... Analog output signal, 17...on/off signal generation circuit,
18...on/off signal, 19...amplitude modulation circuit, 20...amplitude modulation signal, 21...analog input signal, 23...analog output signal.
Claims (1)
基準信号の数をカウントするカウンタと、カウン
タ信号の出力に基づきデイジタル・アナログ変換
を行い振幅変調信号を出力する振幅変調回路を有
し、前記カウンタは開始信号とカウンタの第１の
プリセツト値との間は加算し、カウンタの第２の
プリセツト値より減算する操作を繰り返すアツプ
ダウンカウンタの機能を備え、前記カウンタは開
始信号により基準信号の数をカウント開始し、カ
ウンタ第１のプリセツト値とカウントした値が一
致した後カウンタの値をカウンタ出力信号として
ラツチ出力しておき、そのまま第１のプリセツト
値から第２のプリセツト値の間を基準信号の数の
カウントを続け、カウンタ第２のプリセツト値と
カウンタの値が一致した時カウンタの前記ラツチ
したカウンタ値をカウンタにプリセツト入力して
、その後基準信号の数によりカウンタ値の減算を
行うように構成し、前記カウンタの出力信号を振
幅変調回路に入力してデイジタル・アナログ変換
し、該変換出力信号によりアナログ増幅回路の増
幅度を変化させるように構成し、増幅回路のアナ
ログ入力信号の振幅を制御して出力するよう構成
したことを特徴とする信号振幅制御回路。 It has a reference signal generation circuit that generates a reference signal, a counter that counts the number of the reference signals, and an amplitude modulation circuit that performs digital-to-analog conversion based on the output of the counter signal and outputs an amplitude modulation signal, the counter It has an up-down counter function that repeats the operation of adding between the start signal and the first preset value of the counter and subtracting from the second preset value of the counter, and the counter counts the number of reference signals based on the start signal. After the first preset value of the counter and the counted value match, the counter value is latched and output as the counter output signal, and the number of reference signals is set between the first preset value and the second preset value. continues counting, and when the second preset value of the counter and the counter value match, the latched counter value of the counter is preset inputted to the counter, and then the counter value is subtracted according to the number of reference signals. , the output signal of the counter is input to an amplitude modulation circuit for digital-to-analog conversion, and the conversion output signal is configured to change the amplification degree of the analog amplifier circuit, thereby controlling the amplitude of the analog input signal of the amplifier circuit. What is claimed is: 1. A signal amplitude control circuit configured to output a signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9170490U JPH0450927U (en) | 1990-08-31 | 1990-08-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9170490U JPH0450927U (en) | 1990-08-31 | 1990-08-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0450927U true JPH0450927U (en) | 1992-04-28 |
Family
ID=31827571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9170490U Pending JPH0450927U (en) | 1990-08-31 | 1990-08-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0450927U (en) |
-
1990
- 1990-08-31 JP JP9170490U patent/JPH0450927U/ja active Pending