JPH0336761A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0336761A JPH0336761A JP1172239A JP17223989A JPH0336761A JP H0336761 A JPH0336761 A JP H0336761A JP 1172239 A JP1172239 A JP 1172239A JP 17223989 A JP17223989 A JP 17223989A JP H0336761 A JPH0336761 A JP H0336761A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- source
- gate
- semiconductor substrate
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 2
- 239000012535 impurity Substances 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- 150000001875 compounds Chemical class 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 150000002739 metals Chemical class 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract 1
- 230000003321 amplification Effects 0.000 description 6
- 238000003199 nucleic acid amplification method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明(よ 低歪の高周波増幅用FET (電界効果ト
ランジスタ)に関するものであも
従来の技術
近承 高周波機器の高性能化に伴なuL 高周波増幅
用FETの低歪化が強く望まれでいa 以下に従来の高
周波増幅用FETについて説明すも第3図(戴 イオン
注入法によりFETの活性層を形成した 従来の高周波
増幅用FETのgm (相互コンダクタンス)特性を示
すものであも 第3図におイテ、 lotはFET、
103はドレイン1欲1゜4はゲートバイアス1派2
00はgmのゲート−ソース間電圧(Vo 容)依存性
を示す特性曲線であ& FETのゲートに複数の人力
信号が印加されたとき、出力信号に現われる歪成分1よ
FETの非線形に依存する。すなわちFETに流れる
ソース、 ドレイン電流(Ios)をVanで表わすと
、1os−a@+a+Vo*+atVas”+asVa
s’+・・”・となり、 2次歪はa2で、 3次歪は
a3でそれぞれ決定されも −X gmは
であるか板 FETの動作状態におけるgmが定数に等
し鶏 すなわちa2 ”a3−・・・−〇、 a+≠0
であるとき、歪成分はゼロになん 従って動作点近傍に
おけるgm−Vo *曲線のVasに関する微分項がゼ
ロに近いはど歪成分は小さくなる。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a FET (field effect transistor) for high frequency amplification with low distortion, but it is still a conventional technology. There is a strong desire for low distortion in FETs for high frequency amplification. (mutual conductance) characteristics as shown in Figure 3, lot is FET,
103 is drain 1 desire 1゜4 is gate bias 1 faction 2
00 is a characteristic curve showing the dependence of gm on the gate-source voltage (Vo capacity) & When multiple human input signals are applied to the gate of the FET, the distortion component 1 that appears in the output signal depends on the nonlinearity of the FET. . In other words, if the source and drain current (Ios) flowing through the FET is expressed by Van, 1os-a@+a+Vo*+atVas''+asVa
The second-order distortion is determined by a2, and the third-order distortion is determined by a3. −・・・−〇, a+≠0
When , the distortion component becomes zero. Therefore, as the differential term with respect to Vas of the gm-Vo* curve near the operating point is close to zero, the distortion component becomes small.
発明が解決しようとする課題
しかしなが転 上記従来の方法で+1FETの動作点近
傍におけるgm−Vat曲線のVatに関する微分項を
ゼロに近づけることは極めて困難であも これi;LF
ET形成時におけるイオン注入法による不純物の深さ方
向への分布パ ガウス分布に近い分布を持つことによa
本発明は上記従来の問題点を解決するもので、低歪の
高周波増幅用FETを提供することを目的とすも
課題を解決するための手段
この目的を遠戚するために本発明の高周波増幅用F E
T i& 半導体基板上にgmのVes依存性が相
異なる第11 第2のFETを形成し 前記両FET
のゲート、ソース、 ドレインをそれぞれ接続し動作点
付近で相互コンダクタンスを平坦としたものであも
作用
この構成によって、gm−Vow曲線のVatに関する
微分項がゼロに近い領域を作ることが出来 この部分を
動作点に選ぶことにより、低歪の高周波増幅用FETを
作ることができも
実施例
以下、本発明の一実施例について、図面を参照しながら
説明す71o 第1図は本発明の第1の実施例におけ
る半導体装置の回路図を示すものであも第1図(a)に
おいて、101.102はFET、103はドレイン重
態104はゲートバイアス型温 第1図(b)において
、105はF E T 101のgm−Vas特i
106はFE T 102のgm−Vow特性、 10
7f;t、 F E ’r 101と102のgm−
Vest性を足し合わせたものであム 第1図(a)の
様に構成された回路は 全体として第1図(b)に示す
g[D−Yes特性を持ったl& FETの動作点を
Va 5−OV付近に設定すれハgmが平坦であること
か転 極めて低歪の高周波増幅器を実現することができ
へ 第2図C& 本発明の半導体装置のプロセス工程
の実施例を示すものであも 第2図(a)は第1のFE
Tの活性層201α 第2図(b)は第2のFETの活
性層202の形成方法を示すものであも レジスト20
4をマスクとして、不純物イオンIを半絶縁性化合物半
導体基板203に注入すも その抵 ソース、 ドレイ
ン領域にn+注入を行なも\ ソース、ドレイン、ゲー
ト金属を蒸着して、ソース電極20大 トレイン電極2
0飄 ゲート電極207を形成L 第2図(c)に示
す様に各電極を接続すも 活性層201.202はそれ
ぞれ第1図105.106に対応する特性を得るために
異なるイオン注入条件を用いて形成されている。Problem to be Solved by the InventionHowever, there is a disadvantage in that although it is extremely difficult to bring the differential term with respect to Vat of the gm-Vat curve near the operating point of +1FET close to zero using the conventional method described above, this i;LF
The distribution of impurities in the depth direction due to the ion implantation method during ET formation has a distribution close to a Gaussian distribution.
The present invention solves the above conventional problems, and aims to provide a FET for high frequency amplification with low distortion. For F E
An eleventh second FET having different gm dependence on Ves is formed on the Ti&semiconductor substrate, and both of the FETs are
This configuration creates a region where the differential term with respect to Vat in the gm-Vow curve is close to zero. By selecting the operating point as the operating point, a high-frequency amplification FET with low distortion can be manufactured. In FIG. 1(a), 101 and 102 are FETs, 103 is a drain heavy state, 104 is a gate bias type temperature control device, and in FIG. 1(b), 105 is an FET. E T 101 gm-Vas special i
106 is the gm-Vow characteristic of FET 102, 10
7f;t, F E'r 101 and 102 gm-
As a whole, the circuit configured as shown in Figure 1(a) is the sum of the Vest characteristics. If set to around 5-OV, it is possible to realize a high frequency amplifier with extremely low distortion due to the fact that the gm is flat. Figure 2(a) shows the first FE.
Active layer 201α of T. FIG. 2(b) shows a method of forming the active layer 202 of the second FET.
4 as a mask, impurity ions I are implanted into the semi-insulating compound semiconductor substrate 203, and n+ implantation is performed into the resistor and drain regions. Source, drain, and gate metals are evaporated, and the source electrode 20 large train is formed. Electrode 2
Form the gate electrode 207. Connect each electrode as shown in Figure 2(c).The active layers 201 and 202 are implanted under different ion implantation conditions to obtain the characteristics corresponding to Figure 105 and 106, respectively. It is formed using
発明の効果
以上の様に本発明1上gmのVas依存性が相異なる複
数個のFETを並列に接続することにより、低歪の増幅
を行なう優れた高周波増幅用半導体装置を実現できるも
のであもEffects of the Invention As described above, in accordance with the present invention, an excellent semiconductor device for high frequency amplification that performs low distortion amplification can be realized by connecting a plurality of FETs having different Vas dependencies of gm in parallel. too
第1図(a)は本発明の第1の実施例における半導体装
置の回路は 第1図(b)は同gm−Va*特性は 第
2図(a)〜(c)は本実施例の半導体装置のプロセス
工程諷 第3図は従来の半導体装置の回路図とgm−I
/am特性図であもFIG. 1(a) shows the circuit of the semiconductor device according to the first embodiment of the present invention. FIG. 1(b) shows the gm-Va* characteristics of the semiconductor device according to the first embodiment of the present invention. Figure 3 shows the circuit diagram of a conventional semiconductor device and GM-I
/am characteristic diagram
Claims (2)
ソース間電圧依存性が相異なる第1、第2の電界効果ト
ランジスタを形成し、前記両トランジスタのゲート、ソ
ース、ドレインをそれぞれ接続し、動作点付近で相互コ
ンダクタンスを平坦としたことを特徴とする半導体装置
。(1) A mutual conductance gate on a semiconductor substrate.
It is characterized by forming first and second field effect transistors having different source-to-source voltage dependencies, and connecting the gates, sources, and drains of both transistors, respectively, and flattening the mutual conductance near the operating point. Semiconductor equipment.
Tの活性領域を、異なるイオン注入条件を用いて形成す
ることを特徴とする特許請求の範囲第1項記載の半導体
装置。(2) First FET and second FE in the same semiconductor substrate
2. The semiconductor device according to claim 1, wherein the active regions of T are formed using different ion implantation conditions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1172239A JPH0336761A (en) | 1989-07-03 | 1989-07-03 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1172239A JPH0336761A (en) | 1989-07-03 | 1989-07-03 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0336761A true JPH0336761A (en) | 1991-02-18 |
Family
ID=15938198
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1172239A Pending JPH0336761A (en) | 1989-07-03 | 1989-07-03 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0336761A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5156498A (en) * | 1990-04-05 | 1992-10-20 | Tokuyama Soda Kabushiki Kaisha | Method for controlling moisture content of silica powder |
-
1989
- 1989-07-03 JP JP1172239A patent/JPH0336761A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5156498A (en) * | 1990-04-05 | 1992-10-20 | Tokuyama Soda Kabushiki Kaisha | Method for controlling moisture content of silica powder |
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