JPH0336739A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0336739A JPH0336739A JP17242789A JP17242789A JPH0336739A JP H0336739 A JPH0336739 A JP H0336739A JP 17242789 A JP17242789 A JP 17242789A JP 17242789 A JP17242789 A JP 17242789A JP H0336739 A JPH0336739 A JP H0336739A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- stress
- lead frame
- semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 238000000465 moulding Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、モールド樹脂で被覆された半導体装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device covered with a molding resin.
この発明は半導体装置において、半導体チップの裏面に
穴をあけることにより、半導体装置の表面に加わる応力
を緩和するようにしたものである。This invention relates to a semiconductor device in which stress applied to the front surface of the semiconductor device is alleviated by making a hole in the back surface of the semiconductor chip.
従来、第３図に示すように、半導体装置の半導体チップ
ｌの裏面にリードフレーム２を接着させて固定するよう
にした半導体装置が知られていた。Conventionally, as shown in FIG. 3, a semiconductor device has been known in which a lead frame 2 is bonded and fixed to the back surface of a semiconductor chip 1 of the semiconductor device.
このように、従来の半導体装置においては、半導体チッ
プｌの裏面の全面がリードフレーム２に接着されている
ので、高温の時に、リードフレーム２が膨張した場合、
半導体チップ１の表面に応力がかかり、半導体素子４に
応力が加わり、特性が変化する欠点があった。In this way, in the conventional semiconductor device, the entire back surface of the semiconductor chip l is bonded to the lead frame 2, so if the lead frame 2 expands at high temperatures,
There is a drawback that stress is applied to the surface of the semiconductor chip 1, stress is applied to the semiconductor element 4, and the characteristics change.
そこで、この発明は従来のこのような欠点を解決するた
め、リードフレーム２が高温によって膨張しても、半導
体チップ１の表面に応力がかからず、半導体素子４の特
性を変化させないことを目的としている。Therefore, in order to solve these conventional drawbacks, the present invention aims to prevent stress from being applied to the surface of the semiconductor chip 1 and to prevent changes in the characteristics of the semiconductor element 4 even if the lead frame 2 expands due to high temperatures. It is said that
上記目的を達成するために、この発明は半導体チップ裏
面に穴をあけて、半導体チップの裏面とリードフレーム
の接着する面を少なくし、リードフレームの応力が半導
体チップの表面に加わらないようにした。In order to achieve the above object, the present invention makes a hole in the back surface of the semiconductor chip to reduce the bonding surface between the back surface of the semiconductor chip and the lead frame, so that the stress of the lead frame is not applied to the surface of the semiconductor chip. .
上記のように構成された半導体装置を高温に放置すると
、リードフレームが膨張しても半導体チップの裏面のみ
で応力が吸収することにより、半導体チップの表面に応
力がかからずに半導体素子の特性が変化しないで安定に
することができるのである。If a semiconductor device configured as described above is left at a high temperature, even if the lead frame expands, the stress will be absorbed only by the back side of the semiconductor chip, and the characteristics of the semiconductor element will be improved without stress being applied to the front surface of the semiconductor chip. can be made stable without changing.
以下に、この発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１図において、半導体チップ１の裏面に穴５をあける
。半導体チップｌの裏面とリードフレーム２を接着する
。In FIG. 1, a hole 5 is made in the back surface of a semiconductor chip 1. The back surface of the semiconductor chip l and the lead frame 2 are bonded.
このように穴２をあけた場合は、リードフレーム２から
の応力が穴２で吸収することができるので半導体チップ
１の表面に応力が加わらない、そのため半導体素子にも
応力が加わらない。When the holes 2 are formed in this way, the stress from the lead frame 2 can be absorbed by the holes 2, so no stress is applied to the surface of the semiconductor chip 1, and therefore no stress is applied to the semiconductor element.
以上のような実施例において、このような構造になって
いるので、その効果としては、高温にしてもリードフレ
ーム２からの応力が半導体素子４に加わらず、特性を安
定にすることができる。Since the above-described embodiments have such a structure, the effect is that stress from the lead frame 2 is not applied to the semiconductor element 4 even at high temperatures, making it possible to stabilize the characteristics.
この発明は、以上説明したように半導体チップの裏面に
穴をあけたことで半導体素子に加わる応力を抑制し、特
性を安定にする効果がある。As explained above, this invention has the effect of suppressing the stress applied to the semiconductor element and stabilizing its characteristics by forming a hole on the back surface of the semiconductor chip.
第１図はこの発明にかかる半導体装置の縦断面図、第２
図はこの発明にかかる半導体装置の横断面図、第３図は
従来の半導体装置の縦断面図である。
半導体チップ
リードフレーム
モールド樹脂
半導体素子
穴
出願Å
以上
セイコー電子工業株式会社FIG. 1 is a vertical cross-sectional view of a semiconductor device according to the present invention, and FIG.
The figure is a cross-sectional view of a semiconductor device according to the present invention, and FIG. 3 is a vertical cross-sectional view of a conventional semiconductor device. Semiconductor chip lead frame mold resin semiconductor element hole application A Seiko Electronics Industries Co., Ltd.
Claims (1)
をモールド樹脂で被覆してなる半導体装置において、上
記半導体チップの裏面に多数の穴が設けられていること
を特徴とする半導体装置。What is claimed is: 1. A semiconductor device comprising a semiconductor chip and a lead frame bonded to the back surface of the semiconductor chip covered with a molding resin, characterized in that a large number of holes are provided in the back surface of the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17242789A JPH0336739A (en) | 1989-07-04 | 1989-07-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17242789A JPH0336739A (en) | 1989-07-04 | 1989-07-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0336739A true JPH0336739A (en) | 1991-02-18 |
Family
ID=15941772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17242789A Pending JPH0336739A (en) | 1989-07-04 | 1989-07-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0336739A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0613594A (en) * | 1992-06-26 | 1994-01-21 | Matsushita Electron Corp | Solid-state image pick-up device |
-
1989
- 1989-07-04 JP JP17242789A patent/JPH0336739A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0613594A (en) * | 1992-06-26 | 1994-01-21 | Matsushita Electron Corp | Solid-state image pick-up device |
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