JPH0335544A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0335544A JPH0335544A JP1171423A JP17142389A JPH0335544A JP H0335544 A JPH0335544 A JP H0335544A JP 1171423 A JP1171423 A JP 1171423A JP 17142389 A JP17142389 A JP 17142389A JP H0335544 A JPH0335544 A JP H0335544A
- Authority
- JP
- Japan
- Prior art keywords
- film
- groove
- semiconductor device
- trench
- impurity diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 7
- 239000007789 gas Substances 0.000 abstract description 3
- 230000001590 oxidative effect Effects 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 239000013078 crystal Substances 0.000 abstract description 2
- 238000005121 nitriding Methods 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- SQBBHCOIQXKPHL-UHFFFAOYSA-N tributylalumane Chemical compound CCCC[Al](CCCC)CCCC SQBBHCOIQXKPHL-UHFFFAOYSA-N 0.000 description 2
- 241000442446 Farfantepenaeus brevirostris Species 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000005587 bubbling Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野Ｊ 本発明は、半導体装置に関するものである。[Detailed description of the invention] [Industrial Application Field J The present invention relates to a semiconductor device.
さらに言えば、半導体装置内に形成されたトレン分離構
造に関するものである。More specifically, it relates to a trench isolation structure formed within a semiconductor device.
【発明の概要］
ン
本発明は、半導体装置のトレンチ分離に於て、溝内に、
金属酸化物が埋め込まれていることを特徴とした半導体
装置に関するものである。[Summary of the Invention] The present invention provides a method for trench isolation of a semiconductor device.
The present invention relates to a semiconductor device characterized by having a metal oxide embedded therein.
［従来の技術］
第４．５図は、従来のトレンチ分離の一実施例を示した
。第４図に於て、溝をエツチングで形成した後、５ｉｚ
Ｎ、 ／Ｓ ｉ Ｏａ ＲｉＪ！ｌ １８を全面にデポ
し、続イテ、Ｐａ Ｉ ＹＳ １ｌｌｉｌ ９を４００
０人デボする０次に６μ以上の溝部にダミー用ＳｉＯ□
Ｉ！！２０をフォトエッチにより形成した後全面に、レ
ジスト膜を２〜３μ塗布後、エッチバックすると、すべ
ての溝部に、レジスト２１が、残り、このレジストと、
グミ−５ｉ Ｏｚ膜をマスクにして、ＰｏＩＹＳｉ膜を
エッチバックすると溝内にＰｏＩＹＳｉが残留する。こ
れを熱酸化することにより、溝内に５ｉｎｓ膜２２が形
成される。その後、Ｓ ｉｉＮ ａ ／ Ｓ Ｉ Ｏｚ
膜ヲエッチンクし、洗浄後、ゲート酸化膜２５を形成す
る。さらにゲート電極２６を形成し、後は１通常工程に
よりプロセスを完成させる。[Prior Art] Figure 4.5 shows an example of conventional trench isolation. In Figure 4, after forming the groove by etching, 5iz
N, /S i Oa RiJ! Deposit l 18 on the entire surface and continue with Pa I YS 1llil 9 for 400
SiO□ for dummy in the groove of 6μ or more for zero order
I! ! 20 is formed by photo-etching, a resist film of 2 to 3 μm is coated on the entire surface, and then etched back, the resist 21 remains in all the grooves, and this resist and
When the PoIYSi film is etched back using the Gummy-5i Oz film as a mask, PoIYSi remains in the groove. By thermally oxidizing this, a 5-ins film 22 is formed within the trench. After that, S iiN a / S I Oz
After etching and cleaning the film, a gate oxide film 25 is formed. Furthermore, a gate electrode 26 is formed, and the process is then completed by one normal step.
〔発明が解決しようとする課題１
しかし従来方法によるトレンチ素子分離は溝の大小によ
り、ポリシリコンエッチハックの時に、大きな溝部は、
ポリシリコンがなくなる為、グミ−３ｉＯ−マスク形成
を行わなくてはならず、工程が非常に長い、又、溝中を
埋める時、ポリシリコン面がスムースでないので、クビ
レ２３や５１３Ｎ ４／ Ｓ ｉ Ｏｚ ｌｌＩべりに
よる、段差２４が、形成されてしまう、この為ポリシリ
コン電極２６をエツチングにより形成する時、この段差
やクビレ部にポリシリコンが残留しゲート電極間で、シ
ュートが生じるという欠点があった。[Problem to be solved by the invention 1 However, trench element isolation using the conventional method depends on the size of the trench, and when polysilicon etch hacks, large trenches
Since there is no polysilicon, a gummy-3iO-mask must be formed, which is a very long process, and the polysilicon surface is not smooth when filling the trench, resulting in cracks and 513N4/S i A step 24 is formed due to the Oz II layering. Therefore, when the polysilicon electrode 26 is formed by etching, polysilicon remains on the step or the crevice, resulting in a shoot between the gate electrodes. Ta.
本発明は、従来方法に見られたこのような欠点を一掃し
１合理的で、クビレや段差のない、トレンチ素子分離層
を持った半導体装置を提供するちのである。The present invention eliminates these drawbacks seen in the conventional method and provides a semiconductor device having a trench isolation layer that is rational and free from cracks and steps.
〔課題を解決する為の手段）
本発明は１分離用溝をエツチングした後、溝側壁部のみ
に、絶縁膜を形成し、該溝中に、金属膜を選択的に成長
させた後、該金属を酸化、あるいは、窒化させて、分離
層を平坦にしがも、合理的に形成するちのである。[Means for Solving the Problems] The present invention involves etching a one-separation trench, forming an insulating film only on the trench sidewalls, selectively growing a metal film in the trench, and then etching the trench. The isolation layer can be formed rationally by oxidizing or nitriding the metal to make it flat.
［実 施 例］
１、第１．２．３図は１本発明によるトレンチ分離方法
を示したもので、第１図が完成図である。[Example] 1. Figures 1.2.3 show the trench isolation method according to the present invention, and Figure 1 is a completed diagram.
Ｎ基板（１）中にＰＷｅ Ｉ２１２ （２）とＮＷｅ
Ａ １２（３）を形成後、溝をＳ ｉ Ｏａ膜１４をマ
スクにして、ＲＩＥで形成する０次にＳ ｉ Ｏｘ Ｂ
を、全面にデポ後ＲＩＥでエッチバックすることにより
、溝側壁部のみＳｉｎ、膜４が残り、溝底部は、５ｉｆ
ｔが除かれＳｉが露出する０次に、該Ｓｉｎ、をマスク
として、トリイリブチルアルミニウム（Ｃ，Ｈ，）、Ａ
Ｌガスを、出発体とするＣＶＤ法により、Ｓｉ単結晶上
の溝内に、ＡＬ膜をエピタキシャル成長させる。トリイ
リブチルアルミニウムは、Ａｒでバブリングしてウェハ
ー面ニ供給シ、１００〜２５０’Ｃに加熱すると、１μ
／ｍｉｎの成長速度で、溝中に、均質に単結晶エビ層（
１６）が得られた。ＰＷｅｌｌ中のＰストッパーは、溝
形成後Ｓ ｉ Ｏｚ膜をデポした後。PWe I212 (2) and NWe in N substrate (1)
After forming A 12(3), the groove is formed by RIE using the S i Oa film 14 as a mask.
By etching back by RIE after depositing on the entire surface, the Sin film 4 remains only on the groove sidewalls, and the 5if
t is removed and Si is exposed. Using the Si as a mask, tri-butylaluminum (C, H,), A
An AL film is epitaxially grown in a groove on a Si single crystal by a CVD method using L gas as a starting material. When tri-butylaluminum is supplied to the wafer surface by bubbling with Ar and heated to 100 to 250'C, it becomes 1 μm.
At a growth rate of /min, a single crystal shrimp layer (
16) was obtained. The P stopper in the PWell was formed after the groove was formed and the SiOz film was deposited.
１／２で形成した。ＡＬの結晶性をよくする為には、１
０５０℃以上のランプアニールをすると、改善される。It was formed by 1/2. In order to improve the crystallinity of AL, 1.
This can be improved by lamp annealing at 050°C or higher.
ＡＬの選択成長後、酸素を含んだガス中で酸化し、ＡＬ
、０３膜６を形成する。その後、１４と４のＳ ｉＯ＊
ＩＩＩをエツチングしゲート酸化膜７、ゲート電極８
、低濃度Ｎ型不純物拡散層９、サイドウオール膜１０、
高濃度Ｎ型不純物拡散ｔａｌｌを形成し第２フイールド
１１１１２中にコンタクト孔をもうけ、ＡＬ系配［１３
を形成し。After selective growth of AL, it is oxidized in an oxygen-containing gas and the AL
, 03 film 6 is formed. Then 14 and 4 SiO*
III is etched to form a gate oxide film 7 and a gate electrode 8.
, low concentration N-type impurity diffusion layer 9, sidewall film 10,
A high-concentration N-type impurity diffusion tall is formed, a contact hole is formed in the second field 11112, and the AL system [13
form.
Ｔｒを完成させる。Complete Tr.
〔発明の効果）
本発明は従来の如く、溝の狭い広いにかかわらず、すべ
ての溝中に均質で平坦性な、選択金属酸化膜が得られる
為、工程が非常にシンプルで、短縮されると同時に、従
来のトレンチ素子分離にみられた、モホロジーの悪さ、
や段差が生じない為、素子分離の信頼性と歩回りを向上
させることができるものである。[Effect of the invention] The present invention, unlike the conventional method, can obtain a uniform and flat selective metal oxide film in all grooves, regardless of whether the grooves are narrow or wide, so the process is extremely simple and shortened. At the same time, poor morphology observed in conventional trench element isolation,
Since there are no steps or steps, reliability of device isolation and yield can be improved.
又１本実施例では、ＡＬだけについて述べたが、ＡＬ中
にＳｉや、Ｂ、Ｐ、Ａｓ等の不純物元素を含むことら可
能で、それらの不純物をＳｉ中に拡散することらできる
。又それにより工程をさらに短縮することも可能である
。Further, in this embodiment, only the AL has been described, but it is possible to contain impurity elements such as Si, B, P, and As in the AL, and these impurities can be diffused into the Si. Moreover, it is also possible to further shorten the process.
又、ＡＬの場合、完全に酸化させる１部下方に、金属と
して残すことらできる。さらに、ＡＬ以外の金属、Ｗ、
ＭＯ，Ｔｉ、Ｚｒ、Ｃｏ等ち形成でき、酸化物の他、窒
化物においても、同様の効果が得られる６のである。Further, in the case of AL, it is possible to leave it as a metal under the part to be completely oxidized. Furthermore, metals other than AL, W,
MO, Ti, Zr, Co, etc. can be formed, and in addition to oxides, nitrides can also be used to obtain the same effect.
第１図、第２図及び第３図は本発明の実施例を示す半導
体装置の断面図、第４図、及び第５図は従来の半導体装
置を示す図。
Ｎ基板
Ｐ Ｗ ｅ １２ （Ｉ
ＮＷｅββ
絶縁膜
Ｐストッパー
金属酸化膜
７・・・ゲート膜
８・・・ゲート電極
９・・・Ｎ型低濃度拡敢層
ｌＯ・・・サイドウオール膜
１１・・・Ｎ型高濃度拡散層
１２・・・第２フイールド膜
１３・・・配線層
１４・・・酸化膜
１５・・・Ｓｉ面
１６・・・金属膜
１７・・・Ｓｉ溝
１ Ｂ ・・・５ｉｓＮ４／ Ｓ ｉ Ｏｘ膜１９・・
・ポリシリコン
２０・ ・ ・ダミーＳ ｉ Ｏｘ膿
２１・・・レジスト
２２・・・Ｓ ｉ Ｏａ Ｍ！
２３・・・クビレ
２４・・・段差
２５・ ・ ・ゲート膜
２６・・・ゲート電極
２７ ・
・ゲート電極残り
以
上FIGS. 1, 2, and 3 are cross-sectional views of a semiconductor device showing an embodiment of the present invention, and FIGS. 4 and 5 are views showing a conventional semiconductor device. N substrate P W e 12 (I NWeββ Insulating film P stopper metal oxide film 7...Gate film 8...Gate electrode 9...N-type low concentration expansion layer lO...Side wall film 11... N-type high concentration diffusion layer 12...Second field film 13...Wiring layer 14...Oxide film 15...Si surface 16...Metal film 17...Si groove 1 B...5isN4 / S i Ox film 19...
・Polysilicon 20・・・Dummy S i Ox Pus 21...Resist 22...S i Oa M! 23... Neck 24... Step 25... Gate film 26... Gate electrode 27... More than the rest of the gate electrode
Claims (2)
埋め込まれる分離層は、少なくとも、金属酸化物層ある
いは金属窒化物層を含んでいることを特徴とする半導体
装置。(1) A semiconductor device characterized in that, in trench element isolation of a semiconductor device, an isolation layer buried in the trench includes at least a metal oxide layer or a metal nitride layer.
いることを特徴とした請求項１記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the metal oxide film contains an impurity diffusion element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1171423A JPH0335544A (en) | 1989-07-03 | 1989-07-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1171423A JPH0335544A (en) | 1989-07-03 | 1989-07-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0335544A true JPH0335544A (en) | 1991-02-15 |
Family
ID=15922857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1171423A Pending JPH0335544A (en) | 1989-07-03 | 1989-07-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0335544A (en) |
-
1989
- 1989-07-03 JP JP1171423A patent/JPH0335544A/en active Pending
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