JPH033051U - - Google Patents
Info
- Publication number
- JPH033051U JPH033051U JP6363789U JP6363789U JPH033051U JP H033051 U JPH033051 U JP H033051U JP 6363789 U JP6363789 U JP 6363789U JP 6363789 U JP6363789 U JP 6363789U JP H033051 U JPH033051 U JP H033051U
- Authority
- JP
- Japan
- Prior art keywords
- output terminal
- cpu
- mode
- program
- resetting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
- Safety Devices In Control Systems (AREA)
Description
第１図は本考案の一実施例を示すブロツク回路
図、第２図は第１図実施例の要部回路図、第３図
は本考案の一実施例プログラムを示すフローチヤ
ート図、第４図は第３図の一実施例プログラムに
もとずくＣＰＵの出力端子Ｔ１に表れる電圧波形
図、第５図は本考案の他の実施例を示すプログラ
ムのフローチヤート図、第６図は第５図の一実施
例プログラムにもとずくＣＰＵの出力端子Ｔ１に
表れる電圧波形図、第７図は従来の要部回路図で
ある。
１……第１の積分回路、２……第２の積分回路
、３……切り替え回路、Ｔ１……出端子、Ｔ２…
…リセツト端子、Ｔ３……電源電圧供給端子、１
０……ＣＰＵ、２０……ＲＡＭ、３０……ＲＯＭ
、４０……データバス、５０……電源電圧供給部
、１，２，３，３０……ＣＰＵに対してリセツト
をかける手段。
Fig. 1 is a block circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram of the main part of the embodiment of Fig. 1, Fig. 3 is a flowchart showing a program of an embodiment of the invention, The figure is a voltage waveform diagram appearing at the output terminal T1 of the CPU based on the program of the embodiment shown in FIG. 3, FIG. FIG. 7 is a diagram of the voltage waveform appearing at the output terminal T1 of the CPU based on the example program shown in the figure, and FIG. 7 is a circuit diagram of a conventional main part. DESCRIPTION OF SYMBOLS 1...First integration circuit, 2...Second integration circuit, 3...Switching circuit, T1...Output terminal, T2...
...Reset terminal, T3...Power supply voltage supply terminal, 1
0...CPU, 20...RAM, 30...ROM
, 40... data bus, 50... power supply voltage supply unit, 1, 2, 3, 30... means for resetting the CPU.
Claims (1)
現れる出力端子を設けたＣＰＵと、このＣＰＵが
メイン・ルーチンの処理実行中の適宜合間に、前
記出力端子のモードを反転するための処理を割り
込ませるプログラムを格納したメモリと、前記出
力端子のモードを常時監視し、予め設定した時間
内に前記モードの反転がないとき、前記ＣＰＵに
対してリセツトをかける手段とを備え、前記ＣＰ
Ｕが前記メモリに格納された前記プログラムを読
み出し、自らの前記出力端子を制御することを特
徴とするＣＰＵ制御装置。 A CPU equipped with an output terminal that displays either a high or low level mode, and a program that interrupts processing to invert the mode of the output terminal at appropriate intervals while this CPU is executing main routine processing. and means for constantly monitoring the mode of the output terminal and resetting the CPU when the mode is not reversed within a preset time.
A CPU control device characterized in that U reads the program stored in the memory and controls the output terminal of itself.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6363789U JPH033051U (en) | 1989-05-31 | 1989-05-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6363789U JPH033051U (en) | 1989-05-31 | 1989-05-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH033051U true JPH033051U (en) | 1991-01-14 |
Family
ID=31593867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6363789U Pending JPH033051U (en) | 1989-05-31 | 1989-05-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH033051U (en) |
-
1989
- 1989-05-31 JP JP6363789U patent/JPH033051U/ja active Pending
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