JPH0330303B2 - - Google Patents
Info
- Publication number
- JPH0330303B2 JPH0330303B2 JP56168668A JP16866881A JPH0330303B2 JP H0330303 B2 JPH0330303 B2 JP H0330303B2 JP 56168668 A JP56168668 A JP 56168668A JP 16866881 A JP16866881 A JP 16866881A JP H0330303 B2 JPH0330303 B2 JP H0330303B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- analog
- digital
- power supply
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000000295 complement effect Effects 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 230000003321 amplification Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
Description
【発明の詳細な説明】
本発明はアナログ回路とデイジタル回路が同一
チツプ上にあるコンプリメンタリ・メタルオキサ
イドセミコンダクタ（以後Ｃ・MOSと略記する）
集積回路の基板電位供給方法に関するものであ
る。[Detailed Description of the Invention] The present invention is a complementary metal oxide semiconductor (hereinafter abbreviated as CMOS) in which an analog circuit and a digital circuit are on the same chip.
The present invention relates to a method of supplying a substrate potential to an integrated circuit.
従来からＣ・MOS回路は主にデイジタル回路
用に考えられてきていた。最近、Ｃ・MOS構造
上に比較的容易に容量を付加するプロセスが実現
された。その結果、高利得のアナログ回路をＣ・
MOS構造により実現し得、さらに同一チツプ上
にデイジタル回路を混乱させることが可能となつ
た。ところが、ここでアナログ回路とデイジタル
回路を混在させた故に次の問題点を生じる。つま
り、デイジタル回路内でＣ・MOS構造を構成す
るＰ−チヤネルMOSトランジスタとＮ−チヤネ
ルMOSトランジスタ（以後Ｐ−MOS TRS、Ｎ
−MOS TRSと略す。）が過渡的に同時にONす
る入力電圧範囲が存在し、これに寄因する貫通電
流がデイジタル回路部の電源ラインを流れる。こ
の結果、デイジタル部の電源ラインには配線（主
にアルミニウム配線）抵抗に応じた雑音電圧を発
生する。 Conventionally, C-MOS circuits have been considered mainly for digital circuits. Recently, a process for relatively easily adding capacitance to a CMOS structure has been realized. As a result, high gain analog circuits can be
This could be achieved using a MOS structure, and furthermore, it became possible to confuse digital circuits on the same chip. However, since analog circuits and digital circuits are mixed here, the following problem arises. In other words, P-channel MOS transistors and N-channel MOS transistors (hereinafter P-MOS TRS, N
-Abbreviated as MOS TRS. ) exists at the same time in a transient manner, and the through current caused by this flows through the power supply line of the digital circuit section. As a result, a noise voltage corresponding to the resistance of the wiring (mainly aluminum wiring) is generated in the power supply line of the digital section.
この電源ラインに混入した雑音の電圧が、その
ままアナログ部への電源ラインに混入すると、ア
ナログ部での微弱な入力信号にこの雑音電圧が重
畳し、アナログ部での増幅動作に障害を与えると
言う問題がある。 If this noise voltage mixed into the power supply line is directly mixed into the power supply line to the analog section, this noise voltage will be superimposed on the weak input signal in the analog section, causing a disturbance to the amplification operation in the analog section. There's a problem.
本発明の目的は、上記した問題点をなくし、ア
ナログ回路とデイジタル回路を同一チツプ上に乗
せ、かつ安定な増幅動作を行なうＣ・MOS集積
回路を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems, to provide a CMOS integrated circuit in which an analog circuit and a digital circuit are mounted on the same chip, and which performs stable amplification operation.
上記の目的を達成するために本発明は、デイジ
タル回路部とアナログ回路部との独立な電源供給
端子を単独にもうけたところに特徴がある。 In order to achieve the above object, the present invention is characterized in that independent power supply terminals are provided for the digital circuit section and the analog circuit section.
第１図に本発明の一実施例による、具体的なレ
イアウト図、第２図に集積回路の断面図を示す。
第１図において、１は集積回路が搭載されている
シリコンチツプであり、２，３はアナログ回路の
セル、４，５，６，７はアナログ回路とデイジタ
ル回路へ供給される電源用パツドであり、パツド
より実線で示したものはアルミニウム配線であ
る。８はデイジタル回路のユニツトセルであり９
〜２１は集積回路の入出力用パツド群である。こ
れらのパツド群は第２図に示したように配線２４
を介してリードフレーム２３に接続され外部回路
と接続されるものである。このようにアナログ回
路とデイジタル回路との電源供給配線を別個に設
けることにより、両者間にフイルタ等を設けるこ
とが可能となり前述したデイジタル回路の動作時
の雑音電圧がアナログ回路に混入することを防ぐ
ことが可能となるものである。さらに上記したよ
うな電源供給手段をとることにより、アナログ回
路とデイジタル回路へ供給する最適な電圧を別個
に設定することが出来、かつ電源を別々に制御す
ることも出来、省電力効果にもつながる長所を持
つことになる。 FIG. 1 shows a specific layout diagram according to an embodiment of the present invention, and FIG. 2 shows a cross-sectional view of an integrated circuit.
In Figure 1, 1 is a silicon chip on which an integrated circuit is mounted, 2 and 3 are analog circuit cells, and 4, 5, 6, and 7 are power supply pads that are supplied to the analog and digital circuits. , the solid line drawn from the pad is aluminum wiring. 8 is a unit cell of the digital circuit, and 9
21 is a group of input/output pads for the integrated circuit. These pad groups are connected to wiring 24 as shown in FIG.
It is connected to the lead frame 23 via the lead frame 23 and connected to an external circuit. By providing power supply wiring for the analog circuit and digital circuit separately in this way, it is possible to install a filter, etc. between the two, which prevents the aforementioned noise voltage during operation of the digital circuit from entering the analog circuit. This makes it possible. Furthermore, by using the power supply method described above, it is possible to separately set the optimal voltage to be supplied to analog circuits and digital circuits, and it is also possible to control the power supplies separately, which leads to power saving effects. It will have advantages.
以上述べたように本発明によれば高増幅度を持
つた増幅器をデイジタル回路と同一集積回路上に
混在させた際に問題となつていたデイジタル回路
部で発生する雑音電圧が増幅器に与える影響を低
減でき、かつ前述したような長所を持つことがで
きる。 As described above, according to the present invention, the influence of the noise voltage generated in the digital circuit section on the amplifier, which has been a problem when an amplifier with a high amplification degree is mixed on the same integrated circuit as a digital circuit, can be reduced. can be reduced, and still have the advantages mentioned above.
第１図は本発明の一実施例を示すレイアウト
図、第２図は集積回路の構造を示す断面図であ
る。
１……シリコンチツプ、２，３……アナログ回
路セル、８……デイジタル回路セル、４〜７，９
〜２１……パツド、２３……リードフレーム。
FIG. 1 is a layout diagram showing one embodiment of the present invention, and FIG. 2 is a sectional view showing the structure of an integrated circuit. 1... Silicon chip, 2, 3... Analog circuit cell, 8... Digital circuit cell, 4 to 7, 9
~21... Padded, 23... Lead frame.
Claims (1)
ンダクタ構造を持ち、アナログ回路とデイジタル
回路を同一チツプ上に具備した集積回路におい
て、 該集積回路に電源を供給する電源回路を、アナ
ログ部とデイジタル部に分けて、各々独立に集積
回路の端子より電源を供給し、かつ、アナログ部
とデイジタル部を別々に制御するように構成した
ことを特徴とする集積回路の電源供給回路。[Claims] 1. In an integrated circuit that has a complementary metal oxide semiconductor structure and includes an analog circuit and a digital circuit on the same chip, a power supply circuit that supplies power to the integrated circuit is provided between the analog section and the digital section. 1. A power supply circuit for an integrated circuit, characterized in that the power supply circuit is configured to separately supply power from the terminals of the integrated circuit and separately control the analog section and the digital section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56168668A JPS5870565A (en) | 1981-10-23 | 1981-10-23 | Power supply circuit of intergrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56168668A JPS5870565A (en) | 1981-10-23 | 1981-10-23 | Power supply circuit of intergrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5870565A JPS5870565A (en) | 1983-04-27 |
| JPH0330303B2 true JPH0330303B2 (en) | 1991-04-26 |
Family
ID=15872279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56168668A Granted JPS5870565A (en) | 1981-10-23 | 1981-10-23 | Power supply circuit of intergrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5870565A (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6398872A (en) * | 1986-10-15 | 1988-04-30 | Rohm Co Ltd | Analog/digital ic |
| JPS6424857U (en) * | 1987-08-05 | 1989-02-10 | ||
| JPH01258459A (en) * | 1988-04-08 | 1989-10-16 | Seikosha Co Ltd | Integrated circuit using battery as power source |
| JPH0290666A (en) * | 1988-09-28 | 1990-03-30 | Nec Corp | Power wiring structure of integrated circuit |
| JPH02143553A (en) * | 1988-11-25 | 1990-06-01 | Nec Corp | Semiconductor device |
| JPH0810209Y2 (en) * | 1989-02-21 | 1996-03-27 | ソニー株式会社 | Integrated circuit |
| JPH02110818U (en) * | 1989-02-22 | 1990-09-05 | ||
| JPH02238657A (en) * | 1989-03-13 | 1990-09-20 | Fujitsu Ltd | Semiconductor device |
| JPH03102913A (en) * | 1989-09-15 | 1991-04-30 | Rohm Co Ltd | Interface for cmos circuit |
| US6219909B1 (en) | 1990-11-28 | 2001-04-24 | Hitachi, Ltd. | Method of mounting disk drive apparatus |
| JPH07502868A (en) * | 1991-10-30 | 1995-03-23 | ハリス・コーポレーション | Analog-digital switch and manufacturing method thereof |
| US5649160A (en) * | 1995-05-23 | 1997-07-15 | Microunity Systems Engineering, Inc. | Noise reduction in integrated circuits and circuit assemblies |
| JP6369191B2 (en) * | 2014-07-18 | 2018-08-08 | セイコーエプソン株式会社 | CIRCUIT DEVICE, ELECTRONIC DEVICE, MOBILE BODY, AND RADIO COMMUNICATION SYSTEM |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5420680A (en) * | 1977-07-18 | 1979-02-16 | Hitachi Ltd | Large scale integrated circuit |
-
1981
- 1981-10-23 JP JP56168668A patent/JPS5870565A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5420680A (en) * | 1977-07-18 | 1979-02-16 | Hitachi Ltd | Large scale integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5870565A (en) | 1983-04-27 |
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