JPH03296234A - Wire-bonding method of semiconductor device - Google Patents

Wire-bonding method of semiconductor device

Info

Publication number
JPH03296234A
JPH03296234A JP9098122A JP9812290A JPH03296234A JP H03296234 A JPH03296234 A JP H03296234A JP 9098122 A JP9098122 A JP 9098122A JP 9812290 A JP9812290 A JP 9812290A JP H03296234 A JPH03296234 A JP H03296234A
Authority
JP
Japan
Prior art keywords
wire
bonding
pad
chip
film lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9098122A
Other languages
Japanese (ja)
Inventor
Fumimaro Ikeda
池田 史麻呂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9098122A priority Critical patent/JPH03296234A/en
Publication of JPH03296234A publication Critical patent/JPH03296234A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494Connecting portions
    • H01L2224/4943Connecting portions the connecting portions being staggered
    • H01L2224/49433Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512Aligning
    • H01L2224/85148Aligning involving movement of a part of the bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To achieve bonding without any mark on a wire and that for a chip with a narrow pitch between pads by performing bonding of a short wire initially from a film lead side to a pad side and then that of a long wire from the pad side to the film lead side. CONSTITUTION:First, a short wire 5 is used for bonding from a film lead side to a chip side between a lower stage side film lead 2a and a pad 4 at a side of a chip 3, wire bonding of all lower stage film lead 2a is completed, and then an upper stage side film lead 2b and the pad 4 at a side of the chip 3 are bonded from the pad side to the chip side using a long wire 6, thus achieving bonding to all internal film leads. Therefore, the bonded wire has a peak near the film lead side and the pad side is in wire shape with a low loop, thus preventing contact with an adjacent short wire when a tool moves to the pad side and from the pad side to the film lead side when bonding a longer wire.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の組立方法に関し、特にセラミッ
クケースを用いた半導体装置のワイヤボンディング方法
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for assembling a semiconductor device, and more particularly to a method for wire bonding a semiconductor device using a ceramic case.

〔従来の技術〕[Conventional technology]

従来セラミックケースにダイボンディングされた半導体
チップと、セラミックケースの内部膜リードと”を2種
類の長さのAu線(以下ワイヤ)で接続するボンディン
グ方法は、短い方のワイヤ及び長い方のワイヤ共に、□
チップ電極(以下パッド)側から膜リード側へとボンデ
ィングが行なわれている。
Conventionally, the bonding method connects the semiconductor chip die-bonded to the ceramic case and the internal film lead of the ceramic case using two different lengths of Au wire (hereinafter referred to as wire). , □
Bonding is performed from the chip electrode (hereinafter referred to as pad) side to the membrane lead side.

第3図(a)は上記従来方法を説明するための平面図、
同図(b)は断面図であり、これらの図において、セラ
ミックケース1にダイボンディングされた半導体チップ
3のパッド4から下段の膜リード2a及び上段膜リード
2bへそれぞれ短いワイヤ5および長いワイヤ6を用い
てワイヤボンディングを行うと、パッド5側近くにピー
ク5a、6aを有するワイヤループが形成される。ここ
で、通常、短ワイヤ5と長ワイヤ6は交互に配置された
ワイヤボンディングとなっている。
FIG. 3(a) is a plan view for explaining the above conventional method;
FIG. 5B is a cross-sectional view, and in these figures, a short wire 5 and a long wire 6 are connected from the pad 4 of the semiconductor chip 3 die-bonded to the ceramic case 1 to the lower film lead 2a and the upper film lead 2b, respectively. When wire bonding is performed using the wire, a wire loop having peaks 5a and 6a near the pad 5 side is formed. Here, the short wires 5 and the long wires 6 are normally arranged alternately for wire bonding.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

こうした従来のワイヤボンディング方法では、短ワイヤ
をボンティングした後に、長ワイヤをボンディングする
際、第4図の斜視図に示すように、ツール8と隣接ワイ
ヤが接触し、ワイヤにキズが付いて何かの拍子に断線す
るということが起る。
In such a conventional wire bonding method, when bonding a long wire after bonding a short wire, the tool 8 comes into contact with the adjacent wire, as shown in the perspective view of FIG. It happens that the wire breaks at the same time.

特に、短ワイヤ5のループ高が高くなると、長ワイヤ6
をボンディングするためツール8がパッド側に移動した
時、またパッド側から膜リード側へ移動する過程でツー
ルと隣接ワイヤが接触することになる。これは、チップ
のダイボンド位置がズしている時には、ワイヤ間隔が狭
まくなり、−層その危険性が増大することになる。また
、短ワイヤのワイヤ変形(曲り)も加わり、パッド間距
離が短いチップはボンディングができないという問題が
ある。
In particular, when the loop height of the short wire 5 increases, the long wire 6
When the tool 8 moves to the pad side for bonding, and in the process of moving from the pad side to the film lead side, the tool and the adjacent wire come into contact. This means that when the die bond position of the chip is misaligned, the wire spacing becomes narrower, increasing the risk of damage. In addition, wire deformation (bending) of short wires is added, and there is a problem in that chips with short distances between pads cannot be bonded.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題に対し本発明のワイヤボンディング方法は、最
初に短ワイヤのボンティングを膜リード側からパッド側
へ行ない、次に長ワイヤをパッド側から膜リード側ヘボ
ンディングする。
In order to solve the above problems, the wire bonding method of the present invention first performs bonding of short wires from the membrane lead side to the pad side, and then bonds long wires from the pad side to the membrane lead side.

〔実施例〕 次に本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.

第1図(a)は本発明の第1実施例を説明するための平
面図、同図(b)は断面図である。第1図(a)、 (
b)において、セラミックケース1にグイボンディング
されたチップ3のパッド4と、ケースの内部膜リード2
a、2bとがそれぞれ短ワイヤ5および長ワイヤ6で接
続されている。この実施例でのセラミックケース1は、
内部膜リードが」1下2段で構成され、下段膜リード2
a、上段膜!J −F’ 2 b交互にチップ側のパッ
ドとワイヤで接続されている。ここでのワイヤボンディ
ング方法は、まず下段側膜リード2aと、チップ3側パ
ツド4との間を、膜リード側からチップ側へ短ワイヤ5
でボンディングし、全ての下段膜リード2aのワイヤボ
ンティング完了した後、次に上段側膜リード2bとチッ
プ3側パツド4とをパッド側からチップ側へ長ワイヤ6
でボンディングし、全ての内部膜リードへのボンディン
グが行なわれる。
FIG. 1(a) is a plan view for explaining a first embodiment of the present invention, and FIG. 1(b) is a sectional view. Figure 1(a), (
In b), the pads 4 of the chip 3 bonded to the ceramic case 1 and the internal film leads 2 of the case
a and 2b are connected by a short wire 5 and a long wire 6, respectively. The ceramic case 1 in this example is
The internal membrane lead is composed of 1 and 2 lower tiers, and the lower tier membrane lead is 2.
a. Upper membrane! J-F' 2 b are alternately connected to pads on the chip side by wires. In this wire bonding method, first, a short wire 5 is connected between the lower membrane lead 2a and the pad 4 on the chip 3 side from the membrane lead side to the chip side.
After completing the wire bonding of all the lower film leads 2a, next connect the upper film leads 2b and the pad 4 on the chip 3 side with a long wire 6 from the pad side to the chip side.
Bonding is performed to all internal film leads.

第2図(a) (b)はそれぞれ本発明の第2の実施例
を説明するための平面図と断面図である。これらの図に
おいて、セラミックケース11の内部膜リード7a、7
bは千鳥足の配置で形成されている。ここでのワイヤボ
ンディングも先の実施例と同様に、最初に短ワイヤ5を
内側の膜リード7a側からパッド4ヘボンデインダを行
ない、全ての短ワイヤ5がボンディング完了後、チップ
3側のパッド4から外側の膜リード7bへ長ワイヤ6の
ボンディングが行なわれる。
FIGS. 2(a) and 2(b) are a plan view and a sectional view, respectively, for explaining a second embodiment of the present invention. In these figures, the internal membrane leads 7a, 7 of the ceramic case 11
b is formed in a staggered arrangement. In the wire bonding here, as in the previous embodiment, the short wires 5 are first bonded to the pads 4 from the inner film lead 7a side, and after all the short wires 5 are bonded, the short wires 5 are bonded to the pads 4 on the chip 3 side. Bonding of the long wire 6 to the outer membrane lead 7b is performed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、短い方のワイヤを内部膜
リード側からパッド側ヘボンディングしている。これに
よりボンディングされたワイヤは膜リード側近くにピー
クを有し、パッド側はループの低いワイヤ形状となる為
、次に長い方のワイヤをボンティングする際にツールが
パッド側及びパッド側から膜リード側への移動時に隣接
する短ワイヤと接触することがなくなる。よって、ワイ
ヤにキズが入ることがないボンディングが可能となる。
As explained above, in the present invention, the shorter wire is bonded from the internal film lead side to the pad side. As a result, the bonded wire has a peak near the membrane lead side, and the pad side has a wire shape with a low loop, so when bonding the longer wire next, the tool will move from the pad side and the membrane lead side. There is no possibility of contact with adjacent short wires when moving toward the lead side. Therefore, bonding can be performed without damaging the wire.

また、パッド間ピッチが狭いチップに対しでもボンディ
ングが可能となる。
Furthermore, bonding is possible even for chips with a narrow pitch between pads.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は本発明の第1実施例を説明するためのボ
ンティング状態を示す平面図、同図(b)は断面図、第
2図(a)は、本発明の第2実施例のボンディング状態
を示す平面図、同図(b)は断面図、第3図(a)は従
来のワイヤボンディング方法でのボンティング状態を示
す平面図、同図(b)は断面図、第4図は従来のワイヤ
ボンディング方法を説明するための斜視図である。 ■、11・・・・・・セラミックケース、2a・・・・
・・下段膜リード、2b・・・・・・上段膜リード、3
・・・・・・半導体チップ、4・・・・・・電極パッド
、5・・・・・・短ワイヤ、6・・・・・・長ワイヤ、
7a・・・・・・内側膜リード、7b・・・・・外側膜
リード、8・・・・・・ツール。
FIG. 1(a) is a plan view showing a bonding state for explaining the first embodiment of the present invention, FIG. 1(b) is a sectional view, and FIG. 3(b) is a plan view showing the bonding state in the example, FIG. 3(b) is a sectional view, FIG. 3(a) is a plan view showing the bonding state in the conventional wire bonding method, FIG. 4 is a perspective view for explaining a conventional wire bonding method. ■, 11...Ceramic case, 2a...
...Lower membrane lead, 2b... Upper membrane lead, 3
... Semiconductor chip, 4 ... Electrode pad, 5 ... Short wire, 6 ... Long wire,
7a...Inner membrane lead, 7b...Outer membrane lead, 8...Tool.

Claims (1)

【特許請求の範囲】[Claims]  セラミックケースにダイボンディングされた半導体チ
ップの電極と、前記ケースの内部膜リードとを2種類の
長さのワイヤを用いて接続するワイヤボンディング方法
において、前記の短い方のワイヤは前記膜リードからチ
ップ電極へボンディングを行ない、長い方のワイヤはチ
ップ電極側から膜リードへボンディングすることを特徴
とする半導体装置のワイヤボンディング方法。
In a wire bonding method in which the electrodes of a semiconductor chip die-bonded to a ceramic case and the internal film leads of the case are connected using wires of two different lengths, the shorter wire connects the chip from the film lead to A wire bonding method for a semiconductor device, characterized in that bonding is performed to an electrode, and the longer wire is bonded from the chip electrode side to the film lead.
JP9098122A 1990-04-13 1990-04-13 Wire-bonding method of semiconductor device Pending JPH03296234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9098122A JPH03296234A (en) 1990-04-13 1990-04-13 Wire-bonding method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9098122A JPH03296234A (en) 1990-04-13 1990-04-13 Wire-bonding method of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03296234A true JPH03296234A (en) 1991-12-26

Family

ID=14211489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9098122A Pending JPH03296234A (en) 1990-04-13 1990-04-13 Wire-bonding method of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03296234A (en)

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