JPH03296103A - Timer device for programmable controller - Google Patents

Abstract

PURPOSE:To ensure the accurate working of a timer by selecting one of the zero value, the timer set value, and two types of present timer value as the output of the present timer value set under the conditions of a timer set value register and a comparison output register. CONSTITUTION:A counter reset means 7 stores the count value in a DELTAt register 15 and resets a counter 16, and a present timer value register 14 stores the time elapsed up to the present time point after the timer 16 is started. At the same time, an adder 10 adds together the values of both registers 14 and 15. Then a timer set value register 13 stores the time set value, and a storage outputs the timer set value to the adder 10. A comparison output register 8 stores temporarily the output of a comparator 9. Then an output data selector 6 selects the zero value, the timer set value, the present timer value, or the present timer value +DELTAt as the output of the present timer value set under the conditions of the registers 14, 13 and 8. Thus the accurate working of a timer is ensure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timer device for a programmable controller in which a common part is shared by a plurality of timers.

[Prior Art] FIG. 4 is a diagram showing a conventional timer device of a programmable controller disclosed in, for example, Japanese Patent Application Laid-Open No. 52-60389, in which a common part is shared by a large number of timers. In the figure, (2) is a RAM in which each address has a timer current value storage area that stores the current value of the timer corresponding to that address, and a timer output status storage area that stores the timer output status that corresponds to that address. be. (
SC) is a reference clock pulse generator that generates a pulse for incrementing the current value of the timer at regular intervals, and includes a reference lock section (17), a pulse generator (20), and an AND gate (1).
9). The reference clock section (17) inputs the synchronization signal (n) sent from the arithmetic processing section (not shown) of the programmable controller, and as shown in the counter input timing diagram of the conventional example in FIG. The arithmetic processing section executes the control program at address 0 in the storage section (not shown) of the programmable controller for a certain period of time T in synchronization with the execution of the control program.

A reference clock signal (0) having a width of time T1 for executing the entire control program once every time is generated. A pulse generator (20) generates a pulse signal that increments the current timer value. The AND gate (19) is connected to the reference clock section (1
When the reference clock signal (0) from 7) and the timer operation command signal (e) from the arithmetic processing section are both "L",
One pulse signal (p) from the pulse generator (20) is passed through. This passed signal, ie, the output signal of the AND gate (19), is assumed to be k. (16) is a presettable counter that sets the previous timer current value read from RAM (21) in response to the timer number designation signal (1) from the arithmetic processing section.

This presettable counter (16) is reset by the reset signal (c) when the timer operation command signal (e) is "0", and is reset by the AND gate (19) when the timer operation command signal (e) is "1". When a count up pulse signal (k) is sent from the timer, the current value of the set timer is incremented by one. When the timer operation command signal (e) is "1" and the reference clock signal (0) is "0", the contents of the presettable counter (16) are held as they are. (9) is the setting value of the corresponding timer (g
) and the output of the presettable counter (16), that is, the current value of the timer, and the output of the presettable counter (16) is compared.
6) is a comparator that generates an output only when the counter output (h) is larger.

(12) is RAM by the timer number designation signal (i).
(This is a timer output register that stores the timer output state up to the previous time read from 21 and outputs this content. This is a logic unit that determines a new output state of the corresponding timer from f) and is composed of an AND element (4) and an OR element (5).

Next, the operation will be explained. A programmable controller constantly and repeatedly executes a control program containing timer instructions. When the programmable controller reaches the point where the timer command is executed, the timer number designation signal (i) of the relevant timer, the timer operation command signal (e) of the relevant timer, and the timer setting value (g) of the relevant timer are sent to this device. (First, RAM (2
), the current value of the timer up to the previous time and the timer output state up to the previous time are read out, and the respective presettable counters (
16) and is set in the timer output register (12). When the timer operation command signal (e) is "0", the presettable counter (16) is reset by the reset signal (c) inverted by the inverter (18). When the timer operation command signal (e) is "l", the reference clock section (17
) is “1”, the AND gate (19)
One pulse through the presettable counter (16)
The current value of the timer is incremented by 1. When the timer operation command signal (e) is "1" and the reference clock signal (0) is "0", the current value in the presettable counter (16) is held as is. Next, the presettable counter (16
) is compared with the sent timer setting value (g) using the comparator (9), and if the counter output (h) exceeds the timer setting value (g), the comparison output signal (j) is Let it be "l". In the AND element (4) and the OR element (5), the timer operation command signal (e) is "l" and the comparison output signal (j) is "
When the timer output (a) becomes "1", the new timer output (a) becomes "1".

The above operation is performed every time the timer instruction is executed. The reason why the timer output signal (f) is input to the OR element (5) is that even if the presettable counter (16) overflows and the counter output (h) becomes below the timer setting value (g) again, a new timer output is generated. This is to prevent (a) from becoming "0". When the above operations are completed, new timer output (a) and counter output (current value) (h) are written to RAM (2).

Note that the pulse of the reference clock signal (0) is set to the time width T1 for executing the entire program of the programmable controller once, so the reference clock signal (0)
During the period T0, there are several opportunities for one timer instruction to be executed. However, the reference clock signal (
0) is "l" only in degrees. As a result, all the timers whose timer operation command signal (e) is "1" have the period T of the reference clock. The current value is incremented by one for each time, and a timer operation is performed.

[Problem to be solved by the invention]

The conventional timer device for a programmable controller is configured as described above, and the width of the reference clock pulse is set to the time width T for executing the entire program of the programmable controller once. In addition, in this device, when the count UP condition of the timer presettable counter is satisfied when the timer instruction is executed, the presettable counter is incremented only once, so the timer reference clock (To) runs the sequence program once. If it is shorter than the execution time (T1) (To<TI), and the timer instruction that increments the presettable counter is located at a location where the reference clock has turned off, the count up condition is Even if ONL is used, the presettable counter is not incremented, and there is a problem that accurate timer operation cannot be performed.

Furthermore, since the counter's manual power is changed depending on the timer conditions, the circuit of the counter input section becomes complicated, making it difficult to control it.

This invention was made to solve the above problems, and provides a programmable controller that operates normally no matter what time the reference clock of the timer is set, and that has a simple control circuit for the counter input section. The purpose of this invention is to obtain a timer processing device.

[Means to solve the problem]

A timer device for a programmable controller according to the present invention includes a counter that counts clock signals generated at a constant cycle, a Δt register that stores a count value Δt of the counter for each instruction processing cycle of a sequence program, and a Δt register that stores a count value Δt of the counter for each instruction processing cycle of a sequence program. a counter reset means for resetting the counter after storing a numerical value; a timer current value register for storing the elapsed time from the start of the timer to the present; an adder for adding the values of the Δt register and the timer current value register; A timer setting value register that stores the timer setting value, a comparator that compares the above-mentioned timer setting value and the above-mentioned adder output, a comparison output register that temporarily stores the output of the above-mentioned comparator, the above-mentioned timer current value register, and timer setting. The counter, the adder, The comparator and output data selector are constructed in hardware.

[Operation] The counter in the present invention counts clock signals generated at a constant period, the Δt register stores the counted value Δt of the counter for each instruction processing cycle of the sequence program, and the counter reset means stores the counted value in the Δt register. After storing, the above counter is reset, the timer current value register stores the elapsed time from the timer activation to the present, the adder adds the values of the above Δt register and the timer current value register, and the timer setting value register The timer setting value is stored, the storage unit outputs the above timer setting value and the above adder, the comparison output register temporarily stores the output of the above comparator, and the output data selector outputs the above timer current value register and timer setting value register. Then, one of the zero value, timer set value, timer current value, and timer current value Δt is selected as the output of the timer current value according to the register conditions of the comparison output register.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. It should be noted that the same reference numerals as those in the conventional example indicate the same or similar elements.

In Figure 1, (1) is the arithmetic processing unit of the programmable controller, and (2) is the timer current value storage area that stores the current value of the timer corresponding to each address and the timer output state corresponding to that address. This is a RAM provided with a timer output state storage area for storing. (11) is a timer operation command register that temporarily stores the timer operation command signal sent from the arithmetic processing unit (fl), and (12) is a timer operation command register in which the arithmetic processing unit (1) uses the timer number designation signal (i) to read the RAM (
21 is a timer output register that temporarily stores the previous timer output state read out, (13) is a timer setting value register that temporarily stores the corresponding timer setting value sent from the calculation processing section (1), and (14) is a calculation This is a timer current value register that temporarily stores the previous timer current value read out from RAM (2) by the processing unit (1) in response to the timer number designation signal (i).

(15) is a clock signal (
k) is a Δt register that temporarily stores the value of the timer current value (ql) of the timer current value register (14) and the adder (10).
are added and output as an added output value (h).

This addition output value (h) is compared with the timer setting value (g) of the timer setting value register (13) by the comparator (9), and the result is stored as a binary signal in the comparison output register (8). Ru. (16) is a counter that clocks the clock signal (k) output from the reference clock section (17). This counter (16) is reset by a reset signal (C) outputted from the control circuit (7) every time the sequence program (11) Durham ends.

The timer operation command signal (e), timer output signal (f), and comparison output signal (j), which are the outputs of these registers (11) to (5), are composed of an OR element (5) and an AND element (4). The output is used as the new timer output (a). Furthermore, these timer operation command signal (e), timer output signal (fl), and comparison output signal (j) are input to the output data selector (6), and depending on these conditions, 0, timer setting position (gl, timer Present value(
q), the added output value (h) is selected and output as a new timer current value output (r).

The details of the output data selector (6) as an output selection circuit are shown in the configuration diagram of the output data selector (6) in FIG. In FIG. 3, n indicates that the timer setting value register (13) and the timer current value register (14) are n-bit registers, and corresponding to the n bits, the gate elements (61) to ( This shows that n logic circuits (LL) consisting of (67) are required.

In addition, (3) is an input/output gate that mediates data to be accessed between the arithmetic processing unit (1), RAM (2), and (12), and the input/output timing is determined by the gate signal ( b). The control circuit (7) also controls the timing of temporary storage in each register using the latch signal (d).

The operation will be explained below. The programmable controller constantly and repeatedly executes a sequence program containing timer instructions. When the programmable controller I/roller comes to the point where the timer instruction is executed, the arithmetic processing section (1) of the programmable controller outputs the timer number designation signal (i) of the relevant timer, and the current value of the relevant timer is stored from the RAM (2). Read out the timer output status 7, read out the timer operation command signal and timer setting value from the above sequence program, and read out these signals (bl is the input/output gate (
3), and the latch signal (d) output from the control circuit (7).
) is stored in the corresponding registers (ll) to (14). Further, the clock signal Fk) output from the reference clock section (17) is counted by the counter (16). At that time, before executing the sequence program,
This counter (16) is reset by the reset signal (C) output from the control circuit (7), and at the end of the sequence program, the Δt register (I5) is reset by the latch signal (dl) output from the control circuit (7). ).In this way, the time Δt for one execution of the sequence program is stored in the Δt register (15).

Next, the contents of the timer current value register (14) and the Δt register (15) are added by an adder (10). Adder +101
The addition output value (h) of is determined by the timer setting value (h) by the comparator (9).
g) and the timer setting value (gl is the addition output value (h
If it is smaller than l, "1" is stored in the comparison output register (8), and if it is larger, "0" is stored in the comparison output register (8). The new timer output (a) is when the timer operation command signal (e) is "1" (timer ON) and the previous timer output signal (f) is "]"
[Timer count IIP completed] or comparison output signal (j
) becomes "l" when it is "l" (timer count UP).

Otherwise, "0" is output. The above logic is realized by an AND element (4) and an OR element (5).

In addition, the current value output (r) of the new timer is determined by the output data selector [6] according to the conditions of the timer operation command signal (e), the previous timer output signal (f), and the comparison output signal (j). Either the setting position (g), the previous timer current value (q), the addition output value (h) (previous timer current value (q) + ΔL), or 0 is selected.

To explain the details, the conditions and outputs correspond as shown in the relationship diagram of the input conditions and output data in the output data selector (6) in FIG. In other words, the timer operation command signal (e
) is “0” (timer 0FF), the current value is output (1-1
becomes “0”, and the timer operation command signal (e) becomes “1” (
In timer ONI, the previous timer output signal (f) is “1”.
“If (timer count has been UP), the current value output (r) will be the previous timer current value (q). Also, if the timer operation command signal (e) is “l” (timer ON), the previous timer current value (q) is “0” (timer not counted UP/operating)
Then, the comparison output signal (j) is "0" (timer not counted)
P), the current value output (r) is the addition output value (h) (L to the previous current value 10), and the comparison output is "1" (timer count U
P), the timer setting value (gl) is output respectively. Figure 3 shows a circuit that realizes the above contents with H/W (
15) It is.

Finally, the arithmetic processing unit (1) sends a timer number designation signal (
It outputs the current value of the new timer (r) and the new timer output (a) through the input/output gate (3).
It is written in the address area of RAM (2) corresponding to the timer number designation signal (i).

In the above embodiment, the logic circuit for outputting the new timer output (a) is composed of an AND element (4) and an OR element (b).
), but this may also be constructed using a negative logic circuit such as a NAND element or a NOR element.

Further, in the above embodiment, the adder (10) was used to obtain the current value of the timer, but instead, a subtracter was used to subtract Δt from the current value (ql) of the timer. The output may be compared with "0" by a comparator (9) and a comparison output signal (j) may be output.

[Effects of the Invention] As shown in H-H above, according to the present invention, a counter that counts clock signals generated at a constant cycle, and a count value Δt of the counter (16) and a timer are calculated for each instruction processing cycle of a sequence program. After startup, an adder that adds the value to the timer current value indicating the elapsed time up to the present time, a comparator that compares the timer setting value and the output of the above adder, the output of the above comparator, the above timer current value, and the timer Based on the set value, output as the new timer current value to zero value, the above timer setting value, timer current value, and timer current value + Δt
Since the counter, adder, comparator, and output data selector are configured in hardware, accurate timer operation is possible, as well as timer input control. This has the effect of simplifying the configuration of the circuit section and allowing the user to freely select the reference tarok.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a timer device of a programmable controller according to an embodiment of the present invention, FIG. Figure 3 shows H of the output data selector.
/■ Block diagram, FIG. 4 is a block diagram of a timer processing device of a conventional programmable controller, and FIG. 5 is a counter input timing diagram of a conventional example. In the figure, (1) is an arithmetic processing unit, (2) is a RAM, (
3) is an input/output gate, (6) is an output data selector, (7
) is a control circuit, (8) is a comparison output register, (9) is a comparator, (lO) is an adder, (11) is a timer operation command register,
(12) is the timer output register, (13) is the timer setting value register, (14) is the timer current value register, (15) is the Δt register, (16) is the counter, (17) is the reference clock section, (
a) is the new timer output signal, fb) is the gate signal, (
c) is a reset signal, fd) is a latch signal, (e) is a timer operation command signal, [f] is a timer output signal, (g) is a timer setting value, (h) is an addition output value, (i) is a timer A number designation signal, (jl is a comparison output signal, fk) is a clock signal, (q) is a timer current value, and (r) is a current value output signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A counter that counts clock signals generated at regular intervals, a Δt register that stores the counted value Δt of the counter for each instruction processing cycle of the sequence program, and a counter reset that resets the counter after storing the counted value in the Δt register. a timer current value register for storing the elapsed time from the start of the timer to the present; an adder for adding the values of the Δt register and the timer current value register; and a timer setting value register for storing the timer setting value. , a comparator that compares the timer setting value and the output of the adder, a comparison output register that temporarily stores the output of the comparator, and a timer according to the register conditions of the timer current value register, timer setting value register, and comparison output register. Equipped with an output data selector that selects the output of the current value from zero value, timer setting value, timer current value, and timer current value + Δt, and the counter, adder, comparator, and output data selector are configured in hardware. A timer device for a programmable controller, characterized in that: