JPH032941A - Picture memory device - Google Patents

Abstract

PURPOSE:To read out the picture data in a short access time without increasing the number of complicated peripheral circuits nor increasing the power consumption by reading out the picture data on a designated position of a storage means together with the adjacent picture data. CONSTITUTION:The n-bit picture data inputted via an input means 106 is written into a storage means 101 via a writing means 104 with the adjacent relation kept among the picture elements of the picture data. When the written picture data is read out, (m) pieces of reading means 105a - 105m read out the picture data on an optional designated position (m) of the means 101 and those picture data on (m - 1) positions adjacent to the position (m). These read picture data are sent to an output means 107. Thus plural pieces of adjacent picture element data are read out at one time with a single reading access. As a result, the time required for reading the picture data out of the means 101 is extremely shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) This invention relates to a memory device for digital image processing.

(Conventional technology) 'In recent years, digital image processing technology has developed rapidly.

In digital image processing, it is possible to store and reproduce several scanning lines of image signals in semiconductor memory and process them.
It has become possible to perform real-time processing between lines and between fields (or frames), which was difficult with conventional analog signal processing technology.

Among such semiconductor IC memories, those having a capacity for one line are called field memories, and these image memories are available as semiconductor chips. Current television sets use logic LSIs that perform signal processing.
Separately, the reality is that multiple semiconductor memory chips are mounted, and in terms of processing speed and space, it is desirable to house the image memory described above in the same chip as the LSI that performs signal processing. There is a strong demand to speak. In fact, logic LSI
A variety of image memories that can be built into a computer have been developed, and an increasing number of recent LSIs for image signal processing have built-in image memories.

A two-dimensional filter is an example of digital image signal processing using an image memory. In such a filter, the calculation shown in FIG. 4(c) is performed between the 3×3 pixel image data shown in FIG. 4(a) and the coefficient data shown in FIG. 4(b). By doing this, two-dimensional filtering is performed.

Here, in the digital image processing described above, data of a certain pixel of an image and data of pixels adjacent to that pixel may be read out from the image memory.

However, generally, the data of each pixel of the image is written in the image memory without maintaining the adjacency relationship of each pixel, so when reading the data of the adjacent pixel, it is necessary to read out the data of the adjacent pixel. In the case of a filter, 02 memory accesses are required, which has the drawback of requiring a considerable amount of access time.

(Problem to be Solved by the Invention) In this way, in the conventional IC memory, as clearly shown when used in a two-dimensional filter, etc., in order to obtain data in an area of nXn pixels, it is necessary to use the memory n2 times. The drawback is that it requires access and takes a lot of time to process.

This invention was made to address the above-mentioned drawbacks of conventional devices, and by simply providing a simple peripheral circuit to the currently developed memory cell array, it is possible to avoid an increase in the area of the memory cell or the increase in power consumption. <The object is to provide an image memory device that can read image data in a shorter access time than conventional ones.

[Structure of the invention]

(Means for Solving the Problems) In order to solve the above problems, the image memory device of the present invention includes a storage means for storing digitized n-bit image data, and an n ( 1m
an input means having terminals, an output means having n×m terminals, and a storage means for storing the n-bit image data inputted from the input means at a designated position of the storage means while maintaining the adjacency relationship of each pixel of the image. at least m for guiding m In n bits of image data from an arbitrary specified position in each bit of the storage means and (m-1) positions adjacent to the specified position to the output means; The present invention is characterized in that the image data at the specified position of the storage means is read out together with (m-1) adjacent image data.

(Operation) In the apparatus of the present invention, the n-bit image data inputted through the input means is first written into the storage means by the writing means while maintaining the adjacency relationship of each pixel of the image. Next, when reading out the image data written in this way, the image data at any specified position m in the storage means and (m-1) positions adjacent to this position are read out by m reading means. Read and lead to output means. In this way, by reading out a plurality of pieces of adjacent pixel data at once with one read access, the time required to read out image data from the storage means is greatly reduced.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an image memory device according to an embodiment of the present invention. In the figure, 101
is a 1-bit memory cell array, and although not shown, n cells are provided to store a total of n bits of image information. Note that in the case of image data of 1 bit for self and black, only one memory cell array 101 is required for 1 bit, and therefore n is an integer of 1 or more.

102 is a row address decoder for reading/writing, 103 is a column address decoder for reading/writing (hereinafter referred to as address decoder), and 104 is n.
Bit image data writing circuit, 105 a to 105
m represents m data read circuits for reading data stored in each memory cell array 101. In addition, read/write combined row and column address decoder 1
02.103 is generally built into each memory cell array 101. Additionally, the address decoder 102.1
03 and the data writing circuit 104 constitute a writing means to the memory cell array, and this writing means writes n-bit image data to the memory cell array 101 while maintaining the adjacency relationship of each pixel of the image. ing. and address decoder 102.10
3 and the data read circuit 105 constitute means for reading data from the memory cell array. In this embodiment, the data write circuit 104 and the data read circuit 105 are provided in common for each memory cell array 101, so the data write circuit 104 and the data read circuit 105 are provided in common for each memory cell array 101.
There is one data reading circuit 105 and m data reading circuits 105.

Furthermore, 106 is an input means for inputting n-bit image information to the memory cell array 101, and specifically, it is composed of n input terminals r.corresponding to n-bit information. Reference numeral 107 is an output means for outputting m pieces of data from each memory cell array 101, and is composed of a total of rn x n terminals. Note that the row address decoder 10
The Y address signal 108 is input to the column address decoder 2, and the X address signal 109 is input to the column address decoder 103.
Specify the address (a, b) of the memory cell array 101. Also, write and read circuits 104.105
A control signal 110 is input to control the operation of each circuit.

Next, the operation of the above device will be explained.

FIG. 2 is a diagram conceptually showing a method of inputting image data to the above device. In the device of this invention, the input means 106
The n-bit image input signal is sent to the memory cell array 1 via
When writing to 01, the old write circuit 104 writes the second
As shown in the figure, information on each pixel 202 of an image 201 is basically stored in each memory cell 203 of the memory cell array 101 while maintaining the adjacency relationship between the pixels. be exposed.

Next, a reading operation of the image data written to the memory cell array 101 as described above will be explained. To make the explanation easier to understand, it is assumed here that one frame of image data has a configuration of 8×8 pixels×1 bit, and adjacent 3×3 pixels are extracted from the frame. In accordance with this condition, FIG. 3 shows a block diagram of an apparatus that is a more specific version of the embodiment shown in FIG. 1.

In FIG. 3, numeral 301 is a memory cell array having an 8×8×1 bit configuration, and has a total of 84 memory cells 300 as shown. 302 is a read/write row address decoder, and 303 is a read/write row address decoder.
This column address decoder is also used for writing, and the row address decoder 302 receives a 3-bit Y address signal 3.
08, a 3-bit X address signal 309 is input to the column address decoder 303. 304 is a write circuit for writing 1-bit input data 306 from an input means (not shown) into the memory cell array 301; 305a is a read circuit for reading data from a memory cell at a designated address (a, b); 305b,
305c is the address (a-1, b) before and after the specified address (a, b) in the memory cell array 301.
), (a+1.b). Note that the readout circuit 305a
,b.

The 1-bit output data 307a, b, c from C is outputted to the outside via an appropriate output terminal (not shown).

310 is a write circuit 304 and a read circuit 305a,
It shows the input of control signals for controlling b and c.

Further, X and Y addresses a and b are input to column and row address decoders, respectively.

In the above device, as described above, during writing, image data is written into the memory cell at the address (a, b) specified by the writing circuit 304 while maintaining the adjacency relationship between each pixel of the image. In the conventional read method, the address decoder 302 reads all the memory cells in the specified row b in the same manner as in the conventional method, selects one of the rows with the column address decoder, and specifies the address (a, b). However, in the device of this embodiment, the specified
The circuit 30 also reads out a−1 and a+l before and after address a.
5b and 5c read and output simultaneously. By doing so, it becomes possible to read three adjacent pieces of data at once.

Therefore, by repeating this operation three times, 3×3 pixel data can be read out with three memory accesses.

As described above, while the conventional device described above required 9 memory accesses to read 3×3 pixel data, the device of the embodiment requires only 3 accesses, which significantly increases the access time. will be relaxed.

Note that in the above device, since a conventional single port memory can be used as the memory cell, the memory cell size can be reduced. Furthermore, in the embodiment shown in FIG. 1 above, the write circuit and the read circuit are provided in common for n memory cell arrays, but these circuits may be integrated into each memory cell array, depending on design convenience. Therefore, f can be selected carefully. Note that when integrated into a memory cell array, n write circuits and n×m read circuits are required corresponding to the number of bits of the memory cell array.

〔Effect of the invention〕

As described above, the image memory device of the present invention can read out image data in a shorter access time than conventional devices without increasing the number of complex peripheral circuits or increasing power consumption. An image memory device suitable for processing can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic tM configuration of an image memory device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the device in FIG. 1, and FIG. 3 is a more detailed diagram of the device in FIG. FIG. 4 is a block diagram showing an outline of the apparatus in which the tM structure of the two-dimensional filter is shown. 101, 102, 103, 104, 105, 106, 107, memory cell array, read/write row address decoder, read/write column address decoder, data write circuit, data read circuit, input means, output means, - -\, 5

Claims (1)

[Claims] Storage means for storing digitized n-bit image data, input means having n terminals for inputting image data, and output means having n×m terminals. , writing means for writing the n-bit image data inputted from the input means into a specified position of the storage means while maintaining the adjacency relationship of each pixel of the image; and an arbitrary specified position of each bit of the storage means; at least m reading means for guiding m sets of n-bit image data from (m-1) positions adjacent to the designated position to the output means;
An image memory device, characterized in that the image data at a specified position in the storage means is read out together with (m-1) adjacent image data.