JPH03286571A - Mos field-effective transistor - Google Patents

Abstract

PURPOSE:To allow holes generated near a drain region to escape from a barrier by built-in potential at a channel section to a source electrode side and prevent the accumulation near the source region by allowing a junction depth in the source region to have a shallow structure so that carrier tunneling may be produced. CONSTITUTION:A gate section comprises a gate length ranging from 0.1mum to 0.3mum and a 300nm thick electrode on a 5nm thick oxide film 4a. On both sides is formed a silicon nitride film side wall 6a. A source region comprises a high concentration N-type epitaxial layer 9 including 5nm thick high concentration impurities and a high concentration N-type impurity diffusion region 10 diffused by 5nm in a depth direction by lamp annealing treatment from there. A drain region comprises a high concentration N-type impurity dope region 8 diffused by 30nm in a depth direction by high dose ion implantation and a high concentration N-type impurity diffusion region 10a formed by lamp annealing treatment from there.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a MOS field effect transistor, and in particular to an S field effect transistor.
MOS type field effect transistor (MOSFE) with ○■ structure
Regarding T).

[Conventional technology]

In recent VLSIs, MOS field effect transistors with a gate length of about 08 μm are being used as the integration becomes higher and smaller. Furthermore, in a MOS field effect transistor formed on an SOI substrate, a single crystal layer with an SOI layer thickness of about 0.5 μm, which is easy to grow, has conventionally been used. However, the thickness of S○■ is 0.5 μm.
It has been known that when layers are used, the characteristics of the MOS field effect transistor deteriorate due to two-dimensional effects such as punch-through and short channel effects. However, by making the SOI layer thickness less than or equal to the maximum depletion layer thickness, 2
The reduction of dimensional effects and substrate floating effects has been proposed by J.P. Co1Co11n et al.
Electron Tebaishi 1 Shi9- (IEEE
TRANSACTION ON ELECTRO
N DEVTC8LETTER) Volume 24, No.
5 (published in 1987), 2577.

[Problem to be solved by the invention]

However, in the N-channel thin film 501MO8 field effect transistor, holes generated near the drain region cannot escape to the substrate side.

You will return to the train area side.

In addition, in an N-channel MOS field effect transistor, the channel is doped with a P-type impurity to suppress the two-dimensional effect, but in this case, the channel has a higher built-in potential than the source region. Holes are no longer able to escape efficiently to the source region, resulting in a decrease in drain current.

An object of the present invention is to provide a novel structure of a field effect transistor that can solve these conventional problems.

[Means to solve the problem]

The MO3 field effect transistor of the present invention has a structure in which the junction depth of the source region is shallow enough to cause carrier tunneling.

[Effect]

In the MOS field effect transistor of the present invention, by using a source region with a very shallow junction depth,
Holes can be extracted to the source electrode side by tunneling through the barrier created by the built-in potential. Therefore, the holes do not accumulate near the source region and are
A decrease in the drain current of the O6FET can be suppressed.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic sectional view showing an embodiment of the present invention.

The substrate is a silicon substrate 1 formed by thermal oxidation.
, an 8 μm silicon oxide film 2, and a 30 nm thick SOI layer (boron doped: 5×10”) on the silicon oxide film 2.
cm-3). The gate part has a gate length of 0.1 μm to 0.3 μm, and is formed of a 300 nm thick gate electrode 5 on a 5 nm thick gate oxide M4a, with silicon nitride film side walls 6a having a width of 1100 nm on both sides thereof. is formed. The source region is made of highly concentrated impurities (A s : 1020 cm) with a thickness of 5 nm.
-3), and a heavily doped N-type impurity diffusion region 10 which is diffused by 5 nm in the depth direction by a lamp annealing process. In addition, the train region is formed by high-dose ion implantation (A s
: 1020cm-”) 30nm in the depth direction
It is composed of a diffused heavily doped N-type impurity region 8 and a heavily doped N-type impurity region 10a formed by a lamp annealing process.

FIGS. 2(a) to 2(f) are schematic cross-sectional views showing the manufacturing process order of the method of manufacturing the structure of this example.

FIG. 2(a) shows a silicon oxide film 2 on a silicon substrate 1.
A silicon oxide film 4 is formed on the SOI layer 3 formed through
(5 nm) polysilicon film (100 nm) was sequentially deposited, followed by normal photoresist process and ECR (Elec
tron Cyclotron Re5onance)
The polysilicon film in the gate region is etched by a dry etching process to form a gate electrode &5.

FIG. 2(b) shows a state in which 1100 nm of silicon nitride film 6 for sidewalls has been deposited by the CVD method.

Next, as shown in FIG. 2(c), a silicon nitride film 6. Perform etching of silicon oxide M4. At this time, silicon nitride film side walls 6a or 1100n in width are formed in a self-aligned manner by a dry etching process on both sides of the gate part, and at the same time, gate oxide films 4a made of silicon oxide film 4 or silicon nitride film side walls are formed. 6a in a self-aligned manner.

Next, as shown in FIG. 2(d), a silicon oxide film mask 7 is formed on the side where the source is to be formed by a normal photoresist process, and using this as a mask, a high concentration impurity (As: 10"Ocm) is formed. -') is ion-implanted to form a heavily doped N-type impurity region 8 with a depth of 30 nm.
Thereafter, silicon oxide film mask 7 is removed.

This time, conversely, as shown in FIG. 2(e), the drain region side is masked with a silicon oxide film mask 7a, and MBE is performed.
Silicon containing a high concentration impurity (As 1020 cm-3) is selectively epitaxially grown on the region where the source is to be formed using the (Oolecular Beam Epitaxy) method to form a highly doped N-type epitaxial layer 9 with a thickness of 5 nm and 5 m. Then, silicon oxide film mask 7a is removed.

Subsequently, as shown in FIG. 2(f), lamp annealing is performed to activate the impurity, and the highly concentrated N-type impurity is diffused to a depth of 5 nm formed by thermal diffusion from the highly concentrated N-type epitaxial layer 9. A source region composed of a region 10 and a heavily doped N-type epitaxial layer 9, a heavily doped N-type impurity diffusion region 10a formed by thermal diffusion from a heavily doped N-type impurity region 8, and a heavily doped N-type impurity region A drain region consisting of 8 is formed.

〔Effect of the invention〕

As explained above, in the MO3 field effect transistor of the present invention, by using a source region with a very shallow junction depth, holes generated near the drain region can tunnel through the barrier created by the built-in potential in the channel region. By this, it is possible to extract the wire to the source electrode side,
It will no longer accumulate near the source area.

As a result, the drain current of the thin film SOIMO3FET is
This decrease is suppressed compared to the conventional thin film So IMO3FET.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view of one embodiment of the present invention, and FIG.
) to (f) are schematic cross-sectional views in the order of manufacturing steps showing a method for manufacturing an MO3 field effect transistor according to an embodiment of the present invention. 1... Silicon substrate, 2, 4... Silicon oxide film,
3...S○ layer, 4a...gate oxide film, 5...
Gate electrode, 6... Silicon nitride film, 6a... Silicon nitride film side wall, 7, 7a... Silicon oxide film mask, 8... High concentration N-type impurity doped region, 9
...Highly doped N-type epitaxial layer, 10.10a...
・High concentration N-type impurity diffusion region. ;...Niノ]n〃4ru2...Si1nokonna2Otohara3...5QIi 2 Karasu...Gate acid Ijie 5...Gate Denki j brush et al. ...Nitrided Shira 3F 8...High fiN type T-end hair doped Rei Ayu Saki 9...High f
jFiJ type epitaxial layer 10; to... Hikoyiki degree N type';

Claims (1)

[Claims] 1. A MOS field effect transistor having an SOI structure, wherein the junction of the source region has a depth sufficient to cause carrier tunneling. 2. The MOS according to claim 1, wherein the source region is composed of an epitaxial layer having a conductivity type impurity at a high concentration, and a high concentration impurity diffusion layer formed by diffusion from the epitaxial layer. type field effect transistor.