JPH03280091A - Color display circuit - Google Patents

Abstract

PURPOSE:To adjust an effective voltage applied to a display element and to optimize the balance of a color tone by thinning out the ON driving of data in display dot units. CONSTITUTION:For at least one of red, green, and blue color data, a generating means 1 for generating a thinned-out pattern in dot units is provided, the output of the thinned-out pattern generating means 1 is selected with the output of each color data, and the signal of this generating means 1 is respective color data. Thus, a thinning-out process for each dot as a minimum time unit is performed, a shift in thinning-out timing is made, frame by frame, and those are repeated at all times, so the entire display image plane can be thinned out uniformly and the effective voltage applied to the display element can be adjusted optionally. Consequently, the balance of the color toner can be easily be adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a color display circuit for a flat display device.

[Summary of the Invention] The present invention aims to provide a display circuit with good color hue balance in a flat display device using a conventional 8-color display method using an ON10FF control drive circuit. . That is, in order to express color, the brightness of red, green, and blue can be adjusted so that the optimum color tone is balanced. The brightness adjustment method optimizes the hue balance by distinguishing each color data based on how many times it is driven as display data within a unit time.

[Prior Art] FIG. 3 is a circuit configuration diagram showing a conventional eight-color display type flat display device system. In Figure 3,
41 is a personal computer, 42 is an interface circuit, and 43 is a flat display device such as a liquid crystal. Color data R, G, B from personal computer 41
, horizontal synchronization signal Hsyc, and vertical synchronization signal Vsyc are input to the interface circuit 42 . The interface circuit 42 generates color data DATA necessary for operating the flat display device from the video signal, and interface signals such as a shift clock signal CL2, a latch signal CLI, a frame signal FRM, and a polarity inversion signal M. This is a circuit for generating.

The flat display image N43 includes a liquid crystal display element, a display element using plasma, etc., and a drive circuit for driving the display element. Flat display image! The drive circuit of t43 outputs 0N10 F of the display for the input display data.
It only performs F drive operation. The flat display device 43 has red, green, and blue color filters electrodeposited or printed.
ITOi for liquid crystal display elements using photolithography
This is a color panel formed on the i-top. Conventionally, the color tone has been balanced by adjusting the filter thickness of each of the color filters or by changing the driving output of each red, green, and blue driver.

[Problem B to be solved by the invention] As stated above, the present invention solves the problem of turning on the conventional display dot.
10 FF When using a drive circuit for F display operation, the multi-gap method, in which the color film thickness is changed to improve the color tone balance of the color display, had poor yields because it was difficult to control the film thickness. . In addition, the method of changing the driving output voltage of the driver requires preparing a separate driver IC and bias voltage generation circuit for each color to adjust the driving voltage, resulting in multiple circuits, and Problems have arisen in that pattern design and implementation for alternately connecting the outputs of the LCD to the electrodes of the flat panel display device become extremely complicated.

[! ! Means for Solving the Problems 1 The present invention has been made in order to solve the above-mentioned problems. The solution to this problem is to optimize the balance of color tones by thinning data on a display dot basis and changing the frequency of ON drives to adjust the effective voltage applied to the display element. .

[Function] As mentioned above, since the thinning is done in units of display dots, which is the minimum time interval, it is possible to electrically adjust the brightness according to each color without causing flicker, thereby optimizing the color balance. be able to.

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1st
In the figure, 1 is a green thinning pattern generation circuit, 2 is a blue thinning pattern generation circuit, and 3 is thinning data Go.
- A register circuit for storing G7, 4 is a shift register circuit, 5 is a counter circuit, 6 is a decoder circuit, 71
-79 is an AND circuit, 8 is an OR circuit, 9 and lO are AND circuits
circuit, Sl is a set signal for setting thinned data Go-G7 in register 3, I) CK is a dot clock signal, Vsyc is a vertical synchronization signal, N2 is a set signal similar to the above, B, G, R are the same as above. The operation shown in FIG. 1 will be described in terms of zeroth order in which the color data, BD, GD, and RD output from the personal computer are composed of 0 or more color display data input to the interface circuit. The register circuit 3 receives thinned data Go-
G7 is input, and the thinned-out data Go-G7 is stored by a pulse generated by the set signal S1. The stored thinned-out data Go-G7 is output to the shift register circuit 4. The shift register circuit 4 sets the skipped data Go-G7 for each frame by the vertical synchronizing signal Vsyc. The set thinning pattern data Go-G7 is shifted every clock by the dot clock signal DCK and its output signal is input to the AND circuits 71-79. On the other hand, the vertical synchronization signal Vsyc is input to the counter circuit 5, and every nine counts, an AND circuit 11 generates a reset signal to reset the counter circuit 5, and its ECD output is input to the decoder circuit 6. One of the outputs of the decoder circuit 6 is °1'' and becomes the other input of the AND circuits 71-79.The outputs of the AND circuits 71-79 are input to the OR circuit 8, The output is ANDed with green color data G by an AND circuit 10. Therefore, the vertical synchronizing signal Vsyc
Since the "l" output of the decoder circuit 6 moves every time the signal , the signal in which the thinning pattern is shifted every frame is ANDed with the green color data G to become green display data. The blue thinning pattern generation circuit 2 also has the same configuration as the green thinning pattern generation circuit 1 and operates in the same manner. FIG. 2 shows a waveform diagram of a thinning pattern for explaining the embodiment of FIG. 1. FIG. 2 shows how the thinning pattern 9 shifts with respect to display dot numbers 1-21.

In the waveform diagram from Wl to W9, the “H” level is displayed as O.
The N and "L" levels mean that the display is OFF. That is, OFF driving is performed once every 9 dots. From W1 to W9, the thinning pattern is shifted one dot at a time for each frame (the dot position of the OFF drive is moved) and this is repeated over the entire screen, so that a flicker-free display state can be achieved.

[Effects of the Invention] As described above, according to the present invention, thinning is performed for each dot, which is the smallest time unit, and the timing of thinning is shifted for each frame (like W1 to W9 described above). However, since this process is always repeated, it is possible to thin out the cells uniformly over the entire display screen, and therefore, the effective voltage applied to the display element can be arbitrarily adjusted. Therefore, with the ability to adjust the color filter film thickness or change the drive voltage for each color using separate drive ICs and bias voltage circuits, complex problems can be solved and color balance easily achieved. It has great effects, such as being able to provide clear color display at low cost.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. Second
The figure is a thinning pattern generation waveform diagram showing an embodiment of the present invention. FIG. 3 is a diagram showing the system configuration of a conventional eight-color multicolor display device. 1, 2 ・ ・ 3 ・ ・ ・ ・ 4 ・ ・ ・ ・ 5 ・ ・ ・ 6 ・ ・ ・ 1-79 8 ・ ・ ・ ・ ・ ... Thinning pattern generation circuit...Register circuit...Shift register Circuit... BCD counter circuit... Decoder circuit... AND circuit... OR circuit 9°10, AND circuit BD. G.D. RD ・・More than blue, green, red display color data

Claims (1)

[Claims] 1) In a display method that displays color on a flat display device using a plurality of display data, at least one of the color data consisting of red, green, and blue color data is thinned out in dot units. It has a thinning pattern generating means for generating a pattern, and the output of each of the color data is
A color display circuit characterized in that the output of the thinning pattern generating means is selected, and the signal of the selected thinning pattern generating means is used as each color data. 2) The thinning pattern generating means includes a thinning pattern forming means for forming a pattern in which driving is thinned out in units of dots, a shifting means for shifting the timing of the output of the thinning pattern forming means, and a thinning pattern generating means for forming a pattern in which driving is thinned out in units of dots, a shifting means for shifting the timing of the output of the thinning pattern forming means, and an output of the shifting means at least every frame. 2. The color display circuit according to claim 1, further comprising select means for switching. 3) The color display circuit according to claim 1, wherein the hue balance of red, green, and blue can be changed by adjusting the thinning rate of the thinning pattern generating means.