JPH0327569A - Solid-state image-pickup device - Google Patents

Solid-state image-pickup device

Info

Publication number
JPH0327569A
JPH0327569A JP1161284A JP16128489A JPH0327569A JP H0327569 A JPH0327569 A JP H0327569A JP 1161284 A JP1161284 A JP 1161284A JP 16128489 A JP16128489 A JP 16128489A JP H0327569 A JPH0327569 A JP H0327569A
Authority
JP
Japan
Prior art keywords
gate electrode
electrode
overflow control
directly below
overflow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1161284A
Other languages
Japanese (ja)
Other versions
JPH07118529B2 (en
Inventor
Hiromasa Yamamoto
山本 裕將
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1161284A priority Critical patent/JPH07118529B2/en
Publication of JPH0327569A publication Critical patent/JPH0327569A/en
Publication of JPH07118529B2 publication Critical patent/JPH07118529B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To increase the amount of charge to be accumulated and improve sensitivity of a image-pickup device by reducing the channel width directly below a gate electrode as compared with that directly below an overflow control electrode. CONSTITUTION:A gate electrode 4 and an overflow control electrode 8 are formed in one piece and a width W2 formed below the electrode 8 is made longer than a channel width W1 below the electrode 4. The same voltage is applied to both the electrode 4 and 8 and the depth phi4 of a potential well directly below the electrode 4 is made slightly shallower than that phi8 of the potential well directly below the electrode 8. Thus, when there are many changes produced due to photo-electric conversion, the overflown charge directly below an accumulated gate electrode passes through the potential well directly below the electrode 8 into an overflow drain region 9, thus restricting blooming positively.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、固体撮像素子に関し、特に、受光領域におい
て発生した光電変換電荷を一旦蓄積ゲート電極下に蓄積
するタイプの固体撮像素子に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a solid-state imaging device, and particularly to a solid-state imaging device of a type in which photoelectric conversion charges generated in a light-receiving region are temporarily stored under a storage gate electrode.

[従来の技術] 第3図は、この種従来例の固体撮像素子の平面図であり
、第4図(a)、(b)は、それぞれ、第3図のIV 
a − IV a ’線、IVb−IVb ’線断面図
である。
[Prior Art] FIG. 3 is a plan view of a conventional solid-state image sensor of this kind, and FIGS. 4(a) and 4(b) are IV in FIG. 3, respectively.
It is a sectional view taken along the a-IVa' line and the IVb-IVb' line.

第3図、第4図に示されるように、従来の撮像素子にお
いては、P型半導体基板1内にN型受光領域2が設けら
れ、この受光領域に隣接して半導体基板上に絶縁膜3を
介してゲート電極4aが設けられており、そしてこの電
極に続いて電荷転送方向に向かって順に蓄積ゲート電極
5、トランスファゲート電@6が設けられている。トラ
ンスファゲート電極6の先には電荷転送部(その転送ゲ
ート電極の図示は省略されている)7が設けられている
。また、蓄積ゲート電極5に隣接して電荷転送方向と直
角方向にオーバーフロー制御電fi8aが設けられ、そ
の先の半導体基板1内にはN導電型のオーバーフロード
レイン領域9が形或されている。第3図において、実線
AにrIBまれた領域が活性領域であるが、この領域は
、P+型チャネルストッパあるいはロコス酸化膜くいず
れも図示を省略〉によって囲まれ、他の領域がら分離さ
れている。
As shown in FIGS. 3 and 4, in the conventional image sensor, an N-type light-receiving region 2 is provided in a P-type semiconductor substrate 1, and an insulating film 3 is provided on the semiconductor substrate adjacent to this light-receiving region. A gate electrode 4a is provided via the gate electrode 4a, and a storage gate electrode 5 and a transfer gate electrode @6 are provided sequentially in the charge transfer direction following this electrode. A charge transfer section 7 (the transfer gate electrode is not shown) is provided at the tip of the transfer gate electrode 6 . Further, an overflow control electrode fi8a is provided adjacent to the storage gate electrode 5 in a direction perpendicular to the charge transfer direction, and an N-type overflow drain region 9 is formed in the semiconductor substrate 1 beyond that. In FIG. 3, the region indicated by the solid line A is the active region, but this region is surrounded by a P+ type channel stopper or a LOCOS oxide film (both not shown) and is separated from other regions. .

この従来の固体撮像素子の第4図(a)および第4図(
b)の断面に沿った半導体基板表面のポテンシャル分布
を、それぞれ第5図(a)、第5図(b)に示す。受光
領域2で光電変換された電荷は、ゲート電極4a直下の
深さφ41のボテンシャル井戸を通って蓄積ゲート電極
5直下に蓄えられる。通常は、蓄積ゲート電極直下の電
荷はトランスファゲート電極6を介して電荷転送部7へ
送られ(トランスファゲート電極が電荷トランスファ動
作を行っているときの電極6下のポテンシャルを第5図
(a)において点線にて示す)た後、この電荷転送部内
を矢印方向に沿って出カ部へ向けて転送される。しがし
、光電変換された電荷量が多く、これを蓄積ゲート電極
下に保持しきれないときには、あふれた電荷はオーバー
フロー制御電極8a直下の深さφ8aのポテンシャル井
戸を通ってオーバーフロードレイン領域9へ流れ込む。
FIGS. 4(a) and 4(a) of this conventional solid-state image sensor
The potential distribution on the surface of the semiconductor substrate along the cross-section in b) is shown in FIGS. 5(a) and 5(b), respectively. The charges photoelectrically converted in the light receiving region 2 are stored directly under the storage gate electrode 5 through a potential well with a depth φ41 directly under the gate electrode 4a. Normally, the charge directly under the storage gate electrode is sent to the charge transfer section 7 via the transfer gate electrode 6 (the potential under the electrode 6 when the transfer gate electrode is performing a charge transfer operation is shown in FIG. 5(a)). (indicated by a dotted line), the charge is then transferred within the charge transfer section toward the output section along the direction of the arrow. However, when the amount of photoelectrically converted charge is large and cannot be held under the storage gate electrode, the overflowing charge passes through a potential well with a depth of φ8a directly under the overflow control electrode 8a to the overflow drain region 9. Flow into.

このような動作により、蓄積電荷のあふれ出しによるブ
ルーミングと呼ばれる動作不良を防いでいる。
This operation prevents a malfunction called blooming due to overflow of accumulated charges.

[発明が解決しようとする課題] 固体撮像素子においては、ブルーミングを抑制するため
に、ゲート電極4a直下のポテンシャル井戸の深さφ4
はり、オーバーフロー制御電極8a直下のポテンシャル
井戸の深さφ88の方を深くする必要があるが、従来の
固体撮像素子においては、ブルーミング抑制を全うする
ために、製造上のばらつきをも考慮してポテンシャル井
戸の深さの差が十分大きくなるようになされている。し
たがって、従来の固体撮像素子においては、蓄積ゲート
電極下に蓄積可能な光電変換電荷の量が減少し感度が低
下した。また、従来例においては、ゲート電極とオーバ
ーフロー制御電極とは別々の電源からの配線が必要とな
るので、配線が複雑となり、また配線を敷設するための
スペースを必要とした。
[Problems to be Solved by the Invention] In a solid-state imaging device, in order to suppress blooming, the depth of the potential well directly below the gate electrode 4a is set to φ4.
However, in conventional solid-state imaging devices, in order to completely suppress blooming, the potential well depth φ88 directly below the overflow control electrode 8a must be made deeper, taking into account manufacturing variations. The difference in depth of the wells is made to be sufficiently large. Therefore, in the conventional solid-state image sensor, the amount of photoelectric conversion charge that can be stored under the storage gate electrode is reduced, resulting in a decrease in sensitivity. Further, in the conventional example, the gate electrode and the overflow control electrode require wiring from separate power sources, which makes the wiring complicated and requires space for laying the wiring.

[課題を解決するための手段] 本発明による固体撮像素子は、受光領域で発生した光電
変換電荷を一時蓄積ゲート電極下に蓄積しこれをトラン
スファゲート電極を操作して電荷転送部へ送り込むタイ
プのものであって、受光領域と蓄積ゲート電極との間に
はその下を通過する電荷をコントロールするゲート電極
が設けられ、また、蓄積ゲート電極の近傍にはこの電極
下からあふれた電荷を吸収するオーバーフロードレイン
が設けられており、このオーバーフロードレインと蓄積
ゲート電極との間にはオーバーフロー制御電極が設けら
れれいる。
[Means for Solving the Problems] The solid-state imaging device according to the present invention is of a type in which photoelectric conversion charges generated in a light receiving region are temporarily accumulated under an accumulation gate electrode and sent to a charge transfer section by operating a transfer gate electrode. A gate electrode is provided between the light-receiving region and the storage gate electrode to control the charge passing under it, and a gate electrode is provided near the storage gate electrode to absorb the charge overflowing from under this electrode. An overflow drain is provided, and an overflow control electrode is provided between the overflow drain and the storage gate electrode.

そして、本発明の固体撮像素子の特徴とするところは、
ゲート電極とオーバーフロー制御電極とが電気的に接続
され、がっ、ゲート電極下におけるチャネル幅の方がオ
ーバーフロー制御電極下のそれより短くなされている点
である。
The solid-state image sensor of the present invention is characterized by:
The gate electrode and the overflow control electrode are electrically connected, and the channel width under the gate electrode is shorter than that under the overflow control electrode.

[実施例] 次に、本発明の実施例について図面を参照して説明する
[Example] Next, an example of the present invention will be described with reference to the drawings.

第1図は、本発明の一実施例を示す平面図、第2図(a
)は、そのn−n′線断面図であって、これらの図にお
いて、第3図および第4図の従来例と共通する部分には
同一の参照番号が付されているので重複する説明は省略
する。この実施例では、ゲート電極4とオーバーフロー
制御電fi8とが一体化されており、そしてオーバーフ
ローM#電極8下に形成されるチャネルの幅w2は、ゲ
ート電極4下のチャネルの幅w1より長くなされて5 6 いる。
FIG. 1 is a plan view showing one embodiment of the present invention, and FIG.
) is a sectional view taken along the line nn', and in these figures, the same reference numbers are given to the parts common to the conventional example shown in FIGS. 3 and 4, so duplicate explanations will be omitted. Omitted. In this embodiment, the gate electrode 4 and the overflow control electrode fi8 are integrated, and the width w2 of the channel formed under the overflow M# electrode 8 is made longer than the width w1 of the channel under the gate electrode 4. There are 5 6.

第2図(a)の断面の沿った半導体基板表面のポテンシ
ャル分布を第2図(b)に示す。
FIG. 2(b) shows the potential distribution on the surface of the semiconductor substrate along the cross section of FIG. 2(a).

ゲート電極4とオーバーフロー制御電極8には同一の電
圧が印加されるが、チャネル幅Wについてはゲート電極
直下のチャネル幅Wlがオーバーフロー制御電極8直下
のチャネル幅W2より短いため、狭チャネル効果により
ゲート電極4直下のポテンシャル井戸の深さφ4は、オ
ーバーフロー制御電極8直下のポテンシャル井戸の深さ
φ8より少し浅くなる。このため、光電変換された電荷
が多い時には、蓄積ゲート電極5直下のあふれた電荷は
オーバーフロー制御電極8直下のポテンシャル井戸を通
ってオーバーフロードレイン領域9へ流れ込む。よって
、確実にブルーミングを抑制することができる。このよ
うに両電極直下のチャネル幅に差をつけることにより両
電極下のポテンシャルの差を精度よくコントロールでき
るので、両電極に印加する電圧差によってポテンシャル
に差をつける場合のようにマージンをとる必要がなくな
り、蓄積ゲート電極4下に蓄積可能な電荷量を増加させ
ることができる。
The same voltage is applied to the gate electrode 4 and the overflow control electrode 8, but since the channel width Wl directly under the gate electrode is shorter than the channel width W2 directly under the overflow control electrode 8, the gate electrode 4 and the overflow control electrode 8 are applied with the same voltage. The depth φ4 of the potential well directly below the electrode 4 is slightly shallower than the depth φ8 of the potential well directly below the overflow control electrode 8. Therefore, when there is a large amount of photoelectrically converted charge, the overflowing charge directly below the storage gate electrode 5 flows into the overflow drain region 9 through the potential well directly below the overflow control electrode 8. Therefore, blooming can be reliably suppressed. In this way, by making a difference in the channel width directly under both electrodes, it is possible to precisely control the difference in potential under both electrodes, so it is necessary to take a margin like when making a difference in potential by the difference in voltage applied to both electrodes. Therefore, the amount of charge that can be stored under the storage gate electrode 4 can be increased.

また、このようにして作られる固体撮像素子では、ゲー
ト電極4とオーバーフロー制御電極8とに同一の電圧を
印加することができるので配線を1本減らすことができ
る。
Furthermore, in the solid-state imaging device manufactured in this manner, the same voltage can be applied to the gate electrode 4 and the overflow control electrode 8, so that the number of wiring lines can be reduced by one.

なお、以上の実施例では、P型半導体基板を用いたもの
であったが、これをN型半導体基板を用いたものに変更
することができる。さらに、N型(またはP型〉半導体
基板を用いP(またはN)型ウェル領域内に各素子を形
成するようにしてもよい。
In addition, although the above embodiment used a P-type semiconductor substrate, this can be changed to one using an N-type semiconductor substrate. Furthermore, each element may be formed in a P (or N) type well region using an N type (or P type) semiconductor substrate.

[発明の効果] 以上説明したように、本発明は、ゲート電極直下のチャ
ネル幅をオーバーフロー制御電極直下のそれより短くし
たものであるので、本発明によれば狭チャネル効果を利
用してオーバーフロー制御電極下のポテンシャル井戸の
深さをゲート電極下のそれより深くすることができ、ま
た、そのポテンシャル差を精度よくコントロールするこ
とができる。したがって、本発明によれば、従来例のよ
うに各電極への印加電圧にマージンを設ける必要がなく
なり、蓄積ゲート電極下に蓄積可能な電荷量を増加させ
、撮像素子の感度を向上させることができる。また、本
発明によれば、両電極に印加する電圧は一種類で済むの
で、電圧生成回路、電源配線を1個省略することができ
、回路、配線を簡素化することができる。
[Effects of the Invention] As explained above, in the present invention, the channel width directly under the gate electrode is made shorter than that directly under the overflow control electrode, so according to the present invention, overflow control is performed using the narrow channel effect. The depth of the potential well under the electrode can be made deeper than that under the gate electrode, and the potential difference can be precisely controlled. Therefore, according to the present invention, there is no need to provide a margin for the voltage applied to each electrode as in the conventional example, and it is possible to increase the amount of charge that can be stored under the storage gate electrode and improve the sensitivity of the image sensor. can. Further, according to the present invention, since only one type of voltage is required to be applied to both electrodes, one voltage generation circuit and one power supply wiring can be omitted, and the circuit and wiring can be simplified.

5・・・蓄積ゲート電極、   6・・・トランスファ
ゲート電極、  7・・・電荷転送部、    8、8
a・・・オーバーフロー制御電極、   9・・・オー
バーフロートレイン領域。
5... Storage gate electrode, 6... Transfer gate electrode, 7... Charge transfer section, 8, 8
a... Overflow control electrode, 9... Overflow train region.

Claims (1)

【特許請求の範囲】[Claims] 第1導電型の半導体基板表面に形成された第2導電型の
受光領域と、前記受光領域に隣接して半導体基板の表面
に絶縁膜を介して設けられたゲート電極と、前記ゲート
電極に隣接して設けられた前記受光領域で発生し前記ゲ
ート電極下を通過してきた光電変換電荷を蓄積するため
のポテンシャル井戸を形成する蓄積ゲート電極と、前記
蓄積ゲート電極の一辺に隣接して設けられ前記蓄積ゲー
ト電極下に蓄積された光電変換電荷の電荷転送部への転
送をコントロールするトランスファゲート電極と、前記
蓄積ゲート電極の他の一辺に隣接して設けられたオーバ
ーフロー制御電極と、前記オーバーフロー制御電極に隣
接して前記半導体基板表面に形成された第2導電型のオ
ーバーフロードレイン領域とを具備する固体撮像素子に
おいて、前記ゲート電極と前記オーバーフロー制御電極
とは電気的に接続されておりかつ前記オーバーフロー制
御電極下のチャネルの幅は前記ゲート電極下のそれより
長いことを特徴とする固体撮像素子。
a light-receiving region of a second conductivity type formed on the surface of a semiconductor substrate of a first conductivity type; a gate electrode provided on the surface of the semiconductor substrate adjacent to the light-receiving region with an insulating film interposed therebetween; and adjacent to the gate electrode. a storage gate electrode that forms a potential well for storing photoelectrically converted charges generated in the light-receiving region and passed under the gate electrode; and a storage gate electrode that is provided adjacent to one side of the storage gate electrode. a transfer gate electrode that controls the transfer of photoelectric conversion charges accumulated under the storage gate electrode to the charge transfer section; an overflow control electrode provided adjacent to the other side of the storage gate electrode; and the overflow control electrode. and a second conductivity type overflow drain region formed on the surface of the semiconductor substrate adjacent to the semiconductor substrate, wherein the gate electrode and the overflow control electrode are electrically connected, and the overflow control electrode is electrically connected to the overflow control electrode. A solid-state imaging device characterized in that the width of the channel under the electrode is longer than that under the gate electrode.
JP1161284A 1989-06-24 1989-06-24 Solid-state image sensor Expired - Fee Related JPH07118529B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1161284A JPH07118529B2 (en) 1989-06-24 1989-06-24 Solid-state image sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1161284A JPH07118529B2 (en) 1989-06-24 1989-06-24 Solid-state image sensor

Publications (2)

Publication Number Publication Date
JPH0327569A true JPH0327569A (en) 1991-02-05
JPH07118529B2 JPH07118529B2 (en) 1995-12-18

Family

ID=15732184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1161284A Expired - Fee Related JPH07118529B2 (en) 1989-06-24 1989-06-24 Solid-state image sensor

Country Status (1)

Country Link
JP (1) JPH07118529B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5817217A (en) * 1993-12-07 1998-10-06 Garidel; Jean-Paul Machine for confining a primary fluid by means of a secondary fluid in the vapor phase

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5817217A (en) * 1993-12-07 1998-10-06 Garidel; Jean-Paul Machine for confining a primary fluid by means of a secondary fluid in the vapor phase

Also Published As

Publication number Publication date
JPH07118529B2 (en) 1995-12-18

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