JPH03274726A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a hole for reliably connecting with a diffusion region and to ensure high yield even if alignment accuracy of a patter during projection exposure is low by forming a high step in a first connection hole, which reaches one diffusion region using a conducting film formed simultaneously with a conductive buried film as a dammy and by forming a conductive film and a conducting buried film in a contact part. CONSTITUTION:After a word line 3 is formed, a poly-Si patterns 8, 28 are formed on a first layer insulating film 27, and after a second insulating layer 9 is deposited thereon, the layer insulating films 27, 9 in a formation place of connection hole for connecting a region which becomes a capacitor electrode to one diffusion layer of a substrate, and a conductive film 8 or a dammy of poly-Si patterns are etched and removed, a memory capacitor is formed. Thereby, an electrode area of the capacitor electrode increases. Since first and second connection holes 40, 42 are formed on each of one and the other diffusion layer by providing the poly-Si patterns 8, 28, an alignment margin of formation of contact holes 40, 42 in a capacitor electrode contact part and a bit-line contact part can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device with a wiring width of 08
The present invention relates to a method for producing highly integrated semiconductor devices of micrometers or less with high yield.

(b) Prior Art The prior art and its problems will be explained using diagrams illustrating the configuration of main parts of a semiconductor substrate.

In the conventional technology, as shown in FIGS. 3(a) and 3(b), a first lower layer wiring (diffusion layer) 32 formed by diffusion is used.
After forming the second lower layer wiring 33 on the semiconductor substrate 31 having the same structure, an interlayer insulating film 34 of 5iOz or the like is deposited, and then a connection hole 34a is opened by performing treatments such as photolithography and etching. The upper layer wiring 35 is formed through this connection hole 34a, and the wiring between the upper layer and the lower layer is electrically connected.

In particular, if the upper layer wiring 35 is made of metal η, such as A1,
When the first lower layer wiring 32 is formed on the substrate 31 and is made of an fco diffusion layer, if the connection hole 34a is not positioned with respect to the diffusion layer which is the first lower layer wiring 32, Fourth
As shown in the figure, there is a possibility that the metal wiring 35 is short-circuited with the substrate 31 at the portion indicated by the arrow Q in the figure. However, as shown in FIG.
In order to make connections with
A polycrystalline Si film 36 doped with impurities at a high concentration is coated, and a polycrystalline Si film 36 is formed between the metal wiring 35 and the substrate 31.
This can be prevented by sandwiching 36. That is, short circuits between the substrate 31 and the metal wiring 35 are prevented by covering the ends of the diffusion regions exposed in the connection holes 34a with a polycrystalline Si film 36 doped with impurities at a high concentration. This is because the highly doped impurities from the polycrystalline Si film 36 diffuse toward the substrate, so even if the polycrystalline Si film 36 is deposited at the edge of the diffusion region, short circuits will not occur. to cause.

(c) Problems to be Solved by the Invention The method of covering the connection hole 34a with the polycrystalline Si film 36 as described above has two major problems.

l) The distance between connection holes cannot be reduced.

For example, it plays the role of covering the board 3I at the connection hole part.
Consider the case where polycrystalline Si@36 is processed by etching. If the photoresist that defines the shape of the polycrystalline S1 film 36 after processing is not in the predetermined position and a part of the substrate is exposed, etching the polycrystalline Si film 36 in this state will cause the substrate to be etched. Since it is also made of silicon, the exposed portion is etched as shown by the arrow R in FIG. Such etching of the substrate causes defects such as junction leakage. Therefore, the end of the polycrystalline Si film 36 above the connection hole 34a must be at a certain distance d (from 0°1 μm to 03 μm) from the exposed area on the substrate.
) [Refer to Figure 9] If it is not located far away, it will not be affected.

On the other hand, the lower limit of the distance between polycrystalline SL dot patterns is determined by the resolution of the projection exposure machine. Therefore, the minimum distance between the connection holes is approximately 2@C0.2 .mu.m to 0.6 .mu.m of the distance d in addition to the resolution of the projection exposure machine (approximately 0.6 .mu.m). In other words, the distance L between the connection holes 34a and 34c;
See No. 9 Resolution of projection exposure machine (approximately 0.6 μm)
It is impossible to get that close.

2) It is difficult to form connection holes in a self-aligned manner.

As shown in FIG.
4b and etching the portion where the connection hole is to be formed to a thickness corresponding to the thickness of the interlayer insulating film 34b, thereby connecting to the substrate surface in a self-aligned manner with respect to the second lower layer wiring 33. A hole is formed.

However, if there are multiple upper wiring layers 35 to be connected to the substrate 31, the interlayer insulating films 34b, 3
4c and the polycrystalline Si film must be deposited multiple times as shown in FIG. 8, and when multiple layers are deposited in this way,
The thickness of the interlayer insulating film above the connection hole will be larger than that of the interlayer insulating film on the lower layer wiring, and the space above the connection hole will be filled with the insulating film, making it impossible to form the connection hole in a self-aligned manner. It becomes possible.

The present invention was made in view of the above-mentioned problems, and therefore,
To provide a method for manufacturing a semiconductor device that can form a connection hole that can reliably connect to a diffusion region of a semiconductor substrate, and that can also have a high yield even if the overlay accuracy of patterns during projection exposure is low. It is.

B.) Means and Effects for Solving the Problems The present invention provides a method for forming a plurality of upper layer interconnects deposited on a semiconductor substrate having a lower layer interconnect consisting of a gate portion provided with a sidewall and a diffusion region between the gate portions. , when forming a first connection hole for connecting to one diffusion region and a second connection hole for connecting the above-mentioned upper layer wiring to the other diffusion region via a conductive buried film, (i) After sequentially laminating a first interlayer insulating layer and a resist layer over the entire surface of the semiconductor substrate including the gate portion, and forming a resist film with a predetermined number of turns, (i
1) Using the resist film as a mask, only the first insulating layer on the other diffusion region was removed until at least a portion of the surface of the other diffusion region was exposed, and then the resist film was removed. After that, a conductive layer made of a material whose etching rate is slower than that of the first interlayer insulating film is laminated on the entire surface of the semiconductor substrate including the remaining first interlayer insulating film, and a resist film in a predetermined pattern is formed, (iii) The conductive layer is etched using the resist film as a mask, leaving the conductive film on one diffusion region via the first interlayer insulating film, and electrically connecting the conductive layer on the other diffusion region. (iv) sequentially stacking a second interlayer insulating layer and a resist layer over the entire surface of the first interlayer insulating film including the conductive film and the conductive embedded film; After forming a resist film with a predetermined pattern, (v) using the resist film as a mask, the second interlayer insulating layer and the conductive film on one diffusion region are sequentially etched, and the first interlayer insulating layer immediately below the conductive film is etched.
removing the interlayer insulating film until at least a portion of the surface of one diffusion region is exposed, thereby forming a first connection hole;
(\1) Form a first upper layer wiring part on the semiconductor substrate excluding the other diffusion region with a low C, and bury the first upper layer wiring part in the first!4j connection hole,011) Furthermore, After sequentially laminating a third interlayer insulating layer and a fourth interlayer insulating layer for planarization over the entire surface of the semiconductor substrate including the upper wiring part,
a second interlayer insulating film on the conductive buried film and a third interlayer insulating film on the conductive buried film; removing each fourth interlayer insulating layer to form a second connection hole; (vii)
This method of manufacturing a semiconductor device is characterized in that a second upper layer wiring portion having a predetermined pattern is formed over the entire surface of the fourth interlayer insulating film including the second connection hole.

That is, the present invention provides a method for connecting a plurality of upper layer wirings deposited on a semiconductor substrate having a lower layer wiring consisting of a gate portion with a sidewall and a diffusion region between the gate portions to one diffusion region. When forming a first connection hole and a second connection hole for connecting the above-mentioned upper layer wiring to the other diffusion region via a conductive buried film, a conductive buried film and a conductive buried film are formed in the first connection hole. By using a thin conductive Li film formed at the same time as a dummy, a high step extending to one of the diffusion regions is formed, thereby increasing the area of the first upper layer wiring portion. The first connection hole and the second
When forming the connecting hole, a conductive film and a conductive buried film are formed on each contact part, so that the positioning margin can be increased depending on the contact part, and the pattern during projection exposure can be improved. High yield can be expected during production because the overlay accuracy is low.

The first connection hole in the second invention is, for example, as shown in FIG. 1(d).
As shown in FIG. 3, the second interlayer insulating layer 9, the conductive film 8, and the first interlayer insulating film are etched by RIE anisotropic etching using the resist pattern 30 formed by projection exposure in the first connection hole-shaped open region R as a mask. It is formed by sequentially etching 27. This connection hole, as shown in Figure 1(e),
The bottom surface constitutes the interface 1a with the surface of one diffusion region, and the upper opening lb constitutes the upwardly protruding flange portion of the second interlayer insulating film 29 and sag. Therefore, the height of the upper opening 1b and the bottom surface 1a is A high level difference having a height H is formed as shown in FIG. 1(e) and FIG. 2.

Therefore, the conductive film 8 acting as a dummy: FIG.
d)] are removed when the connection hole 40 is formed, and the wiring area can be increased by that amount in the depth direction.

Therefore, the area of the wiring portion of the first upper layer wiring portion disposed along the inner surface of the first connection hole is increased. That is, by forming the contact portion between the first upper layer wiring portion and one of the diffusion regions to have a high step, the area of the first upper layer wiring portion can be increased.

The conductive layer in this invention is preferably one whose etching rate is slower than 5iOzl when removed by anisotropic etching such as RIE, and polycrystalline silicon is the most preferable. Further, a laminated film of a silicide film such as WSi and a polysi film is also preferable.

Then, the conductive layer is formed by, for example, projection exposure and etched using an anisotropic RIE etching method using a photoresist pattern to form a conductive buried film on the conductive film.

That is, a conductive buried film pad is formed in the contact portion of the second upper layer wiring portion to increase the overlapping margin when the second connection hole is formed. Furthermore, a conductive film is formed on the contact portion of the first upper layer wiring portion to increase the overlapping margin when forming the first connection hole. Moreover, this conductive film acts as a dummy and is removed when the first connection hole is formed. This is the most important feature of the present invention. Therefore, the first upper layer wiring portion is removed by that amount, and the first upper layer wiring portion is removed by the amount removed.
The wiring area of the upper layer wiring section a can be increased.

The first to fourth interlayer insulating layers in this invention include 5
Preferred examples include materials such as 1ft and SiN.

(e) Examples The present invention will be described in detail below based on examples shown in the drawings. However, this invention is not limited by this.

In FIG. 1(g), a DRAM (MOS transistor) is separated by a SiO2 thermal oxide film 2 with a diameter of about 0.4 μm, and a Si substrate i with a thickness of 10 μm on the substrate.
A polycrystalline Si film (a gate wiring which is a word line as a second lower layer wiring) 4 with a thickness of about 3000 nm is formed by diffusing P at a high concentration through a gate oxide film 3 of about 0.0 nm, and this gate wiring. CVOW on the top and side surfaces of S10. After depositing
Si◯ spacers 5 and 6 formed by RTE anisotropic etching, and S◯◯ film as a first interlayer insulating film formed on this gate wiring 4 to a thickness of about 2 μm by CVD method. 27, a first connection hole 40 formed on one diffusion region with a high step difference in length H from the upper opening 1b to the bottom surface of about 1.2 μIT, and a first connection hole 40 formed on one diffusion region with a height difference of about 1.2μIT from the upper opening 1b to the bottom surface, and a A polycrystalline Si film 28 of approximately 0.05 μm in thickness is formed on the Si substrate to a thickness of 0.1 μm using the CVD method in the region excluding the second connection hole 42 as a gamma bit line connection hole and the other diffusion region.
SiO*())'l-21l- deposited on the order of μm
Edge 1 [29] The first upper layer wiring section 41 provided through the first connection hole 40 and the first interlayer insulation @ 29 on the first upper layer wiring section and on the other diffusion region were laminated in sequence. Each layer was deposited to a thickness of approximately 0.1 μm using the CVD method.
The 311th layer of this 5ift was deposited using the CVD method to a thickness of about 0.3μm and the second flattening layer.
Interlayer insulating film I4 and upper layer WSi with a thickness of 0.3 μmaK
A pit line t as a second upper layer wiring portion is formed by projection exposure and anisotropic etching of RIE after depositing a film.
5 and becomes the main character.

Furthermore, the first upper layer wiring section 41 is made of a polycrystalline S layer doped with P at a high concentration and having a thickness of about 500 A, which is disposed in the lower layer.
A capacitor lower electrode 10 is formed by depositing an i film by CVD and patterned by projection exposure and anisotropic etching by RIE, and a capacitor insulating film 11 made of an SiN film with a thickness of about 80 cm is interposed between the capacitor lower electrode 10 and the upper layer. A polycrystalline Si film doped with P at a high concentration to a thickness of about 1500 Å was deposited, and then formed by projection exposure and anisotropic etching using RIE.

Next, the manufacturing method will be explained.

(i) First, a first interlayer insulating layer is formed on the entire surface of the Si substrate 1 including the gate 1 [pole 3] having the upper surface 5 of the SiOt and the side wall 6 of the 5iOt. asi○3 layers 7 and 5 (sequentially stacking resist layers (not shown) 7 see Figure 1 (a)), forming a resist film in a predetermined pattern +7, (i1) using the resist film as a mask. Then, only the first interlayer insulating layer 7 on the other diffusion region is removed by RIE anisotropic etching until at least a portion of the surface 1b of the other diffusion region is exposed, and then the resist film is removed. Si including the first interlayer insulating film 27
A polycrystalline Si layer (not shown) as a conductive layer made of a material whose etching rate is slower than that of the first interlayer insulating film 27 and a resist layer (not shown) are sequentially laminated on the entire surface of the substrate l, and a predetermined pattern is formed. After forming the resist film, (iii) the conductive layer is etched using the resist film as a mask, leaving the conductive film 8 on one diffusion region R via the first interlayer insulating film 27, and on the other. A conductive buried film 28 electrically connected to the diffusion region remains above the diffusion region [see FIG. 1(b), (iv) the conductive film 8 and the conductive buried film 28]. Including
A second interlayer insulating layer 9 and a resist layer (not shown) are sequentially laminated on the entire surface of the first interlayer insulating film 27.
2) After forming a resist film 50 with a predetermined pattern, the resist film 50 is formed.
Using as a mask, the second interlayer insulating layer 9 and the conductive film 8 on one diffusion region R are sequentially etched, and the first interlayer insulating film 27 directly under the conductive film 8 is etched on the surface of one diffusion region R. It is removed until a part of the interface la with the first interlayer insulating film 27 is exposed.
An interlayer insulating film 29 is formed [see FIG. 1(e)], and (vi) next, a Si layer is formed excluding at least the other diffusion region K.
A first upper layer wiring portion 41 is formed on the substrate l, and a first connection hole 40 is buried with a first upper layer wiring portion 41a [see FIG.
)], (vi) Furthermore, the Si substrate l including the first upper layer wiring section 41
After sequentially laminating a third interlayer insulating layer 13 and a fourth interlayer insulating layer 14 for planarization on the entire surface, a third interlayer insulating layer 13 and a fourth interlayer insulating layer 14 for planarization are deposited on the conductive buried film . Fourth interlayer insulating layer 13. +4 is removed to form a second connection hole (bit line connection hole) 42, and (vii) a second upper layer with a predetermined 5< turn is formed over the entire surface of the fourth interlayer insulating film 14 including the second connection hole. A human wire 15 as a wiring part is formed [see FIG. 1(g)].

In this way, a MOS transistor is formed.

In this embodiment, after the word line 3 is formed, the first interlayer insulating film 2 is
A polySi pattern 8.28 is formed on the polySi pattern 8.28, and a second interlayer insulating layer 9 is further deposited on top of the polySi pattern 8. Since the memory capacitor is formed after the dummy conductive film 8 of the 27, 9 and pO1ySi patterns is removed by etching, the electrode area of the capacitor electrode increases. When the capacitor electrode area increases, the amount of charge stored at the same write voltage increases, and reliability against soft errors caused by incidence of α rays improves.

In addition, 1) by providing the oly3i pattern 8.28, the first and second connection holes 40.42 are formed on the diffusion layer of one side and the other side, so that the capacitor electrode contact portion Also, the overlapping margin for forming each contact hole 40, 42 in the human line contact portion can be increased.

(f) Effects of the Invention As described above, the present invention can be expected to (i) provide high yield during production, even when the overlay accuracy of patterns during projection exposure may be low. Furthermore, (i1) the area of the capacitor electrode can be increased by utilizing the difference in level between the contact portion of the capacitor electrode and the diffusion layer. By increasing the area of the capacitor electrode, the amount of accumulated charge that can be obtained can be increased even with the same write voltage, which has the effect of improving reliability against soft errors and the like.

[Brief explanation of drawings]

FIG. 1 is a manufacturing process explanatory diagram for explaining one embodiment of the present invention, and FIGS. 2(a) and (b) are diagrams for explaining the configuration of main parts and the shape of the main parts, respectively, for explaining the above embodiment. FIGS. 3 to 9 are configuration explanatory diagrams for explaining the conventional example. ...Si substrate, 2...thermal oxide film, ...
・Gate oxide film, 4... Polycrystalline Si film, 6...
...Sin spacer, O...capacitor lower electrode, l...capacitor insulating film, 2...capacitor upper electrode, 3...5iOt film ( 3rd interlayer insulating film), 4...
...〃 (4th〃), 5...
・Bit line (second upper layer wiring part), 7...5i
Oz@ (fourth interlayer insulating film), 9...510g film (second), O...first connection hole, 41
. . . 1st upper layer wiring section, 2 . . . Bit line connection hole (second connection hole). Figure 3 Figure 5 Figure 116 Figure 7 jI8 Figure

Claims (1)

[Claims] 1. A plurality of upper layer interconnects formed by depositing on a semiconductor substrate having a lower layer interconnect consisting of a gate portion with sidewalls and a diffusion region between the gate portions are connected to one diffusion region. When forming a first connection hole for connecting the upper wiring to the other diffusion region and a second connection hole for connecting the upper layer wiring to the other diffusion region via the conductive buried film, After sequentially laminating a first interlayer insulating layer and a resist layer on the entire surface to form a resist film in a predetermined pattern, (ii) using the resist film as a mask, deposit the first interlayer insulating layer on the other diffusion region. After removing only the layer until at least a portion of the surface of the other diffusion region is exposed, and then removing the resist film, a first interlayer insulating film is applied over the entire surface of the semiconductor substrate including the remaining first interlayer insulating film. After laminating a conductive layer made of a material with a slower etching rate and forming a resist film in a predetermined pattern, (iii) the conductive layer is etched using the resist film as a mask, and the first interlayer is etched on one diffusion region. A conductive film is left via the insulating film, and a conductive buried film electrically connected to the other diffusion region is left on the other diffusion region, (iv) the conductive film and the conductive buried film are left on the other diffusion region. After sequentially laminating a second interlayer insulating layer and a resist layer over the entire surface of the first interlayer insulating film, forming a resist film in a predetermined pattern, (v) using the resist film as a mask, one diffusion region is formed. The upper second interlayer insulating layer and the conductive film are sequentially etched, and the first interlayer insulating film immediately below the conductive film is removed until at least a portion of the surface of one diffusion region is exposed, thereby forming the first connection hole. (vi) forming a first upper layer wiring section on the semiconductor substrate excluding at least the other diffusion region, and filling the first connection hole with the first upper layer wiring section; (vii) further forming a first upper layer wiring section; After sequentially laminating a third interlayer insulating layer and a fourth interlayer insulating layer for planarization over the entire surface of the semiconductor substrate including the wiring portion, a second interlayer insulating film and a fourth interlayer insulating layer on the conductive buried film are laminated. 3. Remove each fourth interlayer insulating layer to form a second connection hole, and (viii) form a second upper layer wiring portion in a predetermined pattern over the entire surface of the fourth interlayer insulating film including the second connection hole. 1. A method of manufacturing a semiconductor device, characterized by forming a semiconductor device.