JPH032731A - Active matrix type liquid crystal display element - Google Patents

Abstract

PURPOSE:To suppress reduction of the held video signal potential to such degree at the time of discharging of a signal line capacity that a defect of picture quality does not occur by providing an electrode for additional capacity, which forms a capacity to prevent the potential reduction of the signal line together with the signal line, in the peripheral part of a picture element area. CONSTITUTION:In a part under a scanning line 10 of the lowest stage and off a picture element area 16, an electrode 19 for additional capacity is formed in the direction approximately parallel with the scanning line 10 and across signal lines 11. The additional capacity to improve the potential holding capability of the signal line capacity is formed with the signal line 11, the electrode 19 for additional capacity, and a gate insulating film 22. Therefore, the capacity per one signal line 11 is set to about 1.5-fold conventional capacity. Thus, the signal line potential is hardly reduced by discharging of the signal line capacity, and a picture is displayed more accurately than conventional.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a thin film transistor (Thin Film Transistor).
The present invention relates to an active matrix liquid crystal display element in which a display electrode array is configured using a transducer (ransltor, TPT) as a switch element.

(Prior Art) In recent years, with regard to display elements using liquid crystals, active matrix type display elements with large capacity and high density are being actively developed and put into practical use for use in television displays, graphic displays, and the like. In such display elements, semiconductor switches are used as means for driving and controlling each pixel so that high contrast display without crosstalk can be performed. As the semiconductor switch, a TPT or the like formed on a transparent insulating substrate is usually used because it is capable of transmissive display and can easily be made into a large area.

FIG. 5 is a simple circuit diagram showing one pixel of a liquid crystal display element using a display pixel electrode array equipped with TPT. Same figure (
In a), a TPT3 is provided at each intersection of the scanning line 1 and the signal line 2, the gate of the TPT3 is connected to the scanning line 1 for each row, and the source of the TPT3 is connected to the signal line 2 for each column. has been done. Further, the drain of the TPT 3 is connected to a display pixel electrode 4, and a liquid crystal layer 6 is sandwiched between the display pixel electrode 4 and the counter electrode 5. Furthermore, in the same figure (b), with respect to the configuration shown in the same figure (a), a new storage capacitor (Cs) is added in parallel with the capacitance (CIc) of the liquid crystal layer 6.
Insert the total additional capacity (C1oad −C1c+Cs)
By increasing the voltage, the potential holding ability of the display pixel electrode 4 is improved. Here, the storage capacitor (Cs) is formed, for example, between a part of the display pixel electrode 4, a gate insulating film (not shown), and the storage capacitor wiring 7.

Next, an example of a method for driving this type of liquid crystal display element will be described. That is, the scanning line selection voltage (
During a part (Toe) of the period (switching period) in which Vg, on) is applied, the potential of the signal line 2 is set to the video signal potential.

During switching periods other than Toe, this video signal potential is held by the signal line capacitance, and the potential of the display pixel electrode 4 is set to the video signal potential held by the signal line capacitance during the switching period. This signal line capacitance is shown in Figure 5(a).
This is the capacitance formed between the scanning line 19 and the signal line 2 (Cgs) and between the signal line 2 and the counter electrode 5 (CCs), and is shown in Fig. 5(b).
) between scanning line 1 and signal line 2 (Cgs), between signal line 2 and counter electrode 5 (Ccs), and between signal line 2 and storage capacitor wiring 7
This is the capacitance formed between (Cas). Further, during a period (holding period) in which the scanning line non-selection voltage (Vg, of'r) is applied to the gate of the TPT 3, the display pixel electrode 4 holds the video signal potential held in the signal line capacitance. As a result,
A potential difference corresponding to the video signal voltage is applied to the liquid crystal layer 6 sandwiched between the display pixel electrode 4 and the counter electrode 5 set at a predetermined potential. Then, as the arrangement state of the liquid crystal layer 6 changes in accordance with this potential difference, the light transmittance of this portion also changes, and an image is displayed.

(Problems to be Solved by the Invention) However, in this type of liquid crystal display element, the signal line capacity formed by the above-mentioned system may be insufficient, and Toe
Since the signal line potential decreases due to discharge of the signal line capacitance during other switching periods, the potential of the display pixel electrode 4 may be set to a false video signal potential. Then, a potential difference corresponding to the video signal potential is applied to the liquid crystal layer 6 sandwiched between the display pixel electrode 4 and the counter electrode 5. Therefore, the light transmittance of this portion is different from that when a potential difference corresponding to the true video signal potential is applied to the liquid crystal layer 6, and a false video is displayed. This causes image defects such as contrast reduction, flicker, and crosstalk.

This invention was made in view of such conventional circumstances.

[Structure of the Invention] (Means for Solving the Problems) The present invention has a plurality of scanning lines and signal lines intersecting in a matrix on one main surface of an insulating substrate, and thin film transistors connected to the intersecting points near the intersections. an array substrate having a pixel area in which one pixel made of a display pixel electrode is arranged;
A counter substrate formed by forming a common electrode on one principal surface of an insulating substrate, and a liquid crystal layer sandwiched in a gap obtained by combining an array substrate and a counter substrate so that their surfaces face each other. This is about an active matrix type liquid crystal display element. Further, an additional capacitance electrode is provided in the peripheral portion of the above-mentioned pixel region to form a capacitance with the signal line to prevent a drop in potential of the signal line.

(Function) In an active matrix liquid crystal display element using TPT, image display is performed according to the potential of the display pixel electrode, and the potential of the display pixel electrode is determined by the video signal potential held in the signal line capacitance. be done. In this invention, even if the signal line capacitance is discharged, in order to suppress the drop in the held video signal potential to an extent that does not cause poor image quality, the signal line capacitance is increased and the potential holding ability of the signal line capacitance is improved. let

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is an equivalent circuit diagram showing one embodiment of the present invention.

In FIG. 1, one pixel is configured at each intersection of a scanning line 10 and a signal line 11 by connecting a liquid crystal layer 13, a pixel capacitor 14, and a display pixel electrode 15 via a TFT 12, and each of these pixels is grouped together. The pixel area 16 is formed as a whole. Here, the display pixel electrode 15 is connected to the drain of the corresponding TFT 12, and the gate and source of the TFT 12 are connected to the corresponding scanning line 10 and signal line 11, respectively. Further, the scanning circuit 17 sequentially applies gate pulses to the scanning lines 10, and in synchronization with the gate pulses, the signal hold circuit 1
8 outputs the image signal for one line of the scanning line 10 to the signal line 11. The TPT 12 becomes conductive while a gate pulse is applied to a predetermined scanning line 10, and charges are accumulated in the pixel capacitor 14 according to the image signal output to the predetermined signal line 11 at that time, and the liquid crystal layer 13 is driven.

Furthermore, when the gate pulse moves to the next scanning line 10, the TFT
12 becomes non-conductive, and the accumulated charges are held until the next scan, so that the display state of the liquid crystal layer 13 is maintained. Then, in a portion of the lowermost scanning line 10 that is further away from the lower pixel area 16, the signal line 10 is arranged so that the additional capacitance electrode 9 extends in a direction approximately parallel to the scanning line 10.
It is formed by intersecting with 1. In addition, additional capacitance electrode 1
Reference numeral 9 is set to a predetermined potential, such as a counter electrode potential or a ground potential.

FIG. 2 is a sectional view of one pixel portion in one embodiment of the present invention. To explain according to the manufacturing process in the same figure,
For example, a gate electrode 21 is formed on one main surface of an insulating substrate 20 made of glass by coating a Cr (chromium) film, which is a light-shielding material, by sputtering, and then photoetching it into a predetermined shape. Furthermore, a gate insulating film 22 made of silicon oxide (S i Ox ), for example, is formed by plasma CVD so as to cover this. Although not shown, when the gate electrode 21 is formed, the scanning line 10 and the additional capacitance electrode 19 in FIG. 1 are also formed in the same process. For example, i
A semiconductor layer 23 made of type hydrogenated amorphous silicon (a-Si:H) is formed using a plasma CVD method, and on the semiconductor layer 23, n-type a- Ohmic layer 24a made of Si:H
, 24b are also provided using the plasma CVD method. Then, on the gate insulating film 22 adjacent to the semiconductor layer 23, a display pixel electrode 15 is provided by, for example, coating an ITO (indium tin oxide) film by sputtering and then photoetching it into a predetermined shape. ing. Further, one end of a drain electrode 25 is connected to the ohmic layer 24b, and the other end of the drain electrode 25 extends over and is connected to the display pixel electrode 15. Furthermore,
One end of a source electrode 26 is connected to the ohmic layer 24a. Here, the drain electrode 25 and the source electrode 26
For example, a Mo (molybdenum) film and an AI (aluminum) film are formed in the same process by sequentially coating them by sputtering and then photo-etching them into a predetermined shape.
Although not shown, the signal line 11 in FIG.
The drain electrode 25 and the source electrode 26 are also formed in the same process. In this way, the desired array substrate 27 is obtained. On the other hand, a common electrode 29 made of, for example, ITO is formed on one main surface of an insulating substrate 28 made of, for example, glass, thereby forming a counter substrate 30 . An alignment film 31 made of, for example, low-temperature-curable polyimide is further formed on one main surface of the array substrate 27, and an alignment film 31 made of, for example, low-temperature cure type polyimide is also formed on one main surface of the counter substrate 30, for example. Alignment film 3 made of low temperature cure type polyimide
2 is formed. Then, by rubbing each of the alignment films 31 and 32 in a predetermined direction with a cloth or the like on one main surface of the array substrate 27 and the counter substrate 30, an alignment treatment by rubbing is performed, respectively. Furthermore, array substrate 2
7 and the counter substrate 30 are combined so that their surfaces face each other and their alignment axes form approximately 90'', and a liquid crystal layer 33 is sandwiched in the gap thus obtained.

Polarizing plates 34 and 35 are attached to the other main surfaces of the array substrate 27 and the counter substrate 30, respectively, and illumination is performed from the other main surface of either the array substrate 27 or the counter substrate 30. It's in shape.

FIG. 3 is a diagram showing an example of the structure in the vicinity of the additional capacitance electrode 19 on the array substrate 27 in an embodiment of the present invention, in which FIG. 3(a) is a plan view and FIG. 3(b) is a plan view. The same figure (a
) is a cross-sectional view taken along line A-A when viewed from the direction of the arrow. As can be seen from FIG. 3, the signal line 11 and the additional capacitance electrode 19 intersect with each other via the gate insulating film 22 in the peripheral portion of the pixel region 16. Here, the reason why the additional capacitance electrode 19 is provided in the peripheral part of the pixel region 16 is that, considering the manufacturing process, the additional capacitance electrode 19 formed at the same time as the scanning line 10 reduces the aperture ratio of the display element. This is because there is fear.

In this embodiment, since the additional capacitance for improving the potential holding ability of the signal line capacitance is formed by the signal line 11, the additional capacitance electrode 19, and the gate insulating film 22, the signal line
The capacity per unit of 1 can be set to about 1.5 times that of the conventional one. As a result, a drop in signal line potential due to discharge of the signal line capacitance is less likely to occur, making it possible to display images more accurately than in the past. Here, by changing the pattern shape of the additional capacitance electrode 19 or the signal line 11, the above-mentioned additional capacitance can be set to an arbitrary value.

FIG. 4 is a diagram showing another example of the structure in the vicinity of the additional capacitance electrode 19 on the array substrate 27 in one embodiment of the present invention, in which FIG. 4(a) is a plan view and FIG. ) is the same figure (
A cross-sectional view of the BB cross section of a) is shown in the direction of the arrow. This example differs from the example shown in FIG. 3 in that the semiconductor layer 23 partially remains at the intersection of the signal line 11 and the additional capacitance electrode 19. As a result, the additional capacitance for improving the potential holding ability of the signal line capacitor is formed by the signal line 11, the additional capacitance electrode 19, the gate insulating film 22, and the semiconductor layer 23, and the same effect as in the embodiment described above is achieved. can have.

[Effects of the Invention] This invention improves the potential holding ability of the signal line capacitor by providing a predetermined additional capacitance electrode outside the pixel area. Image quality defects caused by a drop in the video signal potential held in the line capacitance can be suppressed.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram showing an embodiment of the present invention, and FIG. 2 is a sectional view of one pixel portion in the embodiment shown in FIG. 1.
3 and 4 are diagrams showing an example of the structure in the vicinity of the electrode for additional capacitance provided on the array substrate in the embodiment shown in FIG. 1, and FIG. FIG. 2 is a schematic circuit diagram representing one pixel. 10...Scanning line 11...Signal line 12...Thin film transistor 13...Liquid crystal layer 15...Display pixel electrode 6...Pixel region 9...Additional capacitance electrode 0.28... Insulating substrate 7...Array substrate 9...Common electrode 0...Counter substrate 3...Liquid crystal layer Agent Patent attorney Nori Chika Ken Yudo Kikuo Takehana Figure 1 ■ (a) (b) Figure (a) Figure (a) (b) Figure

Claims (1)

[Claims] A plurality of scanning lines and signal lines intersect in a matrix on one main surface of an insulating substrate, and one pixel consisting of a thin film transistor and a display pixel electrode connected to the thin film transistor is arranged near the intersection. an array substrate having a pixel area consisting of a pixel region, a counter substrate having a common electrode formed on one main surface of an insulating substrate, and the array substrate and the counter substrate are combined so that the one main surface sides thereof face each other. In an active matrix liquid crystal display element having a liquid crystal layer sandwiched between the resulting gaps, a capacitor is formed in a peripheral portion of the pixel region to prevent a potential drop in the signal line between the pixel region and the signal line. An active matrix liquid crystal display element characterized by being provided with an electrode for additional capacitance.