JPH03272222A - Clock signal generator - Google Patents

Abstract

PURPOSE:To generate a clock with a fast reply to a phase fluctuation by providing a phase modulation means receiving a phase of a clock outputted from a voltage controlled oscillator means and receiving an error signal outputted from a phase comparison means as a modulation input to the generator. CONSTITUTION:A clock outputted from a voltage controlled oscillator 53 is inputted to a phase modulator 56. Moreover, a phase error signal outputted from a phase comparator 51 is inputted to the phase modulator 56 after the gain is adjusted to a prescribed gain by a gain adjustment device 55. The phase modulator 56 applies phase modulation to the clock inputted from the voltage controlled oscillator 53 corresponding to a modulation signal inputted from the gain adjustment device 55. Thus, a phase error difficult to be fallowed by a PLL circuit is corrected by an open servo loop by the phase modulator 56 to decrease the phase error further more.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lock signal generator suitable for use in, for example, a video tape recorder to generate a clock signal that accurately corresponds to a time axis error thereof.

[Prior Art] In order to correct the time axis error of a reproduced video signal in a video tape recorder, it is first necessary to generate a clock signal that accurately corresponds to the time axis error. For this reason,
Typically, a PLL circuit generates a clock synchronized with a horizontal synchronization signal reproduced from a videotape.

[Problem to be solved by the invention] However, the cutoff frequency of the PLL circuit is
It is about Hz, at most about 2 KHz. P
The LL circuit is a sampling system, and in a video tape recorder, the frequency of the horizontal synchronizing signal (15,73KH
z), but even at the 172 frequency of 7.9 KHz, the phase is delayed by about 70 degrees just due to the effect of the sampling hold. In reality, other delays are added due to various factors, so the phase will be further delayed.

Recently, helical scan type video tape recorders have been equipped with multiple heads, and as many heads strike the magnetic tape, jitter has increased. This jitter is IKHz
Since a large amount of the above components are included, the conventional PLL circuit cannot sufficiently remove the time axis error.

The present invention has been made in view of this situation, and it is an object of the present invention to generate a clock that responds quickly to phase fluctuations of an input signal.

[Means for Solving the Problems] A clock signal generator of the present invention includes a phase comparison means for comparing the phases of two input signals and outputting an error signal thereof, and a clock signal generator for comparing the phases of two input signals and outputting an error signal thereof. A voltage controlled oscillation means that generates a clock of a corresponding frequency, a phase comparison means and a voltage controlled oscillation means constitute a PLL circuit, and the clock outputted by the voltage controlled oscillation means is frequency-divided and the phase is compared by the phase comparison means. The present invention is characterized by comprising frequency dividing means for supplying one signal as one signal, and phase modulating means for modulating the phase of the clock outputted by the voltage controlled oscillation means and an error signal outputted by the phase comparing means.

[Operation] In the clock signal generator configured as described above, a PLL circuit is configured by the phase comparison means, the voltage controlled oscillation means, and the frequency dividing means, and a clock synchronized with the input signal is output from the voltage controlled oscillation means. The phase of this clock is further phase-modulated by a phase modulator that uses the phase error signal of the PLL as a modulation signal.

Therefore, it is possible to generate a clock that responds quickly to phase fluctuations.

[Embodiment] FIG. 1 is a block diagram showing the configuration of an embodiment of the clock signal generator of the present invention.

The phase comparator 51 (phase comparison means) receives from a circuit not shown, for example, a reproduced horizontal synchronizing signal separated and extracted from a video tape reproduction signal, and inputs the signal from the counter 54 (frequency dividing means) and the reproduced horizontal synchronizing signal. The phases are compared. Phase comparator 5
The phase error signal outputted by 1 is passed through a low-pass filter (LPF
) 52 to a voltage controlled oscillator (VCO) 53 (voltage controlled oscillation means). The clock output from the voltage controlled oscillator 53 is input to a counter 54 and frequency-divided.

The above phase comparator 51, low pass filter 52, voltage controlled oscillator 53 and counter 54 constitute a PLL circuit.

The phase error signal of the phase comparator 51 is input as a modulation signal to a phase modulator 56 (phase modulation means) via a gain adjuster 55, so that the clock output from the voltage controlled oscillator 53 is phase modulated.

Next, its operation will be explained.

A phase comparator 51 compares the phases of the reproduced horizontal synchronizing signal and the output signal of the counter 54, and outputs an error signal. This phase error signal is smoothed by a low-pass filter 52 and then input to a voltage controlled oscillator 53. Voltage controlled oscillator 53 generates a clock at a frequency corresponding to the signal from low pass filter 52. This clock is counter 5
4 is input. The counter 54 divides the frequency by counting a predetermined number of clocks, and outputs the divided output to the phase comparator 51.

In this way, the phase comparator 51, the low-pass filter 5
2. PL by voltage controlled oscillator 53 and counter 54
The closed servo loop of the L circuit locks to the reproduced horizontal synchronizing signal, and the voltage controlled oscillator 53 outputs a clock synchronized with the reproduced horizontal synchronizing signal.

The clock output from the voltage controlled oscillator 53 is input to the phase modulator 56. The phase error signal output from the phase comparator 51 is also input to the phase modulator 56 after being adjusted to a predetermined gain by a gain adjuster 55 . The phase modulator 56 phase modulates the clock input from the voltage controlled oscillator 53 in accordance with the modulation signal input from the gain adjuster 55.

The response characteristic of the PLL circuit is shown by curve P in Fig. 2. In other words, if the jitter frequency of the input signal (reproduced horizontal synchronization signal) is lower than the cutoff frequency fc, the response characteristic of the PLL circuit is as follows. Since the response is possible, the level of the phase error signal becomes smaller. However, as the frequency increases,
It becomes difficult to respond quickly and the level of the error signal increases.

Therefore, the phase modulator 56 is not provided, and the RAM write address control is performed only by the output of the PLL circuit.
When jitter is improved by C (time axis error correction circuit), the improved characteristic will be a characteristic in which the curve isP is folded around the O decibel line, as shown by IItl line J in Figure 2. . That is, when the jitter frequency is low, the PL
Since the L circuit follows and responds quickly, the degree of improvement is large. However, as the frequency increases, the PLL circuit cannot respond quickly, so a phase difference occurs between the clock and the reproduced horizontal synchronization signal, and the degree of jitter improvement decreases.

Therefore, in the phase modulator 56, voltage control (immediate oscillator 5
Corresponding to the phase error signal adjusted by the gain adjuster 55, the clock outputted by 3 is phase-modulated to a greater degree as the jitter frequency becomes larger (the level of the phase error signal becomes larger). As a result, a phase error that cannot be tracked by the PLL circuit is corrected by the oven servo loop of the phase modulator 56, and the phase error can be further reduced.

The phase modulator 56 can be configured as shown in FIG. 3, for example.

In this embodiment, the collector of the NPN+- transistor 21 is connected to a predetermined voltage source VCC via a resistor 22, and its emitter is grounded via a resistor 23.

A clock is input to the base of the N P N +- transistor 21, and signals having mutually opposite phases appear at its collector (point B) and emitter (point A). This reverse phase signal is
It is synthesized by the capacitor 24 and a series circuit consisting of the capacitor 25, PIN diodes 26, 27, and capacitor 28, and is output from point C.

A predetermined bias current flows through the anode of the PIN diode 26 via a resistor 32 and a coil 29. Further, a predetermined bias current flows through the anode of the PIN diode 27 via the resistor 32 and the coil 31. Further, a variable resistor 33, a resistor 34 and a coil 30 are connected to the cathodes of the PIN diodes 26 and 27.
A predetermined voltage is applied through the capacitor 35 and a modulation signal is input through the coil 30.

As a result, the equivalent resistance of the PIN diodes 26 and 27 changes in accordance with the level of the modulation signal, and the phase of the signal output from point C is changed between 0 degrees and +18 degrees as shown in FIG.
It can be controlled within a range of 0 degrees.

Furthermore, FIG. 5 shows the configuration of another embodiment of the phase modulator 56.

In this embodiment, a triangular wave converter 61 and a voltage comparator 62
The phase modulator 56 is configured by the following.

The clock (FIG. 6A) is input to the triangular wave converter 61,
It is converted into a triangular wave (Fig. 6C). This triangular wave is input to a voltage comparator 62, and its voltage (level) is compared with the modulation signal (FIG. 6B). As a result, the voltage comparator 62
As a result, a phase-modulated clock (FIG. 6D) corresponding to the modulation signal is output.

FIG. 7 is a block diagram showing the configuration of a third embodiment of the phase modulator 56 of the present invention.

A modulation signal is input to the A/D converter 41, and its output is supplied to the address terminal of the data selector 42. Further, the clock is input directly to the data terminal of the data selector 42 via inverters 43 to 49.

The clock is applied to inverters 43 to 49 sequentially. Since the inverters 43 to 49 have a delay time from when a signal is input to when they generate an output signal, the outputs of the inverters 43 to 49 are signals having mutually different phases. These signals are supplied to data terminals O to 7 of the data selector 42.

On the other hand, the modulated signal is A/D converted by the A/D converter 1, and in the case of this embodiment, is sent to the address terminals A2 to A of the data selector 42 as 3-bit digital data. is supplied to The data selector 4-110-2 selects and outputs one of the signals input to the data terminals O to 7 in accordance with the signal applied to the address terminal.

FIG. 8 is a block diagram showing the configuration of a fourth embodiment of the phase modulator 56 of the present invention.

A modulation signal is input to the A/D converter (A/D) 1, and its output is sent to the ROM (X-ROM) 2 and ROM (Y-ROM).
M) 3. The outputs of flOM2 and flOM3 are supplied to D/A converters (D/A) 4 and 5, respectively. D
/A converter 4 outputs NPN via variable resistor 6)
N P differentially connected to transistors 13 and 14
N l-supplied to the base of transistor 12.15. Similarly, the output of the D/A converter 5 is supplied via a variable resistor 7 to the base of an NPN transistor 8.11 which is differentially connected to NPN transistors 9 and 10.

The collectors of NPN transistors 9.11 and 13.15 are connected to each other and are further connected to a low-pass filter (LPF).
)16. NPN transistor 8, 10
, 12.14 are connected to a predetermined voltage source. The output of the low-pass filter 16 is connected to a voltage source via a resistor 17.

A clock is input to the terminals CK of the D-type flip-flops 18 and 19. The output terminal Q of the D-type flip-flop 19 is connected to the terminal of the D-type flip-flop 18.
Furthermore, the output terminals Q of the D-type flip-flop 18 are connected to the terminals of the D-type flip-flop 19, respectively.

The output terminal Q of the D-type flip-flop 18, which outputs a signal with a phase of 0 degrees, is also connected to the emitters of differentially connected NPN transistors 10 and 11 via a resistor 73, and outputs a signal with a phase of 180 degrees. Its output terminal Q, which outputs NPN, is differentially connected via a resistor 71.
It is connected to the emitters of transistors 8 and 9. Similarly, a D-type flip-flop 1 outputs a signal with a phase of 90 degrees.
The output terminal Q of 9 is also connected via a resistor 75 to the emitters of differentially connected NPN transistors 12 and 13 = 11-12-, and its output terminal Q outputs a signal with a phase of +90 degrees. is connected via a resistor 77 to the emitters of differentially connected NPN transistors 14 and 15.

Furthermore, the emitters of NPN transistors 8 to 15 have
resistance? A predetermined voltage is supplied through 2, 74, 76, and 78.

The modulated signal is A/D converted, A/D converted, and then supplied to the ROM 2.3. The ROM2 stores data on sine characteristics, and the ROM3 stores data on cosine (COS) characteristics.

That is, ROMs 2 and 3 store data Dx and D expressed by the following equations for address A (for example, addresses O to 255).
y is memorized.

D x-127 (sin (2yr A/256)+1)
D y = 127 (cos (2rt A/256
) +1) Then, the ROMs 2 and 3 output the modulated signal output from the A/D converter 1 as an address and the data corresponding to the address as a control signal to the D/A converters 4 and 5, respectively. D/A converters 4 and 5 D/A convert the input control signals. D by D/A converters 4 and 5
The /A-converted control signal is adjusted to a predetermined level by variable resistors 6 and 7, and then transferred to NPN transistors 11 and 1.
5 and the bases of NPN transistors 8 and 10, respectively.

D-type flip-flops 18 and 19 synchronize with the clock input to the terminal CK, latch the logic at the terminal at the timing when the clock is input, and transfer the latched logic from the output terminal Q to the opposite side. The logic is output from the output terminal Q at the timing of the next clock. As a result, the output terminal Q of the D-type flip-flop 18
and Q, signals with a phase of 0 degrees and 180 degrees are output, and output terminals Q and 0 of the D-type flip-flop 19 have a phase of +9
Signals of 0 degrees and 190 degrees are output.

At this time, the frequency of the signals output from the D-type flip-flops 18 and 19 is 1/4 of the clock frequency.

13- 14- These 4 degrees of 0 degrees, 180 degrees, +90 degrees, and -90 degrees
The phase signals are mutually differentially connected NPN l-transistors 10, 11.8, 9.14 and 15, and 12 and 1.
3, respectively.

As mentioned above, since the control signal output from the D/A converter 4 is input to the bases of the NPN transistors 12 and 15, the signals with phases of +90 degrees and 190 degrees are
Control MI (synthesized at a level corresponding to No. 8. Similarly, for the base of N P N I-Langistaro and 10,
Since the control signal output from the D/A converter 5 is input, the signal with a phase of 0 degrees and 180 degrees is the control fI (I
(Synthesized at a level corresponding to No. 8.

In this way, signals represented by two mutually orthogonal vectors having equal amplitude and frequency are generated, and these two signals are further combined.

For example, when the address is O, the base voltages of NPN transistors 2 to 15 are OV, which means -90 degrees and +
The 90 degree signals have the same level, and the result of synthesis is zero. Further, the NPN transistor 11 is saturated and the NPN transistor 9 is cut off. As a result, only a signal with a phase of 0 degrees is output.

Similarly, at address 63, +9090, at address 127, 18080, and at address 192, -90, 25
At address 5, only the 2πX 255/256 component is output, and at address A, the 2πA/256 degree component is output.

D-type flip-flops 18 and 19 operate digitally, so compared to phase shifters that use reactance,
In principle, its accuracy and stability are excellent, and no adjustment is required.

Furthermore, since the NPN transistors 8 to 15 have a differential connection structure, they exhibit excellent stability, precision, and reliability in terms of linearity, temperature characteristics, aging characteristics, and the like.

The 4-phase output is a rectangular wave, so if you just add it in an analog way, there will be many harmonics and the edges will be stepped, so after passing it through the low-pass filter 16 and removing unnecessary high-frequency components, it will be output. Ru.

15-16- It is theoretically possible to configure the control signal with a phase shift circuit using reactance, but this becomes difficult to realize if the frequency band of the modulation signal is, for example, a wide band of three orders of magnitude or more. Become. Even if it could be realized, a transfer circuit using reactance would change not only the phase but also the amplitude. Also, it cannot be operated with DC input.

In this regard, in the above embodiment, it is extremely easy to store data in a range of one period (2π) or more in the ROM 2.3, so that phase adjustment over a wide tfi range is possible. Further, it can be operated even if the modulation signal is DC.

The video signal played from the videotape is stored in memory (not shown) in synchronization with the clock generated as described above.
If the data is written to and read using a fixed-phase read clock, jitter can be further reduced.

[Effects of the Invention] As described above, according to the clock signal generator of the present invention,
Since the clock output from the voltage controlled oscillation means forming part of the PLL circuit is phase modulated in accordance with the phase error signal output from the phase comparison means forming part of the PLL circuit, the input signal and the clock phase error can be controlled to a smaller value.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the clock signal generator of the present invention, FIG. 2 is a characteristic diagram explaining the operation of the embodiment of FIG. 1, and FIGS. 8 are block diagrams showing the configuration of the embodiment of the phase modulator shown in FIG. 1, FIG. 4 is a vector diagram explaining the operation of the embodiment shown in FIG. 3, and FIG. 2 is a timing chart illustrating the operation of the embodiment. 1... A/D converter, 2, 3... ROM, 4.5.
... D/A converter, 18.19... D-type flip-flop, 51... Phase comparator, 52... Low pass filter, 53... Voltage controlled oscillator, 54... Counter, 55... ...gain adjuster, 56...phase modulator,
61... Triangular wave converter, 62... Voltage comparator. =17- 18- 150- A Figure 6

Claims (1)

[Claims] Phase comparison means for comparing the phases of two input signals and outputting an error signal thereof; and voltage control for generating a clock having a frequency corresponding to the error signal output by the phase comparison means. an oscillation means, a PL together with the phase comparison means and the voltage controlled oscillation means;
Frequency dividing means forming an L circuit and dividing the frequency of the clock outputted by the voltage controlled oscillation means and supplying the clock as one signal to be phase compared to the phase comparing means; A clock signal generator comprising: phase modulation means that modulates the phase of a clock using the error signal outputted by the phase comparison means.