JP2533368B2 - Clock generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to an externally synchronized reference clock generation circuit suitable for application to a write clock generation circuit of a time base collector (TBC), etc. Also improves the response speed.

[Related Art] When a video signal is recorded and reproduced on an optical disk, a VTR, or the like as an analog signal, a TBC is generally used to remove a time axis fluctuation of the reproduced video signal.

FIG. 3 shows an example of this TBC 20, in which a reproduced video signal (still image signal) having a time base fluctuation supplied to a terminal 26 is supplied to a write clock generation circuit 24, from which a horizontal synchronizing signal is supplied. Is separated, and the write clock W · CK that matches the time-axis fluctuation of the video signal is generated.

In the A / D converter 21, the reproduced video signal is sampled and digitized based on the write clock W · CK, and the digital video signal is written in the memory 22 by the write clock W · CK having the same time axis fluctuation.

On the other hand, from the read clock generation circuit 25, the read clock R
CK is output, whereby the digital video signal is read out from the memory 22 and converted into an analog signal in the D / A converter 23 based on the read clock R · CK. Therefore, a video signal with a fixed time axis is obtained at the output terminal 27.

The time axis correction capability of the TBC 20 configured as described above depends on how accurately the write clocks W and CK can follow the time axis fluctuation of the reproduced video signal. A general BCO (burr that uses elements such as crystal oscillators, coils, and capacitors that have been proposed so far.
The st controlled oscillator is not sufficient, and a circuit having a wide frequency response range and a fast response speed is required.

Further, such a BCO has a disadvantage that it is likely to become unstable due to the influence of noise, waveform distortion, dropout, skew, and the like.

Therefore, in the burst gate circuit of the TBC and the sync separation circuit, in order to satisfy the contradictory requirements that the time axis fluctuation component of the input video signal is not attenuated and the effect of noise and the like is less likely to occur, the horizontal sync signal separation means (1) Synchronous gate circuit with gate signal using delay circuit or flywheel oscillator (2) Detects dropout and mutes dropout noise in video signal, or synchronous separation (3) Wideband circuit for synchronization, color burst amplification,
Devices such as separation have been devised.

Next, FIG. 4 shows an example of a case where an accurate write clock W · CK is created using the sync signal and the color burst signal separated in this way.

In the write clock generation circuit 24 shown in FIG.
It is a horizontal oscillator signal supplied to terminal 40 and a variable oscillator.
A signal obtained by dividing the output of the VCO (voltage controlled oscillator) 33 by the frequency dividing circuit 34 is phase-compared by the phase comparator 31, and the oscillation frequency of the VCO 33 is controlled by the error voltage.
This PLL system has a loop filter 32 to prevent loop oscillation.
However, if the video signal has a sudden phase change due to the loop filter 32, it hardly follows the change, and becomes irrelevant to the subcarrier phase.

Therefore, when the VCO output is further divided into 1/4 by the frequency dividing circuit 35 to 3fsc (fsc is the subcarrier frequency),
Color burst signal (terminal 41) separated from the input video signal
Reset) with one pulse.

It should be noted that, due to this reset, the phase error with the color burst signal at the frequency-divided output of 3fsc becomes 30 ° or less in terms of the phase of the color subcarrier.

Then, after passing the output of the 1/4 frequency divider through the phase modulator 36, it is frequency-divided by a frequency divider 37 into 1/3 to have the same cycle as the color subcarrier. The phase is compared by the comparator 38, and the error voltage
Is controlled. Also in this case, the loop filter 39 is inserted as described above.

This allows the write clock W to follow the input video signal and be phase-locked to the horizontal synchronization signal.
・ Can make CK.

[Problems to be Solved by the Invention] However, in such a conventional TBC 20, a loop filter 32 and a VCO 33 for generating a signal serving as a source of a write clock and a phase modulator 36 for phase locking to a color burst signal are provided respectively. Since the feedback control using the C.39 is used, it is impossible to realize a write clock generation circuit having a high response speed even with the above-described improvements.

In particular, in the case of an optical disk still image file, one frame of a still image is reproduced in a short time, and the rotational jitter of the optical disk also has a high frequency component. I couldn't do it.

In view of the above, the present invention has solved such a problem, and proposes a reference clock generation circuit having an improved response speed.

[Means for Solving the Problems] A clock generation circuit according to claim 1 includes a first reference signal generation means, a second reference signal generation means, a phase difference detection means, and an output clock signal generation means. Prepare The first reference signal generation means generates a first reference signal. The second reference signal generating means generates a second reference signal having a phase orthogonal to the phase of the first reference signal in response to the first reference signal. The phase difference detecting means detects a phase difference between the predetermined input signal and the first reference signal, and outputs first and second detection signals that represent the detected phase difference and have mutually orthogonal phases. . The output clock signal generation means generates an output clock signal synchronized with the phase of the input signal in response to the first reference signal, the second reference signal, and the first and second detection signals. The output clock signal generating means includes a first multiplying means, a second multiplying means, and an adding means. The first multiplication means includes a first reference signal and a first reference signal.
Is multiplied by the detection signal of. The second multiplication means multiplies the second reference signal by the second detection signal. The adding means adds the respective outputs of the first and second multiplying means and outputs the sum as an output clock signal.

In the clock signal generating circuit according to claim 2, the phase difference detecting means according to claim 1 includes a sampling means,
The calculation means and the storage means are provided. The sampling means samples the first reference signal in response to the input signal, and determines the absolute phase of the input signal based on the level of the sampled first reference signal. The calculating means calculates a phase difference between the determined absolute phase and a predetermined phase. The storage means stores predetermined sine wave data and cosine wave data, outputs a sine wave signal having the phase difference calculated based on the sine wave data as a first detection signal, and outputs the cosine wave. The cosine wave signal of the calculated phase difference based on the data is output as the second detection signal.

[Operation] In this clock generation circuit, the phase difference between the input signal having jitter and the first reference signal is detected for each cycle of the input signal, and the output clock signal is output based on the detected phase difference. Is generated. Therefore, the output clock signal synchronized with the input signal is generated in a wide band and at a high speed. This makes it possible to provide a stable clock generation circuit having a sufficiently wide frequency response range and a fast response speed.

[Example] Hereinafter, an example of the reference clock generating circuit according to the present invention will be described in detail with reference to FIG. 1 when applied to the above-described TBC write clock generating circuit.

In the write clock generation circuit 24 of FIG.
Bandpass filter 2 with 4.05MHz square wave reference clock signal output from crystal oscillator 1 with 4.05MHz (= fc)
Is converted into a sine wave signal sin (2πfct) of 4.05 MHz.

 Here, π is the circular constant, and t is the time (hereinafter the same).

The sine wave signal sin (2πfct), which is an analog signal, is 4
It is input to the first D / A converter (programmable attenuator) 3 having a quadrant multiplying function as its reference voltage, and is also input to the 1/4 cycle delay unit 4. This sine wave signal sin (2πfct) is also sent to the A / D converter 6 as an A / D signal.
It is input as a conversion target. Since the sine wave signal sin (2πfct) input to the 1/4 cycle delay unit 4 is delayed by 1/4 cycle, it becomes a cosine wave signal cos (2πfct).

Therefore, the sine wave signal sin (2πfct) is converted into two reference signals (sine wave signal sin (2πfct) and cosine wave signal cos (2πfct)) that are in a quadrature relationship due to the presence of the delay device 4. Become.

Cosine wave signal cos (2πfct) which is this analog signal
Is a second D / A converter 5 having a multiplying function.
Is input as the reference voltage.

Here, the sine wave signal sin (2
πfct) and the phase resolution of the cosine wave signal cos (2πfct) depend on the bit configuration of the D / A converters 3 and 5, respectively. For example,
When the D / A converters 3 and 5 each have a 5-bit configuration, the phase resolution is 11.25 degrees (= 360 degrees / 32).

This phase resolution is in the analog circuitry of the system
It should be selected according to the residual time base error formed by S / N or the TBC range required by the system.

Next, the horizontal synchronizing signal is input to the A / D converter 6 via the terminal 11 as a sampling clock signal. Here, the horizontal sync signal corresponds to the input signal for the purpose of achieving phase synchronization. For example, in the case of the NTSC system, it is 15.75K.
Has a frequency of Hz. The A / D converter 6 receives a sine wave signal sin (2πf when a horizontal sync signal with jitter is input.
The voltage of ct) is sampled, and the analog voltage is converted into a digital signal a and output. Sine wave signal sin
While the phase of (2πfct) is always constant, the phase of the horizontal synchronizing signal changes every cycle. Therefore, a different voltage is sampled for each cycle of the horizontal synchronizing signal. Therefore, the digital signal a has the absolute phase of the horizontal synchronizing signal when the sine wave signal sin (2πfct) is used as a reference.

Digital signal a representing the absolute phase of the horizontal sync signal
Is input to the calculator 7. In the calculator 7, the absolute phase a
Then, a phase difference (ab = c) from the preset phase b is calculated by the initial phase setting device 8. The calculator 7 has a ROM for sine and a ROM for cosine. Figure 2 shows
It is a graph showing the data stored in ROM for sine and ROM for cosine. The vertical axis represents the data stored in the ROM, and the horizontal axis represents the phase difference c. Therefore, when a predetermined address signal based on the phases a and b is applied to these two ROMs at the same time, the sine component sin (ab) and the cosine component cos (a-) corresponding to the phase difference c (= ab).
b) (both are digital signals) can be simultaneously output.

The two sine components sin (a−a−
b) and the cosine component cos (ab) function as the first and second detection signals.

The sine component sin (a-b) output from the calculator 7 is supplied to the first D / A converter 3, and the cosine component cos (a-b) is supplied to the second D / A converter 5. It The D / A converters 3 and 5 are both designed so that the output amplitude of the D / A converters 3 and 5 can be controlled by a reference signal when converting the input digital signal, which is a detection signal, into an analog signal.

Therefore, in the first D / A converter 3, the supplied digital sine component sin (ab) is converted into analog, but the sine wave signal sin (2πfct) input as the reference voltage at this time is converted. The sine component sin (ab) is multiplied (multiplied), and the multiplication result (analog signal) represented by the following equation (1) is output.

Multiplication result = sin (2πfct) · sin (ab) (1) On the other hand, in the second D / A converter 5, the supplied digital cosine component cos (ab) is converted into analog. ,
At this time, the cosine wave signal cos input as the reference voltage
(2πfct) is multiplied (multiplied) by the cosine component cos (ab), and the multiplication result (analog signal) represented by the following equation (2) is output.

Multiplication result = cos (2πfct) · cos (ab) (2) Here, the sine wave signal sin (2) supplied to the D / A converter 3
Since πfct) can take positive and negative values, it can be said to be a two-quadrant signal. Further, since the sine component sin (a-b) supplied to the D / A converter 3 can also take positive and negative values, it can be said to be a two-quadrant signal. Therefore,
This D / A converter 3 has a 4-quadrant multiplying function. This also applies to the D / A converter 5.

The respective multiplication outputs are added by the analog adder 9. The output of the analog adder 9 is as follows.

sin (2πfct) ・ sin (c) + cos (2πfct) ・ cos (c) = cos (2πfct-c) (where c = ab), which is a cosine wave with a 90 ° phase difference from the first reference signal. A cosine wave signal cos (2πfct-c) whose phase is delayed by c with respect to the signal cos (2πfct) is output.

Finally, the cosine wave signal cos (2πfct-c) is binarized by the comparator 12 and used as the write clock W · CK. Therefore, the write clock W · CK is a clock whose phase is synchronized with the horizontal synchronization signal.

The cosine wave signal cos (2πf
In ct-c), the phase c corresponding to the phase difference of the horizontal synchronizing signal with respect to one clock of the reference signal appears. That is, the phase of the cosine wave signal cos (2πfct), which is the same as the sine wave signal, is instantaneously changed by the phase difference c between the sine wave signal which is the reference signal and the horizontal synchronizing signal which is the input signal.

Moreover, the cosine wave signal cos (2πfct-c) is phase-locked with the horizontal synchronizing signal having the time axis fluctuation. Since the cosine wave signal cos (2πfct-c) is converted into a binary signal by the comparator 12, it is obtained as a stable write clock W · CK.

In the above-described embodiment, the time axis correction of the reproduced video signal is performed only by adjusting the initial phase of the write clock with respect to the horizontal synchronizing signal, but this can also obtain a sufficient TBC effect.

This is because, even in the case of a moving image or a still image of component recording, the time-axis fluctuation during one horizontal period is small. However, if you want a more accurate TBC effect,
The end phase error of the horizontal synchronizing signal is stored in the memory 22 of the TBC 20, and based on this storage error, the phase of the sampling clock (readout clock R / CK) of the D / A converter 23 for converting a digital signal into an analog signal is horizontal. Phase modulation may be performed in units of a period. Then, as the read clock generating circuit, the same means as in the above-described write clock generating circuit may be used.

The present invention is not limited to the above embodiment. For example, sine and cosine signals have a 1/4 phase
Since the signals are exactly the same just by shifting the period, even if the sine wave and the cosine wave are exchanged in the above-described embodiment, the same effect can be obtained.

Further, in the D / A converters 3 and 5, the sine waves and the cosine waves are multiplied, but the sine wave and the cosine wave may be multiplied for the same reason. In that case, the sign of the phase c in the finally output cosine wave signal is only inverted.

The analog adder 9 may perform subtraction processing instead of addition processing.

EFFECTS OF THE INVENTION As described above, according to the present invention, the phase of the output clock signal can be synchronized with the phase of the target input signal in a wide band and at a high speed. It is possible to generate a stable output clock signal that also has a response speed.

Therefore, the present invention is extremely effective when applied to a TBC write clock generation circuit for an optical disk still image file or the like, which has a short time axis fluctuation and has high rotation jitter.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a reference clock generation circuit according to the present invention, FIG. 2 is a waveform diagram showing the contents of a sine ROM and a cosine ROM, FIG. 3 is a block diagram of a conventional TBC, and FIG. FIG. 9 is a block diagram of a write clock generation circuit used in a conventional TBC. 1 …… Crystal oscillator 2 …… Band pass filter 3 …… D / A converter 4 …… 1/4 cycle delay device 5 …… D / A converter 6 …… A / D converter 7 …… Calculator 8 …… Initial phase setter 24 …… Write clock generation circuit

Claims (2)

(57) [Claims] A first reference signal generating means for generating a first reference signal; and a second signal having a phase orthogonal to a phase of the first reference signal in response to the first reference signal. Second reference signal generating means for generating a reference signal, detecting a phase difference between a predetermined input signal and the first reference signal, representing a detected phase difference, and providing a first signal having a phase orthogonal to each other. And a phase difference detecting means for outputting a second detection signal; and in response to the first reference signal, the second reference signal, and the first and second detection signals, Output clock signal generating means for generating a synchronized output clock signal, wherein the output clock signal generating means multiplies the first reference signal by the first detection signal; A second reference signal and the second detection signal; Comprising a second multiplying means for multiplying, and adding means for outputting the sum as the output clock signal by adding the respective outputs of said first and second multiplying means, clock generating circuit. 2. The phase difference detecting means samples the first reference signal in response to the input signal, and determines the absolute phase of the input signal based on the level of the sampled first reference signal. Sampling means to determine, a calculating means for calculating the phase difference between the predetermined absolute phase and a predetermined phase, storing predetermined sine wave data and cosine wave data, based on the sine wave data A memory for outputting the sine wave signal of the calculated phase difference as the first detection signal and outputting the cosine wave signal of the calculated phase difference based on the cosine wave data as the second detection signal. The clock generation circuit according to claim 1, further comprising: