JPH0614301A - Time base compensating device - Google Patents

Abstract

PURPOSE:To obtain a time base compensating device capable of increasing a variable range in the phase change of a clock signal and sufficiently correcting a time base error by preparing two phase locked loops. CONSTITUTION:A clock whose clock is almost phoselocked with that of a time base error included in a reproduced video signal 1 is formed by the 1st phase looked loop. In the 2nd phase looked loop, a signal obtained by dividing the frequency of the clock by a frequency divider 16 is phase-compared with a signal obtained by dividing a clock outputted through a variable delay means 15 by a frequency divider 22 by means of a phase comparator 23 and an output obtained from the comparator 23 is added to a phase-compared output from the 1st phase looked loop by an adder 24. The delay of the clock is controlled by a signal obtained from the adder 24. Thereby a phase locked clock is obtained also in the high frequency component of the time base error, and even when non-linearity exists in the delay means, the influence of the non- linearity does not appear in the phase of the clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction device for correcting a deviation (hereinafter referred to as a time base error) of a video signal read from a recording medium such as a video disk from a reference time axis.

[0002]

2. Description of the Related Art When a video signal recorded on a recording medium such as a video disc is read while rotating the recording medium, a time base error may occur in the obtained video signal due to eccentricity of the recording medium or uneven rotation of a rotating mechanism. Occurs,
It is well known that a reproduced image is adversely affected. Therefore, in a device such as a video disc player that reads a video signal from a recording medium such as a video disc, a time axis correction device that corrects a time base error is indispensable.

As a conventional time axis correction device, an analog / digital converting means for analog / digital converting a reproduced video signal obtained from a video disk to obtain a digital video signal, and a memory for temporarily storing the obtained digital video signal. Reading means for reading the digital video signal stored in the memory at a constant timing,
A digital time base collector is constituted by digital-analog conversion means for converting the read digital video signal into a digital-analog signal, and a horizontal synchronizing signal and / or a color burst signal separated from the reproduced video signal is input. A phase locked loop for generating a clock signal substantially in phase with a time base error contained in the reproduced video signal and a phase comparison output from a phase comparison means included in the phase locked loop are input, and the phase comparison output is output in accordance with the phase comparison output. And a phase modulation means for phase-modulating the clock signal, and the analog-digital conversion of the reproduced video signal in the analog-digital conversion means is known by the phase-modulated clock signal. (Japanese Patent Laid-Open No. 1-93273 Publication).

In the above-described conventional time base correction device, the phase shift of the clock signal is performed by the phase modulation performed by the phase modulator, and the variable range of the phase change of the clock signal by this phase shift, that is, the clock is formed. The variable range of the generation timing of one pulse is within the time corresponding to one cycle of the clock signal. When the frequency of the clock signal, that is, the sampling frequency is selected to be four times the color subcarrier frequency according to Nyquist's theorem, one cycle of the clock signal is about 70 ns. On the other hand, the variation range of the generation timing of one pulse forming the clock signal due to the time base error is ± 100
In some cases, it is difficult to obtain a phase modulating means having good linearity, and it is difficult to sufficiently correct the time base error in the conventional time axis correction device.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a time axis correction device capable of sufficiently correcting a time base error.

[0006]

According to the time axis correction apparatus of the present invention, a horizontal sync signal and a color burst signal separated from a reproduced video signal read from a recording medium are input and the time base error contained in the reproduced video signal is substantially in phase. A phase-locked loop that generates a synchronized clock,
A delay unit that delays the clock by a time corresponding to a control signal, a first frequency divider that divides the output of the delay unit by a predetermined frequency division ratio, and a second frequency divider that divides the clock by the predetermined frequency division ratio. The control signal is obtained by adding the frequency division means, the phase comparison means for performing phase comparison of the outputs of the first and second frequency division means, the output of the phase comparison means and the phase comparison output of the phase locked loop. The reproducing video signal is delayed by the time corresponding to the phase change of the output of the delaying unit, and is output.

[0007]

In the time axis correction apparatus according to the present invention, the phase locked loop generates a clock which is almost in phase with the time base error contained in the reproduced video signal, and the clock obtained by dividing this clock is delayed. The signal obtained by frequency-dividing the clock that has passed through the means is subjected to phase comparison, and the obtained phase comparison output and the phase comparison output of the phase-locked loop are added to form a signal, which delay-controls the clock.

[0008]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In FIG. 1, the input video signal supplied to the input terminal 1 is a signal read from a video disc and includes a time base error. This input video signal is A / D (analog / digital)
It is supplied to the converter 2, the burst amplifier 3, and the horizontal sync separation circuit 4. The horizontal sync separation circuit 4 separates the horizontal sync signal, and the burst amplifier 3 separates the color burst signal and shapes the waveform. When separating the color burst signal in the burst amplifier 3,
The horizontal sync signal from the horizontal sync separation circuit 4 is used.

The horizontal sync signal separated by the horizontal sync separation circuit 4 is supplied to the phase comparison circuit 5. In the phase comparison circuit 5, the horizontal synchronizing signal is a voltage controlled oscillator (hereinafter,
(Called VCO), which is the output of the color subcarrier frequency of 4
The clock signal having a doubled frequency is phase-compared with the signal obtained by dividing the frequency by the frequency divider 7 to the horizontal synchronizing frequency, and a signal corresponding to the phase difference between the two signals is generated and output. The color burst signal separated by the burst amplifier 3 and having its waveform shaped is supplied to the phase comparison circuit 8. In the phase comparison circuit 8, the color burst signal is phase-compared with the signal of the color subcarrier frequency obtained by dividing the clock signal by 1/4 by the frequency divider 9 and the signal corresponding to the phase difference between the two signals. Is generated and output.

The outputs of the phase comparison circuits 5 and 8 are the adder 1
After being added and synthesized by 1, the voltage is supplied to the control input terminal of the VCO 6 via the loop filter 12 to form a first phase-locked loop. In this first phase locked loop, the phase comparison circuits 5 and 8
After the time base error contained in the input video signal is detected by and is mixed by the adder 11 at an appropriate ratio,
It serves as a control input for the VCO 6 via the loop filter 12. As a result, the clock signal output from the VCO 6 has jitter according to the time base error.

The clock signal output from the VCO 6 is supplied to the variable delay circuit 15 and divided by the frequency divider 16 into, for example, 1/8. Variable delay circuit 15
Is configured to variably control the delay time in an analog manner according to the control input signal. The clock signal delayed by the variable delay circuit 15 is supplied to the A / D converter 2 and the memory controller 21, and is also divided into, for example, 1/8 by the frequency divider 22. Dividers 16 and 22
Is supplied to the phase comparison circuit 23 for phase comparison, and a signal corresponding to the phase difference between the two signals is generated and output. The output of the phase comparison circuit 23 is one input of the adder 24. The output of the adder 11 amplified by the amplifier 25 is supplied to the adder 24 as another input. The addition output of the adder 24 is supplied to the control input terminal of the variable delay circuit 15 via the loop filter 26 to form a second phase locked loop.

On the other hand, in the A / D converter 2, the VCO
6, the input video signal is sampled by the clock signal output from 6 and delayed by the variable delay circuit 15,
A digital signal corresponding to the obtained sample value is formed,
The input video signal is converted into a digital signal. This A
The video signal digitized by the / D converter 2 is sequentially written in the memory 27 by the memory controller 21. Address control at the time of writing to the memory 27 is performed based on the clock signal delayed by the variable delay circuit 15. The video signal written in the memory 27 is read out at a stable timing by the memory controller 27 performing address control based on the output pulse of the oscillator 29. The video signal read from the memory 27 is converted into an analog signal by the D / A converter 28, and then supplied to the output terminal 30 as a video signal from which the time base error has been removed.

FIG. 2 shows a block diagram of the first and second phase-locked loops having the above construction. In the figure, block B1 is the phase comparison circuits 5 and 8 and the adder 1.
1, the block B2 corresponds to the loop filter 12, the block B3 corresponds to the VCO 6, and the block B4 corresponds to the frequency dividers 7 and 9. The blocks B1 to B4 form a first phase locked loop.
Further, the block B5 corresponds to the frequency divider 16, and the block B5
6 corresponds to the amplifier 25. The block B7 corresponds to the variable delay circuit 15, the block B8 corresponds to the frequency divider 22, the block B9 corresponds to the phase comparison circuit 23, the block B10 corresponds to the adder 24, and the block B11 corresponds to the loop filter. 26, and the block B12 is an A / D converter 2
Corresponding to. The blocks B7 to B11 form a second phase locked loop.

For the first phase locked loop, the following equation 1 is established.

[0015]

[Equation 1]

In equation 1, I represents the input video signal, O1 represents the output of block B4, Ko1 represents the transfer function of block B3, Kd1 represents the transfer function of block B1, and F1 represents the transfer function of block B2. Represents a function, and s represents a complex variable. In each mathematical expression including this mathematical expression 1, the transfer function of each block B4, B5, B8 corresponding to each of the frequency dividers 7, 9, 16, 22 is set to 1.

The phase comparison output E, which is the output of the block B1 in the first phase locked loop, is expressed by the following equation 2.

[0018]

[Equation 2]

Further, regarding the second phase locked loop, the following expression 3 is established.

[0020]

[Equation 3]

In Equation 3, O2 represents the clock signal output from the block B7, Kd2 represents the transfer function of the block B9, A represents the transfer function of the block B6,
F2 represents the transfer function of the block B11, and Ko2 represents the transfer function of the block B7. By substituting the equations 1 and 2 into the equation 3, the following equation 4 is obtained.

[0022]

[Equation 4]

Here, assuming that A = Kd2, Equation 4 can be transformed into Equation 5 below.

[0024]

[Equation 5]

Further, since the frequency of the clock signal is high, it is easy to make the second phase locked loop have a sufficiently wide band, and by doing so, the following formula 6 is established.

[0026]

[Equation 6]

By substituting the equation 6 into the equation 5, the following equation 7 is obtained.

[0028]

[Equation 7]

From Equation 7, it can be seen that even if the variable delay circuit 15 has nonlinearity, its influence is canceled by the second phase locked loop, and a clock signal synchronized with the time base error of the input video signal can be obtained. Figure 1
In this device, the clock signal is used for A / D conversion of the input video signal and writing of the digital signal obtained by this A / D conversion into the memory 27. The output pulse of the oscillator 29 reads the digital signal from the memory 27 at a constant timing and then D / A-converts and outputs the digital signal. Therefore, the input video signal is delayed according to the time base error. It will be output and the time base error will be removed.

[0030]

As described above in detail, according to the time axis correction apparatus of the present invention, the phase locked loop generates a clock which is almost in phase with the time base error contained in the reproduced video signal, and divides this clock. The signal obtained by dividing the clock that has passed through the delay means is phase-compared, and the phase comparison output obtained and the phase comparison output of the phase-locked loop are added to form a signal that delays the clock. Since it is controlled, a clock phase-synchronized with the high frequency component of the time base error can be obtained, and even if there is non-linearity in the delay means, the clock phase is not affected. At the same time, the variable range of the delay time of the delay means can be increased so that the variable range of the clock phase can be made sufficiently larger than the value corresponding to one cycle of the clock. By delaying the reproduced video signal by the time, the time base error can be sufficiently corrected.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

2 is a block diagram of the device of FIG. 1. FIG.

[Explanation of symbols for main parts]

3 ... Burst amplifier 4 ... Horizontal sync separation circuit 5, 8, 23 ... Phase comparison circuit 6 ... VCO 7, 9, 16, 22 ... Frequency divider 11 ... Adder 12, 26 ... Loop filter 15 ... Variable delay circuit 24 ... Adder 25 ... Amplifier

Claims (1)

[Claims] 1. A phase-locked loop which receives a horizontal synchronizing signal and a color burst signal separated from a reproduced video signal read from a recording medium and generates a clock substantially in phase with a time base error contained in the reproduced video signal. A delay means for delaying the clock by a time corresponding to a control signal; a first frequency dividing means for dividing an output of the delay means by a predetermined frequency division ratio; and a frequency division of the clock by the predetermined frequency division ratio. Second frequency dividing means, and the first and second
The delay means comprises: a phase comparison means for performing phase comparison of outputs of the frequency division means; and an addition means for adding the output of the phase comparison means and the phase comparison output of the phase locked loop to generate the control signal. A time axis correction device for delaying and outputting the reproduced video signal for a time corresponding to a phase change of the output of the.