JPH03272184A - Insulated-gate bipolar transistor - Google Patents

Insulated-gate bipolar transistor

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Publication number
JPH03272184A
JPH03272184A JP7403490A JP7403490A JPH03272184A JP H03272184 A JPH03272184 A JP H03272184A JP 7403490 A JP7403490 A JP 7403490A JP 7403490 A JP7403490 A JP 7403490A JP H03272184 A JPH03272184 A JP H03272184A
Authority
JP
Japan
Prior art keywords
mask
semiconductor layer
bipolar transistor
semiconductor
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7403490A
Other languages
Japanese (ja)
Other versions
JP2818959B2 (en
Inventor
Hajime Akiyama
肇 秋山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
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Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2074034A priority Critical patent/JP2818959B2/en
Publication of JPH03272184A publication Critical patent/JPH03272184A/en
Application granted granted Critical
Publication of JP2818959B2 publication Critical patent/JP2818959B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body

Abstract

PURPOSE:To obtain a semiconductor device improved in switching speed and lessened in loss by a method wherein crystal defect is partially formed in a second semiconductor layer of second conductivity type formed on the surface of a first semiconductor layer of first conductivity type. CONSTITUTION:A bipolar transistor of this design is different from a conventional one in following points: a metal absorber 60 of Al or the like is provided to the surface of a collector electrode formed on the other primary face; a mask 61 of stainless steel or the like provided with fine openings is provided thereon; and a light ion beam of He or the like is made to irradiate through the intermediary of the absorber 60 and the mask 61 for the formation of the bipolar transistor. At this point, the acceleration energy and the thickness of the absorber 60 are regulated so as to enable the range of the light ion beam 50 which passes through the fine openings provided to the mask 61 to lie inside a P<+> collector layer 1. By this setup, crystal defects are formed in a region correspondent to the pattern of fine openings provided to the mask 61, whereby a partial lifetime control can be carried out.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は絶縁ゲート型バイポーラトランジスタ(In
5ulated Gate Bipolar Tran
sistor ;以下、IGBTと称す)に関し、特に
ライフタイム制御に伴うターンオフ時間とオン抵抗との
トレードオフ関係の改善及びスイッチング損失の低減を
図るものに関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an insulated gate bipolar transistor (Insulated gate bipolar transistor).
5ulated Gate Bipolar Tran
The present invention relates to IGBTs (hereinafter referred to as IGBTs), and particularly to devices that aim to improve the trade-off relationship between turn-off time and on-resistance associated with lifetime control and reduce switching loss.

〔従来の技術〕[Conventional technology]

バイポーラトランジスタは、一般に低出力インピーダン
スであるが、入力インピーダンスも低い問題がある。一
方、電界効果トランジスタ(以下、MOSFETと称す
)は高入力インピーダンスであるが、出力インピーダン
スも高い問題がある。これらに対し、I GBTはこれ
ら各種トランジスタのもつ欠点を補うように一体化し、
高人力インピーダンスであり、かつ、低出力インピーダ
ンスを実現しようとするものである。
Bipolar transistors generally have low output impedance, but also have a problem of low input impedance. On the other hand, field effect transistors (hereinafter referred to as MOSFETs) have a high input impedance, but also have a problem of high output impedance. In contrast, IGBTs are integrated to compensate for the shortcomings of these various transistors.
The aim is to achieve high human power impedance and low output impedance.

すなわち、表面にMOSFETを形成する基板の裏面に
、基板と異なる導電型の高a度不純物拡散層をつくりこ
むことによって、バイポーラトランジスタとMOSFE
Tを一体化し、かつMOSFETがオンすることにより
生じる電流をパイボーラトランジ(1) スタのベース領域に注入して、注入電流によりバイポー
ラトランジスタを制御するものである。
In other words, by creating a high a degree impurity diffusion layer of a conductivity type different from that of the substrate on the back side of the substrate on which the MOSFET is formed, a bipolar transistor and a MOSFET can be formed.
The bipolar transistor is controlled by the injected current by integrating the T and injecting the current generated when the MOSFET is turned on into the base region of the bipolar transistor (1) star.

一般に、I GBT装置は多数のI GBT素子(以ト
、IGBTセルと称す)が並列接続された構造を有して
いる。第7図は従来のnチャネル型のI GBT セル
の構造を示す断面図であり、第8図はその等価回路を示
す回路図である。
Generally, an IGBT device has a structure in which a large number of IGBT elements (hereinafter referred to as IGBT cells) are connected in parallel. FIG. 7 is a sectional view showing the structure of a conventional n-channel type I GBT cell, and FIG. 8 is a circuit diagram showing its equivalent circuit.

第7図において、(1)はPコレクタ層であり、その一
方主面上にはNエピタキシャル層(2)が形成されてい
る。Nエピタキシャル層(2)の表面の一部鎚域には、
P形不純物を選択的に拡散することによりPウェル領域
(3)が形成され、さらにこのPウェル頭載(3)の表
面の一部頻域には、高醪度のN形不純物を選択的に拡散
することによりN+エミッタ囮域(4)が形成されてい
る。Nエピタキシャル@(2)の表面とN+エミッタ賄
域(4)の表面とで挾まれたPウェル領域(3)の表面
上にはゲート絶縁膜(5)が形成され、このデー1−1
.縁膜(51は隣接するI GBTセル間で一体となる
ようNエピタキシャル層(2)の表m−hにも形成され
ている。ゲート絶縁膜(5)上には、例えばポリシリコ
ンから成るゲート電極(6)が形成され、またPウェル
頭載(3)およびN+エミッタ頗頭載4)の両方に電気
的に接続するように、例えばアルミニウムなどの金嘱の
エミッタ電極(7)が形成されている。なお、ゲート電
極(6)およびエミッタ電極(7は、#@縁膜(8)を
介した多層構造とすることにより、全I GBTセルに
対してそれぞれ共通に電気的につながった構造となって
いる。Pコレクタ層(1)の裏面には金属のコレクタ電
極(9)が全I GBTセルに対し一体に形成されてい
る。
In FIG. 7, (1) is a P collector layer, and an N epitaxial layer (2) is formed on one main surface thereof. In some areas of the surface of the N epitaxial layer (2),
A P-well region (3) is formed by selectively diffusing P-type impurities, and high-strength N-type impurities are selectively added to a part of the surface of the P-well head (3). An N+ emitter decoy region (4) is formed by diffusion into the N+ emitter decoy region (4). A gate insulating film (5) is formed on the surface of the P well region (3) sandwiched between the surface of the N epitaxial @ (2) and the surface of the N+ emitter covering region (4).
.. The edge film (51) is also formed on the surface m-h of the N epitaxial layer (2) so as to be integrated between adjacent IGBT cells.A gate made of, for example, polysilicon is formed on the gate insulation film (5). An electrode (6) is formed and an emitter electrode (7) of metal, e.g. aluminum, is formed to electrically connect both the P-well head (3) and the N+ emitter head (4) ing. Note that the gate electrode (6) and emitter electrode (7) have a multilayer structure via the #@edge film (8), so that they are electrically connected in common to all IGBT cells. A metal collector electrode (9) is integrally formed on the back surface of the P collector layer (1) for all IGBT cells.

Nエピタキシャル層(2)とN+エミッタ鎮域(4)と
で挾まれたPウェル領域(3)の表面近傍はnチャネル
のMO5構造となっており、ゲート端子Gを通じてゲー
ト電極(6)に正電圧を印加することにより、ゲート電
極(6)の直下のPウェル頭載(3)の表面近傍に形成
されたチャネルを通じて、電子がN+エミッタ飴域(4
)よりNエピタキシャル層(2)へと流れる。図示■。
The vicinity of the surface of the P well region (3) sandwiched between the N epitaxial layer (2) and the N+ emitter region (4) has an n-channel MO5 structure, and a positive electrode is connected to the gate electrode (6) through the gate terminal G. By applying a voltage, electrons are transferred to the N+ emitter region (4) through a channel formed near the surface of the P-well head (3) directly under the gate electrode (6).
) to the N epitaxial layer (2). Illustration ■.

はこの様にして流れる電子電流、を示す。一方、+ Pコレクタ層(1)からは少数キャリアである正孔がN
エピタキシャル層(2)に注入され、その一部は上記電
子と再結合して消滅し、残りは図示の正孔電流工りとし
てPウェル頭載(3)を流れる。この様に■GBTは、
基本的にバイポーラ的な動作をし、N−エピタキシャル
層(2)では、電導度変稠の効果から電導度が増大する
ことにより、従来のパワーMO8に比べて低いオン電圧
、大きい電流容量を実現できる利点がある。
represents the electron current flowing in this way. On the other hand, holes, which are minority carriers, are transferred from the +P collector layer (1) to N
It is injected into the epitaxial layer (2), a part of which recombines with the electrons and disappears, and the rest flows through the P-well head (3) as a hole current as shown. In this way, ■GBT is
Basically, it operates in a bipolar manner, and the N-epitaxial layer (2) increases the conductivity due to the effect of conductivity variation, achieving a lower on-voltage and larger current capacity than the conventional power MO8. There are advantages that can be achieved.

なお、第8図において、(10)はNエピタキシャル層
(2)、Pウェル領域(3)およびN+エミッタ頗頭載
4)より成る寄生NPN )ランジスタ、ul)はPコ
レクタ層+1+、Nエピタキシャル層(2(およびPウ
ェル頭載(3)よりなるPNP l−ランジスタ、t1
2)はゲート電極(6)下のPウェル頭載(31表面を
チャネル頭載としたNMOSトランジスタ、RBはPウ
ェル領域(3)の拡散抵抗、RLCはPNP トランジ
スタ1ullのオン抵抗を示している。
In FIG. 8, (10) is a parasitic NPN transistor consisting of an N epitaxial layer (2), a P well region (3) and an N+ emitter mount 4), and ul) is a P collector layer +1+ and an N epitaxial layer. PNP l-transistor consisting of (2 (and P-well head mounted (3), t1
2) is an NMOS transistor with a channel head mounted on the P well region (31 surface) under the gate electrode (6), RB is the diffusion resistance of the P well region (3), and RLC is the on-resistance of 1ull of the PNP transistor. .

I GBTは上記のような利点がある反面、ターンオフ
時には正孔電流Ihの減少がMOSFET等に比へて時
間的にゆっくりしているため、動作周波数を上げられな
い嫌いがある。これは、PNP トランジスタ(]J)
がオン状態のとき、そのベース頭載となるNエピタキシ
ャル@(2)内には電子と正孔とが充満しており、MO
S )ランジスタ叩をオフさせて、Nエピタキシャル層
(2)への電子の注入を遮断しても、正札はその移動度
の小ささから急には減少しないことに起因している。
Although the IGBT has the above-mentioned advantages, it has the disadvantage that the operating frequency cannot be increased because the hole current Ih decreases more slowly at turn-off than in a MOSFET or the like. This is a PNP transistor (]J)
When is in the on state, the N epitaxial layer @ (2) which is mounted on the base is filled with electrons and holes, and the MO
S) This is due to the fact that even if the transistor is turned off to block the injection of electrons into the N epitaxial layer (2), the genuine bill does not suddenly decrease due to its low mobility.

このターンオフ時間を短縮させるために従来から大別し
て二つの手段が知られている。その一つは金や白金など
の改金属原子を、所謂ライフタイムキラーとして、PN
Pトランジスタ(11)のベース領域であるNエピタキ
シャル層(2)内に導入する手段であり、このライフタ
イムキラーがN−エピタキシャル@(2)内の電子と正
孔の再結合中心となってこれらのキャリアを短時間内に
消滅させる。
In order to shorten this turn-off time, two methods are known. One of them is to use modified metal atoms such as gold and platinum as so-called lifetime killers.
This is a means of introducing into the N-epitaxial layer (2) which is the base region of the P-transistor (11), and this lifetime killer becomes a recombination center for electrons and holes in the N-epitaxial layer (2). carrier will disappear within a short period of time.

もう一つは電子線、γ線、中性子線、各種イオン線等の
放射線を照射する手段であり、これらの放射線はN−エ
ピタキシャル層(2)内に深いトラップ準位を導入する
ことから、このトラップ準位がキャリアに対する再結合
中心となるため、ターンオフ時には、キャリアを短時間
内に消滅させることができる。これらの技術はライフタ
イム制御技術と呼ばれ、サイリスタや電力用ダイオード
等種々の素子に適用されている。
The other method is to irradiate radiation such as electron beams, gamma rays, neutron beams, and various ion beams.Since these radiations introduce deep trap levels within the N-epitaxial layer (2), this Since the trap level serves as a recombination center for carriers, carriers can be annihilated within a short time at turn-off. These techniques are called lifetime control techniques and are applied to various elements such as thyristors and power diodes.

一般に放射線照射によるライフタイム制御技術は制御性
や再現性の点から屯金属拡散に比較して良い結果が得ら
れている。しかしながら、放射線照射の中で、電子線、
γ線、中性子線を用いた方法では、照射によりNエピタ
キシャル層)2)内でのトラップ準位が発生するととも
に、同時にゲート酸化膜(5)の膜質を変化させてしま
い、結果として値までも変化させ、その動作信頼性を低
下させる問題がある。この問題はプロトン等の各種イオ
ン線をコレクタ電極(9)側から照射する方法により解
決される。すなわち、第4図に示したようにプロトン等
の各種軽イオン線−をコレクタ電極(9)の形成されて
いる側から照射し、その飛程位置をNエピタキシャル層
(2)の中に設定されるように(第7図中破線で示す)
、その加速エネルギーを調整することによりゲート絶縁
膜(5)及びその他、エミッタ側形成各層+31 、 
!41になんら影響を与えることなくライフタイム制御
を行うことができる。
In general, lifetime control technology using radiation irradiation has yielded better results in terms of controllability and reproducibility than tunic metal diffusion. However, during radiation irradiation, electron beams,
In methods using gamma rays and neutron beams, the irradiation generates trap levels in the N epitaxial layer (2), and at the same time changes the film quality of the gate oxide film (5), resulting in changes in the value as well. There are problems that can cause changes and reduce its operational reliability. This problem can be solved by a method of irradiating various ion beams such as protons from the collector electrode (9) side. That is, as shown in Fig. 4, various light ion beams such as protons are irradiated from the side where the collector electrode (9) is formed, and the range position is set in the N epitaxial layer (2). (as shown by the broken line in Figure 7)
, by adjusting the acceleration energy, the gate insulating film (5) and other layers formed on the emitter side +31,
! Lifetime control can be performed without affecting 41 in any way.

更に、プロトン等の各種イオン照射による結晶欠陥(主
に空孔)は第9図に示すように、その飛程りを中心とし
て、欠陥分布ピーク半値幅W中に集中的に発生し、それ
以外の場所にはあまり影響を与えない特質をもっている
。この特質を利用することにより、制御性の高いライフ
タイム制御を実行することが可能である。例えば、特開
昭64−19771  に示されたように、Pコレクタ
領域(第7図のPコレクタ層(1)に相当)に近いN−
ベース領域(第7図のNエピタキシャル層(2)に相当
)内に飛程りを設定することにより効果的なライフタイ
ム制御を行うことができる。これは、MOSFETに近
いベース舶載はMOSFETのチャネルから注入される
キャリアが引き金となって1大溝度変調を生じる上で@
要な役割を果たすから、この部分に結晶欠陥を発生させ
るとオン抵抗を増大させることになるため、MOSFE
Tのチャネル舶載から最も離れている、Pコレクタ領域
に近いN−ベース領域にイオン線の飛程が来るようにす
るのが望ましいからである。また、オフ動作時の初期ま
で引き続いて注入されている正孔を早く捕捉するために
も、P+コレクタ餉域に近いNベース領域で結晶欠陥を
集中的に発生させるのは有効である。
Furthermore, as shown in Figure 9, crystal defects (mainly vacancies) due to irradiation with various ions such as protons occur intensively in the half-width W of the defect distribution peak, centered on the range, and other than that. It has characteristics that do not affect the location much. By utilizing this characteristic, it is possible to perform lifetime control with high controllability. For example, as shown in JP-A-64-19771, N-
By setting the range in the base region (corresponding to the N epitaxial layer (2) in FIG. 7), effective lifetime control can be performed. This is because carriers injected from the channel of the MOSFET are triggered by the carriers injected from the channel of the MOSFET, causing one major groove modulation.
Since it plays an important role, generating crystal defects in this part will increase the on-resistance, so
This is because it is desirable for the range of the ion beam to reach the N-base region closest to the P collector region, which is farthest from the T channel. Furthermore, in order to quickly capture holes that are continuously injected until the initial stage of off-operation, it is effective to intensively generate crystal defects in the N base region near the P+ collector region.

〔発明が解決しようとする課題1 しかしながら、上記したライフタイム制御は全て、結晶
欠陥をIGBT素子全面に渡って生じさせていることに
は変りがないため、この結晶欠陥の発生に伴い、Nエピ
タキシャル層(2)の抵抗値が必然的に上昇し、第8図
におけるI GBTのオン抵抗RLCが増加してしまう
。つまり、IGBTのオン抵抗とターンオフ時間とはト
レードオフの関係にあり、現状においてそのトレードオ
フ関係が最適とはいえない問題点かあった。
[Problem to be Solved by the Invention 1] However, all of the above-mentioned lifetime controls still generate crystal defects over the entire surface of the IGBT element. The resistance value of layer (2) inevitably increases, and the on-resistance RLC of the IGBT in FIG. 8 increases. In other words, there is a trade-off relationship between the on-resistance and turn-off time of the IGBT, and there is a problem in that the trade-off relationship is not optimal at present.

この発明は上記のような問題点を解決するためKなされ
たもので、イオン線などの電離放射線照射を用いたライ
フタイム制御による、オン折抗とターンオフ時間とのト
レードオフ関係を最善にした構造のIGBTを得ること
を目的とする。
This invention was made to solve the above-mentioned problems, and it is a structure that optimizes the trade-off relationship between on-turn and turn-off times through lifetime control using irradiation with ionizing radiation such as ion beams. The purpose is to obtain an IGBT of

〔課題を解決するための手段〕[Means to solve the problem]

この発明にかかる絶縁ゲート型バイポーラトランジスタ
は、第1の導電形の第2の半導体層と、前記第1の半導
体領域の表面に選択的に形成された第2の導電形の第2
の半導体領域と、前記第2の半導体層と、前記第2の半
導体領域とで挾まれた前記第1の半導体領域の表面上に
形成された絶縁膜と前記絶縁膜上に形成された制御電極
と、前記第1及び第2の半導体舶載にまたがって形成さ
れた第1の主電極と、前記第1の半導体層の裏面上に形
成された第2の主電極とを備え、@記第2の半導体「n
域の前記第1の半導体領域との接合部寄りに部分的に結
晶欠陥を有するように構成したものである。
The insulated gate bipolar transistor according to the present invention includes a second semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type selectively formed on the surface of the first semiconductor region.
a semiconductor region, a second semiconductor layer, an insulating film formed on a surface of the first semiconductor region sandwiched by the second semiconductor region, and a control electrode formed on the insulating film. and a first main electrode formed across the first and second semiconductor layers, and a second main electrode formed on the back surface of the first semiconductor layer, 2 semiconductor “n
The structure is such that crystal defects are partially present near the junction with the first semiconductor region.

〔作 用] この発明における絶縁ゲート型バイポーラトランジスタ
においては、その構成要素である等節回路上のバイポー
ラトランジスタは、第1の半導体領域、結晶欠陥を有さ
ない第2の半導体層及び結晶欠陥を有する第1の半導体
層から成る第1のバイポーラトランジスタと、第1の半
導体領域、結晶欠陥を有する第2の半導体層及び結晶欠
陥を有さない第1の半導体層から成る第2のバイポーラ
トランジスタとの並列接続により構成されると等節約に
みなすことができる。
[Function] In the insulated gate bipolar transistor of the present invention, the bipolar transistor on the equinodal circuit, which is a component thereof, includes a first semiconductor region, a second semiconductor layer having no crystal defects, and a second semiconductor layer having no crystal defects. a first bipolar transistor consisting of a first semiconductor layer having a first semiconductor region, a second semiconductor layer having crystal defects, and a second bipolar transistor consisting of a first semiconductor layer having no crystal defects; It can be considered to be equally economical to configure it by connecting in parallel.

第1のバイポーラトランジスタは、第1の半導体層に結
晶欠陥を有していても第2の半導体層に結晶欠陥を有さ
ないため、長所としてオン抵抗は低く、短所としてター
ンオフ時間は長い。一方、第2のバイポーラトランジス
タは、第2の半導体層に結晶欠陥を有するため、短所と
してオン抵抗は高く、長所としてターンオフ時間は短い
The first bipolar transistor has a crystal defect in the first semiconductor layer but does not have a crystal defect in the second semiconductor layer, so its advantage is that the on-resistance is low, and its disadvantage is that the turn-off time is long. On the other hand, since the second bipolar transistor has crystal defects in the second semiconductor layer, its disadvantage is that its on-resistance is high, and its advantage is that its turn-off time is short.

第1、第2のバイポーラトランジスタが並列に接続され
′Cいることにより、オン状態では第1のバイポーラト
ランジスタが、又ターンオフ時には第2のバイポーラト
ランジスタが支配的に働くので、低オン電圧、高速スイ
ッチングを実現する。
Since the first and second bipolar transistors are connected in parallel, the first bipolar transistor works dominantly in the on state, and the second bipolar transistor works dominantly in the turn-off state, resulting in low on-voltage and high-speed switching. Realize.

〔実施例〕〔Example〕

以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

なお、従来の技術の説明と重複する部分は、適宜その説
明を省略する。
Note that the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.

第1図はこの発明の一実施例のI GBTの構造を示す
断面図である。図において、(1)〜(9)は従来と同
じである。
FIG. 1 is a sectional view showing the structure of an IGBT according to an embodiment of the present invention. In the figure, (1) to (9) are the same as before.

その異なる点は、他主面側におけるコレクタ電極(9)
の表面にアルミニウム等の金属のアブゾーバ(60、啜
にその表面に微細な開口を形成したステンレス等のマス
ク(61)を設け、これらを介してヘリウム等の軽イオ
ン線(50)を照射して形成させるものである。ここで
、マスク(61)の微細開口を通過した部分の軽イオン
線(50)はNベース層(2+内に飛程位置が設゛定さ
れるよう加速エネルギーとアブゾーバ□□□との厚さが
調整される。また、マスク(61)の微細開口を除く明
域を通過した軽イオン線00)はPコレクタ@(1)内
に飛程位置が設定されるようマスク(61)の厚さが調
整される。これにより、微細開口のパターンをほぼ反映
した舶載を部分的なライフタイム制御が行なわれるもの
とすることができる。第2図は第1図に示すものの等節
回路を示す回路図である。図において、(10’l 、
 (121は従来のものと同じもの、(13)はライフ
タイム制御されない明域に形成された内蔵PNP トラ
ンジスタ、tl、11は部分的にライフタイム制御され
た領域を有する内蔵PNP トランジスタである。
The difference is that the collector electrode (9) on the other main surface side
A metal absorber (60) made of aluminum or the like, and a mask (61) made of stainless steel or the like with minute openings formed on the surface are provided on the surface, and a light ion beam (50) such as helium is irradiated through these. Here, the portion of the light ion beam (50) that has passed through the fine aperture of the mask (61) is charged with acceleration energy and absorber □ so that the range position is set within the N base layer (2+). The thickness of the mask (61) is adjusted so that the range position of the light ion beam 00) that has passed through the bright region excluding the fine aperture of the mask (61) is set within the P collector @ (1). The thickness of (61) is adjusted. As a result, partial lifetime control can be performed for loading on ships that almost reflects the pattern of fine apertures. Figure 2 is shown in Figure 1. It is a circuit diagram showing an isochoric circuit of things. In the figure, (10'l,
(121 is the same as the conventional one, (13) is a built-in PNP transistor formed in a bright region whose lifetime is not controlled, and tl, 11 is a built-in PNP transistor with a region whose lifetime is partially controlled.

第3図は軽イオン線([10)か部か的に照射された工
GBTと、軽イオン線幅0)が全面照射されたIGBT
とのトレードオフ特性について比較した図である。
Figure 3 shows an engineered GBT partially irradiated with a light ion beam ([10) and an IGBT fully irradiated with a light ion line width 0).
FIG. 3 is a diagram comparing trade-off characteristics with

この場合、軽イオン線150)には2価のヘリウムイオ
ン(He  )を用い、その加速エネルギーは20Me
Vである。また、アブゾーバ(60)は厚さが30μm
のアルミニウムで構成し、マスク(6I)は厚さが50
μmのステンレスで構成したものである。マスク161
)に形成した微細開口は2種類あり、マスク1は半径γ
が140 /7m の内形窓を、窓間ピッチ200μm
で形成したものであり、マスク2は半径γが160μm
の円形窓を、窓間ピッチ200μmで形成したものであ
る。
In this case, divalent helium ions (He) are used as the light ion beam 150), and their acceleration energy is 20Me
It is V. Also, the absorber (60) has a thickness of 30 μm.
The mask (6I) has a thickness of 50 mm.
It is made of μm stainless steel. mask 161
) There are two types of fine openings formed in the mask 1 with radius γ
is 140/7m, with a pitch of 200μm between the windows.
The mask 2 has a radius γ of 160 μm.
The circular windows were formed with a pitch of 200 μm between the windows.

これよりマスク1、マスク2を用いて部分照射したもの
が、全面照射したものに比べて改善されたトレードオフ
曲線を有することがわかる。
From this, it can be seen that the partial irradiation using Mask 1 and Mask 2 has an improved trade-off curve compared to the whole irradiation.

ところで、第4図はtM、 FEt−Vonが約3.3
■のIGBT暉料について、全面照射、部分照射したも
ののターンオフ波形特性を比較した図である。全面照射
したものに対してマスク2による部分照射したものでは
、ティルミ流が減少しているのがわかる。
By the way, in Figure 4, tM and FEt-Von are approximately 3.3.
FIG. 3 is a diagram comparing the turn-off waveform characteristics of the IGBT material (2) subjected to full irradiation and partial irradiation. It can be seen that the Tilmi flow is reduced in the case where partial irradiation using mask 2 is performed compared to the case where the entire surface is irradiated.

また、第5図は同様にターンオフ時の損失を比較した図
である。マスク(61)の開口が微細化されるにつれて
、ターンオフ損失は低減しており、マスク2による部分
照射では高温状態(図示TA=125℃)においても全
面照射の43910までターンオフ損失を低減できるも
のとなっている。
Further, FIG. 5 is a diagram similarly comparing losses at turn-off. As the aperture of the mask (61) becomes finer, the turn-off loss decreases, and with partial irradiation using mask 2, it is possible to reduce the turn-off loss to 43910 with full irradiation even in high temperature conditions (TA = 125°C in the figure). It has become.

第6図はこの発明の他の実施例のI GBTの構造を示
す断面図である。このものが第1図に示すものと異なる
点は、アブゾーバ+6CI、マスク(61)を−主面側
におけるエミッタ電極(7)上に設置し、それを介して
軽イオン線00)を照射して形成させたものである。こ
の場合にも、アブゾーバ+6(9をアルミニウム等の金
属で形成し、マスク+61)をステンレス等で形成した
ものを用いている。マスク(61)には微細開口が設け
られており、このマスク(61)を介して2価のヘリウ
ムイオン(He  )等の軽イオン線1150)を照射
する。このとき、マスク則の微細開口を除く領域を通過
した軽イオン線用は、Nベース層(2)内の+ 42175層(1)との接合部寄りの領域に飛程位置が
設定されるように、軽イオンの加速エネルギー条件、ア
ブゾーバ(60、マスク刑の卑さか調整される。また、
マスク(61)の微細開口を通過した軽イオン線115
0)は、42175層(1)内に飛程位置が設定される
ようアブゾーバ闘の厚さが調整される。このようにして
製造されたI GBTの等何回路は第2図に示すものと
なる。従って、このものにおいてもトレードオフ関係、
損失等の改善効果は第1図に示すものと同程度に期待で
きる。
FIG. 6 is a sectional view showing the structure of an IGBT according to another embodiment of the invention. This device differs from the one shown in Figure 1 in that an absorber +6CI and a mask (61) are installed on the emitter electrode (7) on the − main surface side, and a light ion beam 00) is irradiated through it. It was formed. In this case as well, an absorber +6 (9 made of metal such as aluminum, mask +61) made of stainless steel or the like is used. The mask (61) is provided with a fine opening, and a light ion beam 1150 such as divalent helium ions (He 2 ) is irradiated through the mask (61). At this time, for the light ion beam that has passed through the area excluding the fine aperture according to the mask rule, the range position is set in the area near the junction with the +42175 layer (1) in the N base layer (2). In addition, the light ion acceleration energy conditions, absorber (60, and the lowliness of the mask punishment) are adjusted.
Light ion beam 115 passed through the fine aperture of the mask (61)
0), the thickness of the absorber battle is adjusted so that the range position is set within the 42175th layer (1). The IGBT circuit manufactured in this manner is shown in FIG. Therefore, in this case too, there is a trade-off relationship,
The improvement effect on loss etc. can be expected to be the same as that shown in FIG.

なお、上記実施例において、軽イオンとしてヘリウムを
用いた場合について示したが、他の軽イオン、例えばプ
ロトン等を用いても上記と同様の効果を奏する。
In the above embodiment, the case where helium was used as the light ion was shown, but the same effect as described above can be obtained even if other light ions such as protons are used.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば第2の導電形の第2の
半導体層内に部分的に結晶欠陥を形成したので、スイッ
チング速度を向上させ、損失が低減された半導体装置を
得られる効果がある。
As described above, according to the present invention, since crystal defects are partially formed in the second semiconductor layer of the second conductivity type, it is possible to improve the switching speed and obtain a semiconductor device with reduced loss. There is.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例であるI GBTを示す断
面図、第2図は第1図に示すものの等何回路を示す回路
図、第3図は軽イオン線が部分的に照射されたI GB
Tと全面に照射されたI GBTとのトレードオフ特性
について比較した図、第4図は軽イオン線が部分的、全
所的に照射されたIGBTのターンオフで波形特性につ
いて比較した図、第5図は同様にターンオフ時の損失を
比較した図、第6図はこの発明の他の実施例のI GB
Tの構造を示す断面図、第7図は従来のI GBTの構
造を示す断面図、第8図は第7図に示すものの等価口路
図、第9図は照射イオンの飛程とそれによって形成され
る結晶欠陥分布の関係を示す図である。 図において、(1)はP+コレクタ層、(2)はNベー
ス層、(3)はPウェル頭載、141はNエミッタ領域
、(5)はゲート絶縁膜、(6)はゲート電極、(7)
はエミッタ電極、(8)は絶縁膜、(9)はコレクタ電
極、輔は軽イオン線、+61はアブゾーバ、 16++
はマスクである。 なお、各図中同一符号は同一、又は相当部分を示す。
Fig. 1 is a cross-sectional view showing an IGBT which is an embodiment of the present invention, Fig. 2 is a circuit diagram showing a circuit similar to that shown in Fig. I GB
Figure 4 is a diagram comparing the trade-off characteristics between T and an IGBT whose entire surface is irradiated. Figure 4 is a diagram which compares the waveform characteristics at turn-off of an IGBT which is partially and fully irradiated with light ion beams. Figure 5 This figure similarly compares the loss at turn-off, and FIG. 6 shows the IGB of another embodiment of the present invention.
7 is a sectional view showing the structure of a conventional IGBT, FIG. 8 is an equivalent path diagram of the one shown in FIG. 7, and FIG. 9 is a diagram showing the range of irradiated ions and FIG. 3 is a diagram showing the relationship between the distribution of crystal defects formed. In the figure, (1) is the P+ collector layer, (2) is the N base layer, (3) is the P well head, 141 is the N emitter region, (5) is the gate insulating film, (6) is the gate electrode, ( 7)
is the emitter electrode, (8) is the insulating film, (9) is the collector electrode, is the light ion beam, +61 is the absorber, 16++
is a mask. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)、第1の導電形の第1の半導体層の表面に形成さ
れた第2の導電形の第2の半導体層と、前記第1の半導
体層の表面に選択的に形成された第2の導電形の第2の
半導体領域と、前記第2の半導体層と前記第2の半導体
領域とで挾まれた前記第1の半導体領域の表面上に形成
された絶縁膜と、前記絶縁膜上に形成された制御電極と
、前記第1および第2の半導体領域にまたがって形成さ
れた第1の主電極と、前記第1の半導体層の裏面上に形
成された第2の主電極とを備え、前記第2の半導体領域
の前記第1の半導体領域との接合部寄りに部分的に結晶
欠陥を有していることを特徴とする絶縁ゲート型バイポ
ーラトランジスタ。
(1) a second semiconductor layer of a second conductivity type formed on the surface of the first semiconductor layer of the first conductivity type; and a second semiconductor layer selectively formed on the surface of the first semiconductor layer. a second semiconductor region of conductivity type 2; an insulating film formed on a surface of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region; and the insulating film. a control electrode formed above, a first main electrode formed across the first and second semiconductor regions, and a second main electrode formed on the back surface of the first semiconductor layer; An insulated gate bipolar transistor characterized in that the second semiconductor region has a crystal defect partially near a junction with the first semiconductor region.
JP2074034A 1990-03-22 1990-03-22 Insulated gate bipolar transistor Expired - Lifetime JP2818959B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2074034A JP2818959B2 (en) 1990-03-22 1990-03-22 Insulated gate bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2074034A JP2818959B2 (en) 1990-03-22 1990-03-22 Insulated gate bipolar transistor

Publications (2)

Publication Number Publication Date
JPH03272184A true JPH03272184A (en) 1991-12-03
JP2818959B2 JP2818959B2 (en) 1998-10-30

Family

ID=13535465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2074034A Expired - Lifetime JP2818959B2 (en) 1990-03-22 1990-03-22 Insulated gate bipolar transistor

Country Status (1)

Country Link
JP (1) JP2818959B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007103770A (en) * 2005-10-06 2007-04-19 Sanken Electric Co Ltd Insulated gate bipolar transistor
JP2010147239A (en) * 2008-12-18 2010-07-01 Toshiba Corp Semiconductor device and method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57115260U (en) * 1981-01-09 1982-07-16
JPH01149481A (en) * 1987-11-03 1989-06-12 Siemens Ag With four-layer construction
JPH01199469A (en) * 1988-02-04 1989-08-10 Toshiba Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57115260U (en) * 1981-01-09 1982-07-16
JPH01149481A (en) * 1987-11-03 1989-06-12 Siemens Ag With four-layer construction
JPH01199469A (en) * 1988-02-04 1989-08-10 Toshiba Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007103770A (en) * 2005-10-06 2007-04-19 Sanken Electric Co Ltd Insulated gate bipolar transistor
JP2010147239A (en) * 2008-12-18 2010-07-01 Toshiba Corp Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
JP2818959B2 (en) 1998-10-30

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