JP3185445B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a region for shortening the recombination lifetime of carriers in a semiconductor device for speeding up switching.

[0002]

2. Description of the Related Art In order to switch semiconductor devices such as PN junction type diodes, transistors and thyristors at high speed, it is important how stored carriers generated at the time of turn-off are eliminated quickly. As a method therefor, several methods for shortening the recombination lifetime (hereinafter, referred to as lifetime) of carriers have been performed.

[0003] One is a method of shortening the lifetime by diffusing impurities that form a deep recombination level where carriers easily recombine. Metals such as Au and Pt are used as impurities. This method is generally performed by depositing a metal impurity on the back surface of a semiconductor substrate and heating the metal impurity to diffuse the inside of the substrate. In this method, although the diffusion coefficient of the impurity is very large, it is diffused throughout the semiconductor substrate.
Conversely, it is difficult to selectively diffuse only a certain area of the substrate.

Another method is to form a lattice defect in a semiconductor crystal by irradiating the entire surface of a semiconductor substrate with a high-energy charged particle beam, and to shorten the carrier lifetime by a deep recombination level caused by the lattice defect. Is the way.

[0005] The speeding up of a semiconductor device by these methods is described in, for example, Mitsubishi Electric Technical Report Vol. 41, No. 11, 1967 and the like. This is a commonly used method. In particular, thyristors, diodes, GTO, I
In a GBT, an electrostatic induction thyristor, and the like, the speed is increased by these methods (hereinafter, referred to as a lifetime control method).

Here, a description will be given of lattice defects. Lattice defects generated in a semiconductor crystal by a charged particle beam actually cause various kinds of defect levels.
Among them, Si formed by irradiation at room temperature and acting as a recombination level at the operating temperature of a semiconductor device is Si
In the case of, there is a level called an A center and a defect level called an E center. All of these defect levels are obtained by electron spin resonance (ESR) or deep level transient spectroscopy (DL).
As previously confirmed by TS), the A center is created by a pair of vacancies and oxygen atoms, and its energy level is about 0.17 eV from the conduction band. The E center is generated by a pair of a vacancy and a group V atom, and the energy level is about 0.4 eV from the conduction band.

The recombination center that shortens the carrier lifetime is more effective if it is located as close as possible to the center of the energy gap (1.1 eV), and the E center at Ec-0.4 eV is particularly effective. The effect of shortening the carrier lifetime at the time of turn-off at a low injection level is great. Therefore,
For speeding up, it is better to form many effective E centers.

Recently, a power IC in which a plurality of power elements and a control circuit thereof are mounted on a single semiconductor substrate has been manufactured in place of the conventional discrete power semiconductor element as described above. In order to quickly switch the power elements mounted on the device, the above-described high-speed technique may be effective.

However, in order to increase the speed of the power element of the power IC, it is necessary to shorten the carrier life only in the power element without affecting the control circuit on the same substrate. When the power element itself is of a type in which all the electrodes are taken out from the substrate surface, the current path is in the horizontal direction, and the speed can be increased by shortening the carrier life only in a specific part.

As a method of increasing the turn-off speed by a method other than the lifetime control, there is a method in which the anode of the power element is short-circuited to suppress the injection of minority carriers from the anode. Shorter turn-off time than control cannot be achieved (ISPSD '9
2, Proceedings P328).

However, in the above method, in any case, the region where the carrier life is shortened is the entire semiconductor substrate. With respect to the depth direction of the substrate, a certain degree of depth direction distribution can be provided by irradiating a charged particle beam such as a proton beam or an α-ray with an appropriate energy. In addition, it is impossible to selectively form a region for shortening the carrier life. In principle, if irradiation is performed with a mask made of an appropriate material having a thickness capable of blocking the above-mentioned proton beam and α-ray, it is possible to selectively form a region having a shortened carrier life even in a planar manner. However, in reality, a thick mask using a heavy metal or the like is required to block the proton beam or the α-ray, and it is impossible to finely process the mask. That is, the above-described conventional technology cannot be applied to a semiconductor substrate on which a power element such as a power IC and a control circuit for the same are mixed, when it is necessary to selectively shorten the carrier life of only the power element. was there.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to increase the speed by selectively forming a region in which the carrier lifetime is to be shortened as a three-dimensional region in a semiconductor substrate. An object of the present invention is to provide a method of manufacturing a semiconductor device that can be achieved.

[0013]

In order to solve the above-mentioned problems, a manufacturing method according to the present invention is directed to a method for manufacturing a semiconductor device in which a region for shortening the recombination lifetime of carriers is formed. The density is increased beforehand, and then the entire surface of the semiconductor device is irradiated with a charged particle beam to selectively increase the density of a specific defect level in the region, thereby changing the region to a region for shortening the recombination lifetime. It is characterized by having a process.

[0014]

According to the method of manufacturing a semiconductor device of the present invention, a specific impurity atom, for example, a group V P atom, whose concentration is relatively increased in a region of a semiconductor substrate in which the carrier lifetime is to be shortened, is added to the entire semiconductor substrate. Lattice defects formed by the irradiated charged particle beam form a pair and generate a high density of defect levels (E center) effective in shortening the carrier lifetime at the operating temperature of the semiconductor device in that region.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the manufacturing method of the present invention, first, a group V atom, for example, a P (phosphorus) atom is introduced into a region where lifetime control is to be selectively performed, and the concentration of the P atom is relatively increased from the periphery. And then irradiating the whole surface with a charged particle beam to form a lattice defect, and the defect level (E center) generated by the pair of the lattice defect and the P atom is relatively set in the region. It is characterized by being generated at a high density.

FIG. 1 schematically shows a process for forming a lifetime control region in a selective region according to the present invention. First, as shown in FIG. 1A, for example, P ions are implanted into a desired selected region 3 of a semiconductor substrate 1 on which a resist mask 2 has been formed by a high energy ion implantation method. afterwards,
As shown in FIG. 1B, by irradiating the entire surface of the semiconductor substrate 1 with a high energy charged particle beam such as protons to the depth of the region 4, lattice defects are formed on the entire surface of the semiconductor substrate. The defect level of the E center is formed in the introduced selected region 3 at a relatively higher density than its surroundings.

A different embodiment will be described with reference to FIG. The figure shows an example in which a lifetime control region is formed on the anode of a horizontal insulated gate bipolar transistor (hereinafter, referred to as a horizontal IGBT) by the manufacturing method of the present invention for speeding up. The IGBT is a MOS device gate type device using the conduction modulation effect.
High current density, high withstand voltage, suitable for large current applications,
The turn-off time is longer than that of the MOSFET, and is a power element requiring lifetime control. In a power IC, a horizontal IGBT may be used to form a plurality of IGBTs on the same semiconductor substrate. The process of the present invention for increasing the speed will be described in order.

FIG. 2A is a sectional view showing a lateral IGBT element separated on a semiconductor substrate by a dielectric 5. First, a P ⁺ gate region 7 is formed in an N ⁻ region 6 by an ordinary impurity diffusion or the like. An N ⁺ source region 8 and a P ⁺ drain region 9 (anode) are formed.

Next, as shown in FIG. 2B, P ⁺ ions are implanted into the side walls of the P ⁺ drain region 9 (anode) by high-energy ion implantation using a thick-film resist mask 10 to remove P atoms. The high concentration region 11 is formed.

Next, as shown in FIG. 2C, a high-concentration region 13 of P atoms is formed at the junction below the P ⁺ drain region 9 (anode) by using a thick film resist mask 12.

Then, as shown in FIG. 2D, after the gate electrode 14, the source electrode 15, the drain electrode 16, and the Si oxide film 17 are formed, a proton (proton beam) or helium (α) is formed.
Irradiating high-energy light ions such as
Defect levels are formed at high density only in the high concentration regions 11 and 13 of P atoms.

At this time, in the high-concentration regions 11 and 13 of P atoms, since a defect level which causes an E center is easily formed, a lattice defect is conventionally formed by irradiating only the N ⁻ layer. The dose of light ion irradiation may be smaller than in the case. Therefore, the portion other than the region where the P atoms are implanted is
Generation of lattice defects due to light ion irradiation is very small.

According to the above-described method, even a semiconductor substrate on which a power element such as a power IC and its control circuit coexist can be used.
Since a region where the defect level of the E center caused by the atom is relatively high can be selectively formed, there is a great effect in shortening the turn-off time.

In the embodiment, the ion implantation method is used for doping P ions, but another doping method may be used. Further, electron beam or γ-ray irradiation may be used instead of light ion irradiation.

In the embodiment, an example of a horizontal IGBT is taken, but the manufacturing method of the present invention can be widely applied to a semiconductor device for controlling a lifetime.

[0026]

According to the present invention, it is possible to control the lifetime of a selected area by the above-described method, which is impossible with the prior art. As a result, in the conventional irradiation of charged particle beams over the entire surface of the semiconductor substrate, a semiconductor device in which a power element such as a power IC and its control circuit are mixed,
Although it has been difficult to increase the speed of the power element by lifetime control without affecting the control circuit, the present invention can increase the speed of the power element without substantially affecting the control circuit.

Conventionally, horizontal IGB mounted on a power IC
At T, the method of increasing the speed was only the method using the anode short structure, and the turn-off fall time could only be increased up to about several hundred ns. If lifetime control is performed in the vicinity, the turn-off fall time can be shortened to several tens of ns, and the period of the switching transient state is shortened, so that the loss due to switching can be greatly reduced. Further, since the loss is reduced, the heat generation of the power IC as a whole is reduced as compared with the related art, so that the current capacity of the power IC can be increased, and the device can be highly integrated and downsized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor substrate for illustrating a basic flow of a manufacturing method according to the present invention.

FIG. 2 is a cross-sectional view of a lateral IGBT whose speed has been increased by the manufacturing method according to the present invention.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 resist mask 3 selection region 4 region 5 dielectric 6 N ⁻ region 7 P ⁺ gate region 8 N ⁺ source region 9 P ⁺ drain region (anode) 10 thick film resist mask 11 high concentration region 12 thick film resist mask 13 High concentration region 14 Gate electrode 15 Source electrode 16 Drain electrode 17 Si oxide film

Claims (1)

(57) [Claims] In a method of manufacturing a semiconductor device in which a region for shortening the recombination lifetime of carriers is formed, a specific impurity atom concentration is relatively increased in the region in advance.
Next, a step of irradiating the entire surface of the semiconductor device with a charged particle beam, selectively increasing the density of specific defect states in the region, and changing the region to a region having a reduced recombination lifetime is provided. A method for manufacturing a semiconductor device.