JPH03271852A - Data preset system - Google Patents

Abstract

PURPOSE:To reduce the processor load and to shorten the processing time by reading out a data storage memory with a pointer value simultaneously with setting of the pointer value to a pointer register by the first memory access and setting this read data to a parameter register. CONSTITUTION:An address ADH and ADL of a pointer register 24 is sent to a bus and is designated to the register by the first memory access. A pointer value DTH and DTL to be set to the register is sent to the bus and is set to the register (gamma1 to gamma4). A local memory 21 is read out with this set pointer value (new pointer) as the address (gamma6), and this read data RD is set to a parame ter register 23. Thus, unnecessary register access is eliminated to not only reduce the processor load but also shorten the processing time.

Description

[Detailed Description of the Invention] [Summary of the Invention] The present invention relates to a method of setting data to a register for storing data at the time of data access from a processor on a channel internal memory, which eliminates the need for extra register access and reduces processor load. A time-sharing register access interface that transfers addresses and data by occupying the bus in the order of the first address and then the next data, with the aim of reducing processing time and processing time.
It has a data storage memory, a pointer register which is set with a pointer value and has a function of incrementing the pointer value and which generates the memory access address, and a parameter register which temporarily stores the read/write data of the memory. In the data advance setting method, the memory is read immediately after the data transfer, the read data is set in the parameter register, and the read data in the register is sent to the parameter register in the next data transfer period. At the same time as the pointer value is set, the data storage memory is read using the pointer value and the read data is set in the parameter register.

[Industrial application field]

The present invention relates to a method for setting data in a data storage register during data access from a processor on a channel internal memory.

In recent years, as the performance of computer systems has improved, there has been an increasing demand for load distribution among processors. For this reason, efforts have been made to make the channel intelligent by providing a sub-processor on the channel side as well. At this time,
It is necessary to exchange control information between the main processor and the sub-processors, and as a means for doing so, in many cases a local memory is provided within the channel, and communication between the main and sub-processors is performed via this memory.

[Conventional technology]

Since local memory is provided in each channel, if all local memory is placed in an address space that can be directly designated by the processor, the problem of address space reduction will occur.

For this reason, in the conventional technology, as shown in FIG. 4, a temporary data storage register (parameter register) 23 and a pointer register 24 for holding in-memory addresses are provided, and memory access is performed using these, thereby reducing the address space of the main memory. is prevented. In FIG. 4, 10 is a main processor, 20 is a channel, and there are generally a plurality of channels. 21 is a local memory provided for each channel, 22 is a sub-processor, and 25 is an interface/memory control unit.

Communication between the main and sub processors is performed by the main processor writing information (communication content) to the local memory, the local memory reading it, and vice versa, but writing to the local memo IJ21 is as follows: The information to be written by the processor is written to the parameter register 23, the address is written to the pointer register 24, and the local memory 21 writes to itself using the information and address of these registers: A923.24. Ru. Since the pointer register 24 has an incrementing function, subsequent writing can be done by simply writing the relevant information to the parameter register 23.

Upon receiving notification that writing has been performed, or at an appropriate period, the other processor reads the local memory 21. This can be done by setting the local memory in continuous readout mode and setting a pointer value in the pointer register if necessary, and subsequent addresses are generated while the pointer register 24 is incremented.

The parameter and pointer registers are accessible by both the main and sub processors, and their addresses are within the address spaces of these processors. The local memory address space is separate from this, thus preventing the reduction of the main memory address space. Using local memory has the great advantage of avoiding main memory bus congestion compared to storing this portion in main memory. The capacity of local memory is generally several high dollars.
It is a kilobyte. There is also a method in which information (data)/address transfer on the bus is performed in a time-division manner.

If an interface that transfers the upper address, lower address, upper data, and lower data in this order is used as the access interface for the registers 23 and 24, the result shown in FIG.
It will look like Figure 6. That is, as shown in FIG. 5, the register access interface RAI
Upper address A, D H1 lower address ADL,
Since the upper data DTH and the lower data DTL to be set to the register 23 are transferred in this order, in the case of a read access, the register 23 is selected by ADH and ADL, and the contents DTH and DTL are sent out at the next time. , ADH, ADL are sent to the register 23 at time T1.
The contents (data) must be fixed. To do this, it is necessary to read the local memory and set the read data in the register 23 before TI, and therefore a method called advance setting is used.

FIG. 6 is a diagram explaining this, and shows τ, to τ4. τ5～τ6
．． . . . is each access cycle. When this cycle starts, in this example, the pointer register 24 is set to count enable WE at τ, and the pointer register 24 is incremented to n+1 after τ6.

Output enable OE is set, and chip select C3 is set at τ6 to output the data at address n+l of the local memory to the memory bus, and this is loaded into the parameter register 23 at τ7. τ is of DTH, also τ
.

Since this is the DTL sending period, data can be transferred to the system bus without any problem.

[Problem to be solved by the invention]

As mentioned above, in the time-division transfer method of parameter register addresses and data, a method is adopted in which the next data is set in advance from local memory to the parameter register during the next address transfer immediately after the previous parameter register access. However, at the time of the first access to the parameter register (when rewriting the pointer register), the preceding set from memory has not been performed, so what was in the register at that time was not the desired one, and it was not read. The data obtained is meaningless.

Conventionally, to prevent this, the first read data was discarded, the pointer that had advanced one step was returned to the initial state, and the parameter register was then read again to obtain the correct data. are doing.

Therefore, when reading memory, four register access operations are required: ∎ pointer set, ∎ read the parameter register and discard the read data, ∎ reset the pointer (return one), and ∎ re-read the parameter register. There were problems such as increased load and increased processing time. Since the operation of setting a pointer value in a pointer register and reading local memory data from it occurs frequently during program execution, the increase in processing time due to the above-mentioned items 1 to 2 cannot be ignored.

The present invention has been made to solve the above problems, and aims to eliminate unnecessary register access, reduce processor load, and shorten processing time.

[Means to solve the problem]

As shown in FIG. 1, in the present invention, in the first memory access, the addresses ADH and ADL of the pointer register 24 are sent to the bus to specify the register, and then the pointer values DTH and DTL to be set in the register are sent to the bus. and sets the value in the register 24 (τ, ~τ4),
The local memory 24 is read using this set pointer value (new pointer) as an address (τ6), and the read data RD is set in the parameter register 24.

(Operation) With this method, desired data can be read from the local memory from the beginning. That is, the address of the pointer register is sent (τ3.τt) to specify the register, and then the pointer value is sent (τ8.τt). τ4) Set this to the register and access the local memory with this τ,)
, while the read data RD is obtained on the memory bus (τ6) and set in the parameter register 23 (τ7), the addresses ADH and ADL of the parameter register 23 are sent (
τ2. τ, ), the contents of the register 23 are sent (τ7
．． τ8) is the desired data from the beginning because the local memory data at the desired address is set in the parameter register 23 at this time τ.

From the second time onward, the process is the same as the conventional method, and the pointer register 24 is incremented during reading, the local memory 21 is read with the incremented pointer value, the read data is set in the parameter register 23, and the set read data is transferred to the bus. The same operation is repeated the specified number of times.

[Example of warehouse] Figure 1 corresponds to Figure 6, and like all the figures, the same parts are given the same reference numerals. Therefore R.A.
I is a register access interface, C3 is a chip select, and OE is an output enable.

FIG. 2 shows a memory system to which the data advance setting method of the present invention is applied, and the configuration is the same as that of FIG. 4.

FIG. 3 is a detailed view of FIG. 2. The interface/memory control section 25 includes an interface control section 25a, a register access control section 25b1, and a memory interface control section 25c. 26 is a write multiplexer, 27 is a read multiplexer, and 31 to 35 are buffers.

To explain the operation of this diagram with reference to FIG. 1, first, a pointer value (the first address of the local memory to be accessed) is sent from the main processor 10 to the pointer register 24 via the register access interface RAI.
(τ3, τ4) and write this to the register (
τ,). When the pointer value is set in the register 24, the register access control unit 25b issues an instruction to the memory interface control unit 25C to read memory data, switches the write multiplexer 26 of the parameter register 23 to the buffer 34 side, and writes the memory. 2
The read data of 1 is set in the register 23.

In the next cycle (τ6), the memory 21 receives the chip select signal C3 output by the memory interface control unit 25c.
and the output enable signal OE (this means that the memory has received a read instruction), and outputs the data at the address indicated by the pointer register 24. The data output from the memory 21 enters the parameter register 23 through a path 34-26-23, and is set into the register 23 by the set clock output from the register access control section 25b.

The main processor 10 goes to read the parameter register 23 (τ9.τk), and the memory control unit reads the ink face control unit 2 according to instructions from the main processor 10.
5a to control the read multiplexer 27,
Outputs the contents of the parameter register 23 onto the register access interface R/1. In this way, the memory data at the address indicated by the pointer register can be read from the beginning.

In Figure 1, etc., time-division transfer is performed in the order of upper ADH, lower ADL of address, upper DTH of data, and lower DTLO, but this is reversed in the order of lower ADL of address, upper ADH, lower DTL of data, and upper DTH. It may be divided and transferred, and other appropriate changes are possible.

〔Effect of the invention〕

As explained above, conventionally, when reading memory data, four register access operations are required: ■ Pointer set, ■ Parameter register read and data discarded, Pointer reset, and Parameter register re-read. However, with the present invention, this can now be done with two operations: (1) setting the pointer, and (2) reading the parameter register. As a result, it becomes possible to reduce the load on the processor and shorten the processing time, which greatly contributes to improving the performance of the computer system.

[Brief explanation of drawings]

FIG. 1 is a time chart explaining the data advance setting method of the present invention, FIG. 2 is a block diagram of a memory system implementing the present invention, FIG. 3 is a block diagram showing a specific example of FIG. 2, and FIG. 5 is a block diagram showing a conventional example, FIG. 5 is an explanatory diagram of time-division transfer of addresses and data, and FIG. 6 is an explanatory diagram of a data advance setting method. In Figure 1, ADH and ADL are addresses and DTH. DTLH data, RD is read data, and 2 in Figure 2
1 is a data storage memory, 23 is a parameter register,
24 is a pointer register. Register access BN2 diagram of a memory system implementing the present invention Block diagram showing a conventional example FIG.

Claims (1)

[Claims] 1. A time-sharing register access interface that transfers addresses and data by occupying a bus in the order of the first address and then the next data; a data storage memory (21); and a pointer value set; a pointer register (24) that generates the memory access address and has a function of incrementing the pointer value, and a pointer register (24) that generates the memory access address;
Parameter register (23) that temporarily stores write data
), the memory is read out immediately after the previous data transfer, the read data is set in the parameter register, and in the next data transfer period, the read data in the register is sent to the bus. In accessing, a data advance setting method is characterized in that, at the same time as setting a pointer value in a pointer register, a data storage memory is read using the pointer value and the read data is set in a parameter register.