JPH03269765A - Logic simulation processing system for register - Google Patents

Abstract

PURPOSE:To automatically verify the timings of the clock input and the data input of a register by constituting a virtual circuit, which consists of a circuit which discriminates the setup time and the hold time of the register, on a simulation device together with the register. CONSTITUTION:A setup time monitor circuit 2 starts the counting operation of a setup time count part 4 by the change of a data input signal to a register 1, and the output of the count part for the change of a clock input signal to the register 1 is obtained, and it is checked whether this output has a prescribed value or not. A hold time monitor circuit 3 starts the counting operation of a hold time count part 5 by the change of the clock input signal to the register 1, and the output of the count part 5 for the change opposite to the change of the data input signal to the register 1 is obtained, and it is checked whether this output has a prescribed value or not. Thus, the timings of the clock input and the data input are automatically verified in consideration of only actually operated paths.

Description

[Detailed Description of the Invention] [Summary] Regarding the logic simulation processing method for registers, the purpose of this is to automatically verify the timing of the register's clock manual and data manual. The count operation of the set-up time counter is started by a change in the data input signal to the register, the output of the counter is determined when the clock input signal to the register changes, and this output is a predetermined value. A set-up time monitoring circuit that checks whether the clock input signal to the register concerned starts counting operation of the hold time counting section due to the change in the clock input signal to the register, and a change opposite to the change in the data input signal to the register concerned. Build a virtual circuit consisting of a hold time monitoring circuit that obtains the output of the relevant counting section when the above occurs and checks whether this output is at a predetermined value. The present invention has a configuration in which the verification is performed using the output and the output of the hold time monitoring circuit.

[Industrial application field]

The present invention relates to a logic simulation processing method, and more particularly to a logic simulation processing method that automatically determines the timing of clock input and data input of each register connected via a combinational circuit.

[Conventional technology]

In general, the registers that make up the synchronous circuit are shown in Figure 4 (a).
), a combinational circuit 42 consisting of a large number of gate circuits is connected between the register 41 at the previous stage and the register 43 at the next stage.
It is equipped with The input data to the registers 41 and 43 must be stable for a predetermined period of time before and after changes in the clock input.

In other words, for example, when data is input using the rising pulse of the clock input, as shown in FIG. It is necessary that each hold time th, which is a stabilization time, has a predetermined time width.

In the conventional simulation processing method that determines the timing of the clock input and data input of each register, changes in the state values of the clock input and data input of each register are memorized, and after the simulation ends, all state values are We were checking to see if time relationships were maintained regarding changes.

Here, for example, 4 registers in the previous stage and 4 registers in the next stage.
One path in the combinational circuit 42 connecting 3 is composed of three gates, and the delay time at each gate is 2 ns.
~5ns, the register 43 at the next stage is stabilized in the state before the clock input change for 6ns after the clock input changes, stabilizes in the state after the clock input change after 15ns, and remains stable for 6ns to 15ns. Since it is not known which state is in between, the conventional processing method calculates the minimum and maximum delay times of all the paths in the combinational circuit 42, and calculates the above-mentioned time with respect to this delay time. The relationship was investigated after the simulation was completed.

[Problem to be solved by the invention]

As described above, in the conventional simulation processing method that determines the timing between the clock input of each register and the data input manually, changes in the state values of the clock input and data input of all registers are once memorized, and this is combined into a combinational circuit. To perform sequential processing to check whether the time relationships are maintained for all state value changes after the simulation ends, taking into account the delay time of all paths in the simulation (including paths that are not actually used). , the required storage capacity became enormous, making it difficult to handle large-scale circuits. Therefore, in the present invention, a virtual circuit consisting of a circuit that determines the set-up and hold times of registers is constructed on a simulation device together with the registers to be simulated, so that clock inputs and data inputs of registers can be connected. It is designed to perform automatic timing verification.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 1 is a register, and a combinational circuit consisting of a large number of gates is connected between it and the previous register.

2 is a set-up time monitoring circuit, which starts the counting operation of the set-up time counting section 4 when the data input signal to the register changes, and when the clock input signal to the register changes, the counting operation of the set-up time counting section 4 is started. It calculates the output and checks whether this output is a predetermined value.

3 is a hold time monitoring circuit, which starts the counting operation of the hold time counter 5 due to a change in the clock input signal to the register 1, and a change opposite to the above change in the data input signal to the register occurs. The output of the counting section 5 at the time of the change is determined, and it is checked whether this output is a predetermined value. Here, if the output of the set-up time counter 4 does not reach the predetermined value, it is verification that the set-up time is not observed, and if the output of the hold time counter 5 does not reach the predetermined value. If the hold time is not met, it is verification that the hold time is not respected.

[Effect]

In the present invention, a virtual circuit consisting of a monitoring circuit that obtains a count output corresponding to the set-up time and the hold time and checks whether this count output is a predetermined value is installed on the simulation device as a simulation target. By constructing it with a register, automatic timing verification of the clock input and data input in the register is performed.

〔Example〕

The present invention will be described in detail with reference to FIGS. 2 and 3.

FIG. 2 shows the setup time monitoring circuit and the data input manual holding section 21. Clock input human power holding unit 22
．． Count section 23. It is composed of an output evaluation section 24 and the like. The data input input holding unit 21 receives the data input signal and outputs its value after one unit time, that is, outputs the value of the data input signal before -unit time. Further, the input signal and output signal of the input holding section 21 are respectively input to the EOR circuit 25 of the counting section 23, and the EOR circuit 25 of the counting section 23
The OR circuit 25 outputs "1" when the data input signal changes from "0" to "1", that is, when the output signal of the input holding section 21 becomes "0" and the input signal becomes "1", This output causes the counter 26 to start counting, and the count output increases sequentially. When the count output reaches a predetermined value, for example "10", the output of the counter 26 is fixed to "0". Further, this count output is input to the output evaluation section 24.

On the other hand, the clock input input holding section 22 receives the clock input signal and outputs its value after one unit time, that is, outputs the value of the clock input signal before -unit time. Further, the input signal and output signal of the input holding section 22 are respectively input to the input change detection section 27 of the output evaluation section 24, and this input change detection section 27 detects the clock input from "0" to "
1, that is, when the output of the input holding unit 22 is 0 and the input becomes 1, it outputs 1. The output signal of the counter 26 and the output signal of the input change detection section 27 are respectively inputted to the evaluation circuit section 28, and the output signal of the counter 26 when the output of the input change detection section 27 changes to "1" is inputted to the evaluation circuit section 28.
The value of the output is checked, and when the value of the output is ``0'', it is evaluated that the set-up time has been observed, and when it is other than ``0'', it is evaluated that the set-up time has not been observed.

FIG. 3 shows the hold time monitoring circuit, which is different from the setup time monitoring circuit in FIG. ) is different in that the counting operation is stopped when the change occurs.

That is, the input holding unit 31 .of the clock input. Input holding unit 32 for data input. Count section 33. It is composed of an output evaluation section 34 and the like. The clock input human power holding section 31 receives the clock input signal and outputs its value after one unit time, that is, outputs the value of the clock input signal before -unit time.

Further, the input signal and output signal of the input holding section 31 are respectively input to the EOR circuit 35 of the counting section 33, and this FO
The R circuit 35 outputs rlJ when the clock input signal changes from "0" to "1", that is, when the output signal of the input holding section 31 becomes "0" and the human input signal becomes "1", and this output As a result, the counter 36 starts counting operation, and the count output increases sequentially. Then, when the count output reaches a predetermined value, for example "10", the output of the counter 36 is fixed to "0". Further, this count output is input to the output evaluation section 34.

On the other hand, the data input input holding unit 32 receives the data input signal and outputs the value after one unit time, that is, −
The value of the clock input signal before the unit time is output. Further, the input signal and output signal of the input holding section 32 are respectively input to the input change detection section 37 of the output evaluation section 34, and this input change detection section 37 detects that the data input changes from "■" to "0", that is, When the output of the input holding circuit 32 is "1" and the input is "0", rlJ is output. The output signal of the counter 36 and the output signal of the input change detection section 37 are respectively input to the evaluation circuit section 38, and the output signal of the input change detection section 37 is input to the evaluation circuit section 38.
Check the value of the output of the counter 36 when the output of the counter 7 changes to "1", and if the value of the output is "0", the hold time is observed, and if it is other than "0", the hold time is observed. The evaluation is that it is not.

〔Effect of the invention〕

The present invention has a configuration in which a virtual circuit consisting of a circuit unit that monitors whether the set-up time and hold time of the registers are observed is constructed on the simulation device together with the registers to be simulated. , it is possible to perform automatic timing verification of clock inputs and data inputs, considering only the buses that actually operate.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an explanatory diagram showing the setup time monitoring circuit of the invention, Fig. 3 is an explanatory diagram showing the hold time monitoring circuit, and Fig. 4 is an explanatory diagram showing the clock input of the register. FIG. 2 is an explanatory diagram showing a timing relationship of data input. In FIG. 1, 1...Register 2...Set-up time monitoring circuit 3...Hold time monitoring circuit 4...Set-up time counting section 5...Opening count section during hold

Claims (1)

[Claims] In a logic simulation processing method for each register connected via a combinational circuit, a setup time count section is provided on a simulation device together with a register to be simulated based on a change in a data input signal to the register. a setup time monitoring circuit that starts the counting operation of the register, determines the output of the counting section when the clock input signal to the register changes, and checks whether this output is a predetermined value, and a clock input signal to the register. The count operation of the hold time count unit is started by the change in the input signal, and the output of the count unit when a change opposite to the change in the data input signal to the register occurs is determined, and this output is determined as a predetermined value. A virtual circuit is constructed that includes a hold time monitoring circuit that checks whether the value is set, and the clock input and data input of the register are controlled by the output of the setup time monitoring circuit and the output of the hold time monitoring circuit of the virtual circuit. A register logic simulation processing method characterized by automatic timing determination.