JPH02184933A - Logical circuit simulation system - Google Patents

Abstract

PURPOSE:To make unnecessary the definition of all pieces of delay information and to easily prepare a delay defining file by attaining simulation and the detection of a glitch noise in the worst case. CONSTITUTION:An output register 5 supervises a response output 106 of an LSI 4, and when its output changes, the register 5 outputs time information after the activation of the simulation and a changed output 107. After access 108 is inputted, a delay defining file 6 outputs delay information 109. When the LSI 4 executes an operation which is not defined in the delay defining file 6, a value included in a changed output 102 is used instead of the delay information 109. An input state value storage memory 7 controls the input state value of each input pin of the LSI 4, inputs memory access 110, and outputs an input history 111 of the input pin concerned. Thus, the delay information defining file can be easily prepared.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a simulation apparatus for digital logic circuits, and particularly to a simulation method for logic circuits including existing high-density integrated circuits.

[Conventional technology]

As logic simulations have become more common due to recent advances in semiconductor technology and computer technology, there has been an increasing demand for large-scale circuit simulations, especially circuit simulations that include LSIs.

Conventionally, when performing logic simulation, a device model written in software is required. However, it is difficult to describe a model of a large-scale LSI such as a microprocessor in software, and it is almost impossible when considering the number of steps required for development. Even if developed, it is difficult to evaluate and simulation requires a large amount of time. One way to solve this problem is to use an actual digital element as a device model.

For example, there is a logic circuit simulation method as disclosed in Japanese Patent Publication No. 61-36262. In this logic circuit simulation method, an existing digital circuit is implemented, the other circuit simulations are created using a general-purpose computer, etc., and the state of the output node of the circuit simulation created by the general-purpose computer is transferred to the input terminal of the digital circuit. and buffering the output signal appearing at the output terminal thereof, and using the buffered output signal as a stimulus to the input node of the circuit simulation. The delay information at that time is extracted from the actual digital circuit.

Another conventional technique is a method in which delay information is extracted from a delay definition file registered in advance in a general-purpose computer.

[Problem to be solved by the invention] Since the conventional logic circuit simulation method described above extracts delay information from the actual digital circuit, it is not possible to simulate the worst case, that is, variations in circuit delay may be reflected in the simulation results. It has the disadvantage of having an impact.

Furthermore, the method of extracting delay information from a delay definition file registered in advance in a general-purpose computer does not capture actual output change points of a digital circuit, and therefore cannot detect noise such as glitches. Therefore, all the delay information of the digital circuit must be defined, and there is a drawback that a great deal of effort is required to create a delay information definition file.

[Means to solve the problem]

In the logic circuit simulation method of the present invention, when simulating a logic circuit including a plurality of circuit elements, a part of the plurality of circuit elements is implemented with an existing LSI, and the other part is simulated by a general-purpose computer. In the method, means for storing a history of states of output nodes of circuit simulation calculated by the general-purpose computer, means for imparting the history of the output nodes to the LSI, and means for monitoring the output terminals of the LSI and controlling the output terminals. means for extracting delay information from when the history is added until the change occurs when a change occurs; and a means for extracting delay information from the delay information and a delay definition file for the LSI prepared in advance on the general-purpose computer. and means for applying the output signal of the output terminal to the input node of the circuit simulation after the delay time has elapsed, in units of circuit simulation time.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, the logic circuit simulation system includes a general-purpose computer 1, a control circuit 2, an input register 3, an LSI 4, an output register 5, a delay definition file 6, and an input state value storage memory 7.

The general-purpose computer 1 executes a circuit simulation excluding the LSI 4 using software, and outputs an LSI access 101 when a change occurs in the output node to the LSI 4. It also outputs memory access 108 and determines the operation of LSI 4 from delay information 109 and change output 102 of LSI 4.

The control circuit 2 inputs the LSI access 101, identifies the bin number and input state value, outputs the memory access 110, inputs the input history 111 from the input state value storage memory 7, and controls the control 103 and access control 104. Output.

The input register 3 inputs a control 103 and an access control 104 and outputs a drive output 105.

LSI4 is control 103. A drive output 105 is input, and a response output 106 is output.

Output register 5 inputs control 103 and outputs LSI
4 is monitored, and when a change occurs in the output, the change output is latched, and a change output 107 is output together with time information since the simulation started.

The delay definition file 6 manages delay information of individual elements,
When access 108 is input, delay information 109 is output. When the LSI 4 performs an operation that is not defined in the delay definition file, the change output 102 is sent instead of the delay information 109.
The value contained in is used.

The input state value storage memory 7 manages the input state values of each input bin of the LSI 4, inputs a memory access 110, and outputs the input history 111 of the corresponding input bin.

〔Effect of the invention〕

In the logic circuit simulation method of the present invention, when simulating a logic circuit including a plurality of circuit elements, a part of the plurality of circuit elements is implemented with an existing LSI, and the other part is simulated by a general-purpose computer. In the method, means for storing a history of states of output nodes of circuit simulation calculated by the general-purpose computer, means for imparting the history of the output nodes to the LSI, and means for monitoring the output terminals of the LSI and controlling the output terminals. means for extracting delay information from when the history is added until the change occurs when a change occurs; and a means for extracting delay information from the delay information and a delay definition file for the LSI prepared in advance on the general-purpose computer. and a means for stimulating the input node of the circuit simulation after the delay time has elapsed by applying the output signal of the output terminal in time units of the circuit simulation. This has the advantage that it is possible to detect noise, there is no need to define all delay information, and it is easy to create a delay definition file.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a logic circuit simulation method showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... General-purpose computer, 2... Control circuit, 3... Input register, 4... LSI, 5... Output register, 6
...Delay definition file, 7...Input state value storage memory.

Claims (1)

[Claims] When simulating a logic circuit including a plurality of circuit elements, a portion of the plurality of circuit elements is an existing LSI.
In a logic circuit simulation method in which the circuit is implemented and other parts are simulated by a general-purpose computer, means for storing a history of a state of an output node of a circuit simulation calculated by the general-purpose computer, and providing the history of the output node to the LSI. means for monitoring an output terminal of the LSI and, when a change occurs in the output terminal, extracting delay information from when the history is added until the change occurs; a means for determining a delay time from a delay definition file for the LSI prepared in advance; and a means for determining a delay time from a delay definition file of the LSI prepared in advance, and stimulating an input node of the circuit simulation after the delay time has elapsed by inputting the output signal of the output terminal in a circuit simulation time unit. 1. A logic circuit simulation method comprising means for: