JPH03269661A - Bus right request system - Google Patents

Abstract

PURPOSE:To shorten the waiting time for answer with a simple circuit constitution by processing an answer transfer request in preference to a command request by means of a bus interface and a bus arbiter. CONSTITUTION:A buffer 72 stores the information showing whether a transfer request signal is equal to a command or answer transfer request signal. The output of the buffer 72 is directly inputted to an AND gate 74 and also to an AND gate 73 after inversion. The result of comparison showing whether the data on a comparator 41 to be transferred remains or not is inputted to both gates 73 and 74. If the data remains, a signal is outputted to a transmission control part 28 in response to the queue additional information. The part 28 transmits an answer transfer request signal RQH or a command request signal RQL to a bus arbiter 71 in accordance with a fact whether the queue additional information is identical with an answer or command request signal. The arbitra tion circuits 75 and 76 transmit the signals on the highest priority among those requests to an AND gate 77 and a NOR gate 78. Then a transfer grant signal GR is outputted to the answer transfer request in preference to the command request.

Description

[Detailed Description of the Invention] [Summary] Regarding a bus request method in a multiprocessor system, the purpose of the present invention is to realize a bus request method that can shorten answer waiting time with a simple circuit configuration. In a multiprocessor system in which a CPU board and a memory board are connected to a common system bus, a bus interface connects a local bus within each board to the system bus, and a system bus usage right for each board is provided. A bus arbiter that performs arbitration, a command transfer request signal line that conveys a command transfer request from the CPU board to the bus arbiter, an answer transfer request signal line that conveys an answer transfer request, and an answer transfer that conveys an answer transfer request from the memory board to the bus arbiter. The bus interface enables the command transfer request signal line or the answer request signal line depending on whether the transfer request is a command transfer request or an answer transfer request, and the bus arbiter enables the command transfer request signal line or the answer request signal line depending on whether the transfer request is a command transfer request or an answer transfer request. When the transfer request arrives, it is determined whether the transfer request is a command transfer request or an answer transfer request, depending on which signal line the transfer request is from, and permission to use the system bus is given to the answer transfer request with priority. Configure.

[Industrial application field]

The present invention relates to a bus request method in a multiprocessor system.

[Conventional technology]

FIG. 5 is a system configuration diagram of a multiprocessor system in which a plurality of CPU boards and memory boards are connected to a common system bus 11.

On the system bus 11, there are multiple CPU boards CPU
o~CP UN and memory board CMO~CM.

A bus arbiter (BA) 12 is connected to the bus arbiter (BA) 12, and the bus arbiter 12 arbitrates the right to use the bus of each board.

Further, FIGS. 6A and 6B are diagrams showing the configurations of a CPU board (CPUi) and a memory board (CM amount), respectively. The CPU board is a microprocessor (μP)
15, a control register (CTLREG) 16, and a bus interface (BIF) 14.
The memory board includes RAM 18 and RAM controller 17.
, and a bus interface 14. The bus interface 14 connects the local bus 13 within the board and the system bus 11.

As a system bus data transfer format in a multiprocessor system, there is a transfer format called a time sprint format in which a command transfer cycle and an answer transfer cycle are separated.

FIG. 7 is a diagram showing an example of signal timing in the time sprint format.

The bus interface 14 of each board receives bus request signals PQi and PQ before transferring a command or an answer.
, is sent. Then, the bus arbiter 12 determines which one has the highest priority and sends a transfer permission signal GR1 to the corresponding board.
, GR, is sent.

In response to this, each board sends a command C1 or an answer AN onto the system bus 11.

Next, FIG. 8 is a circuit diagram of the bus interface 14 provided in each board.

Inside the bus interface 14, there is a first-in-first-out format transmission FIFO that stores transmission data.
21, and a receiving FIF 22 for storing received data. Furthermore, buffers 23.25 and 24.26 are provided between these FIFs 21.22 and the local bus 13 and system bus 11.

The transmission data is stored in the buffer 23 for a time and then stored in the transmission FIFO 21. The transmission data read out from the FIFO 21 in the order of arrival is temporarily stored in the buffer 24 and sent to the system bus 11.

On the other hand, the received data is stored in the buffer 26 and then in the reception FIFO 22. And receiving FIF
The received data read from O22 in the order of arrival is temporarily stored in the buffer 25 and then sent to the local bus 13.

The reception control section 27.30 and the transmission control section 28.29 are
This circuit controls writing and reading of each of these buffers 23 to 26 when transmitting and receiving data. Further, the transmission FIFO control unit 31 and the reception FIFO control unit 32 are circuits that instruct the write address and read address of the transmission FIFO 21 and the reception FIFO 22.

FIG. 9 is a specific circuit configuration diagram of the transmission FIFO control section 31 shown with diagonal lines in FIG. 8.

In the same figure, the input address section 33 is a transmission FIFO
This is a circuit for instructing the write address of 21, and the reception control unit 27 or the transmission control unit 29 via the OR gate 34.
According to the signal given from
Output to IFO21. Further, among the write addresses output from the input address section 33, the address of the delimiter of the transmission data string is stored in the queue buffer 35.

The output address section 36 is a circuit that instructs the read address of the transmission FIFO 21, and outputs an address sequentially incremented by "1" to the transmission FIF 021 according to the read signal from the transmission control section 28. The read address of the output address section 36 and the delimiter address of the transmission data string of the queue buffer 35 are determined by the comparator 3.
7, and the data in the transmission FIF 21 is read until the two addresses match.

The input completed display FF38 is the OR gate 39 during data transfer.
This flip-flop is set by a signal from the reception control section 27 or the transmission control section 29 of the local bus 13 via the local bus 13. Further, the output completion display FF 40 is a flip-flop that is set when data transfer is completed.

The comparator 42 compares these OFF outputs and determines whether a transfer request signal should be output.

For example, when the input completion display FF3B is set and the output completion display FF40 is reset, there is data remaining to be transferred, and the comparator 41 detects a mismatch between the outputs of the two.

1, the transmission control unit 28 outputs a command or answer transfer request signal PQ.

In the time split format, the system bus 11 is open to each board except during periods when commands or answers are being output. However, there are cases where the system bus 11 is exclusively used to transfer data between specific boards, and this is called lock transfer.

FIG. 10 is a diagram showing an example of the format of commands and answers. Command C is composed of data such as destination, source, command type, and data transfer amount. Further, the answer AN is composed of data such as a destination, a source, a command type, and an answer code.

FIG. 11 is a diagram illustrating the operation of the system during lock transfer. When the bus arbiter 12 receives a lock transfer signal, it recognizes the destination board from the destination data in the command C mentioned above, and is configured to accept only transfer requests from the destination board.

FIG. 12 is a circuit diagram of the main part of the bus arbiter, which is involved in the function of accepting and accepting only transfer requests from the destination board during lock transfer.

Destination data in the command is stored in a destination buffer 51, decoded by a decoder 52, and output to an OR gate group 54.

The command and lock transfer signal are sent to the C/AN determination circuit 56.
and the lock determination circuit 57, respectively. The outputs of these determination circuits are input to a set terminal or a reset terminal of an RS flip-flop (FF) 60 via an analog gate 158 or an inverter 59. This R
The 100 outputs of the 5FF 60 are input to each input terminal of the OR gate group 54. When the lock transfer signal is input and the Q output becomes low level, all the input terminals of one of the OR gate group 54 become low level, and only the other input terminal of the OR gate 54 corresponding to the destination stored in the destination buffer 51 becomes low level. Becomes a high level.

As a result, only the gate corresponding to the destination is opened in the AND gate group 61, and a transfer request signal from the destination is input to the arbitration circuit 62.

The arbitration circuit 62 is a circuit that issues a transfer permission signal GR corresponding to the output from the AND gate group 61. During lock transfer, only the transfer request signal from the destination is input to the arbitration circuit 62 by the circuit described above, so that the transfer permission signal can be output only to the destination board.

[Problem to be solved by the invention]

In the time-split data transfer method described above, the bus arbiter manages command and answer transfer request signals from each board connected to the system bus, and issues transfer permission signals sequentially starting with the board with the highest priority. I try to do that.

For example, when CPU board CPUz transfers a command and waits for an answer from memory board CMJ,
When a command transfer request is output from another CPU board CPU with higher priority, a transfer permission signal is issued to the CPU board CPUn, and the transfer of the answer from the memory board is delayed.

Generally, the local bus 13 within the CPU board is of an interlock type, and when an answer is received from the destination board, the frontage-culbus 13 is put on hold until it is received. Therefore, there is a problem in that other devices on the board cannot use the local bus 13 until the answer is returned.

In addition, in devices that perform lock transfer, the bus arbiter 12 identifies the destination board, and the circuit is configured so that it only accepts transfer requests from that destination board and does not accept transfer requests from other boards. Since it is necessary to configure the circuit, there is a problem that the circuit configuration becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to realize a bus request system that can shorten answer waiting time with a simple circuit configuration.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

In a multiprocessor system in which multiple CPU boards and memory boards are connected to a common system bus 11, the bus interface 1 connects the local bus 13 of each board to the system bus 11, and the bus arbiter 2 connects each Arbitrates bus usage rights between boards.

Between the CPU board and the bus arbiter 2 are command transfer request signal lines LCO to LCM that convey command transfer requests and answer transfer request signal lines LPO to L that convey answer transfer requests.
It is connected with PM. Further, the memory board and the bus arbiter 2 are connected by an answer request signal line Lso-LMN. For example, a low level signal is output as a command transfer request signal, and a high level signal is output as an answer transfer request signal from the bus interface 1 of each board via these signal lines.

[For production]

In the above configuration, the bus interface 1 enables the corresponding signal line depending on whether the transfer request is a command transfer request or an answer transfer request. When a transfer request signal arrives, the bus arbiter 2 determines whether the request is a command transfer request or an answer transfer request, depending on whether the signal is received from the command transfer request signal line or the answer transfer request signal line. identify and,
Transfer permission GR is given with priority to answer transfer requests.

Therefore, since the response is given priority, the CPU
The waiting time for board answers is shortened, and the processing efficiency of each board can be improved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing the connection state between the CPU board, memory board, and bus arbiter 71 in a multiprocessor system according to an embodiment of the present invention.

As shown in the figure, between the CPU board and the bus arbiter 71, there are command transfer request signal lines Lco to LCM that send a command transfer request signal RQcz, and an answer transfer request signal RQ□.
An answer transfer request signal line L-p that sends an answer transfer request signal line L-p.

- Connected with LPM. Also, memory board commercial
e to CM and the bus arbiter 71 are connected by an answer transfer request signal line L MW that sends an answer transfer request signal RQNi from the memory board.

Furthermore, the bus arbiter 71 and each board are connected by a signal line that sends a transfer permission signal GR.

In this embodiment, a high level signal is assigned to the answer transfer request signals RQP, RQold, and a low level signal is assigned to the command transfer request signal RQc1. It is determined whether the request is an answer transfer request or a command transfer request.

Next, FIG. 3 is a circuit configuration diagram of a bus interface within the CPU board and memory board.

The figure mainly shows circuits related to transmission, and circuit blocks that are the same as those of the conventional bus interface (FIGS. 8 and 9) are given the same reference numerals and their explanations will be omitted.

In FIG. 3, the queue additional information buffer 72 determines what the transfer request signal is, that is, whether it is a command transfer request or not.
Alternatively, it is a buffer that stores information indicating whether it is an answer transfer request.

The output of this cue additional information buffer 72 is directly input to an AND gate 74, and is inverted and input to an AND gate 73. These and gates 73.7
The comparison result of a comparator 41 that detects whether there is any data that has not been transferred is manually input to the other input terminal of 4, and when there is data left to be transferred, queue additional information is input. A signal corresponding to this is output to the transmission control section 28. For example, when the queue additional information is an answer transfer request, both inputs of the AND gate 74 are enabled and its output becomes high level. In response to this, the transmission control unit 28 outputs a high-level answer transfer request signal RQH to the answer transfer request signal line.

On the other hand, when the queue additional information is a command transfer request, both of the AND gates 73 are enabled and the output becomes high level. In response to this, the transmission control section 28
outputs a low-level command transfer request signal RQL to the command transfer request signal line.

Thereby, the bus arbiter 71 side can determine whether the transmitted transfer request signal is an answer transfer request or a command transfer request by checking whether the transmitted transfer request signal is at a high level or a low level.

This queue additional information buffer 72 also contains a transmitting F.
Since queue additional information indicating either a command transfer request or an answer transfer request is stored at each break in the data string stored in the IF○ 21, the content of the transfer request can be analyzed at short intervals.

Next, FIG. 4 shows the constituent countries of the bus arbiter 71 of the embodiment.

As shown in the figure, the bus arbiter 71 receives low-level command transfer requests RQL e to RQL of each boat color.
N (RQCO-RQCM) and high level answer transfer request RQ Ho~RQ HN (RQ P.~R
QPM and RQM (1 to RQMN) are input.

For command transfer requests RQL1 and answer transfer requests RQHt from each board, section stop circuits 75 and 76 are provided which determine which transfer requests are to be processed with priority. The arbitration circuits 75 and 76 store priorities corresponding to each board, and when answer transfer requests and command transfer requests are output from multiple boards at the same time, the output terminal corresponding to the board with a higher priority High-level signals are output in order from there.

Each output of the command arbitration circuit 75 is connected to the AND gate group 7
7, and each output of the answer arbitration circuit 76 is input to a multi-coupler gate 78 and an OR gate group 79.

Now, if multiple command transfer requests and multiple answer transfer requests are manually input to the bus arbiter 71 at the same time, the command arbitration circuit 75 and the answer arbitration circuit 76 will send requests to the board with the highest priority among the respective requests. A high level signal is output from the corresponding output terminal. At this time,
Since one of the inputs of the NOR gate 78 becomes a high level due to the output of the answer arbitration circuit 76, the output of the NOR gate on the 7th becomes a low level, and one of the input terminals of the AND gate group 77 all becomes a low level.

As a result, the command transfer request input to the AND gate group 77 is ignored, and the transfer permission signal GR1 is sent to the board with the highest priority among the boards that output the answer transfer request.
is output.

Furthermore, if there is another answer transfer request at this time, the output of the NOR gate 78 becomes low level in the same way, so that the transfer permission signal is output with priority over the answer transfer request.

In this way, by providing a command transfer request signal line and an answer transfer request signal line, and by distinguishing a command transfer request and an answer transfer request from each board and sending them to the bus arbiter 71, the bus arbiter 71 side can receive both request signals. can be identified.

Furthermore, since both signals can be distinguished, the answer transfer request can be processed with priority. Moreover, these functions can be realized with a simpler circuit configuration than conventional ones.

As a result, the answer is immediately returned to the CPU board that issued the command, so the time the CPU board is in the answer waiting state is shortened.

Therefore, the local bus within the board can be used more effectively to improve the processing efficiency of each board.

In addition, when conventionally performing lock transfer, in order to ignore transfer requests from other boards, the bus arbiter 71 recognizes which board is the destination of the lock transfer and only responds to answer requests from that board. Although it was necessary to provide a circuit for attaching the receiver, the present invention eliminates the need for these circuits. In other words, if the command transfer request is limited to the board that first sent the lock transfer command, then the answer transfer request will be processed with priority. It is possible to process answer transfer requests while securing the right to use the bus.

Note that the CPU board and memory board described in the above embodiments are not limited to board-like boards equipped with a microprocessor or memory, and may be divided into multiple devices.
The present invention can also be applied to systems that share a system bus.

〔Effect of the invention〕

According to the present invention, an answer transfer request can be processed with priority over a command transfer request using a bus interface and a bus arbiter with a simple configuration, so that the time that a CPU that outputs a command is in an answer waiting state can be shortened. , the processing efficiency of the system can be improved.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention; Fig. 2 is a diagram showing the connection state of the bus arbiter, CPU board, and memory board; Fig. 3 is a circuit diagram of the bus interface of the embodiment; Fig. 4 is a diagram showing the connection state of the bus arbiter, CPU board, and memory board; , the constituent countries of the bus arbiter in the example, FIG.
Figure 6 (a) shows the constituent countries of multiprocessor systems.
Figure 7 shows an example of time-split signal timing. Figure 8 shows the configuration of the conventional bus interface 14. Figure 9 shows the configuration country of the transmission FIFOvIW section 31 in Figure 8, Figure 10 shows the format of commands and answers, Figure 11 shows the operation during lock transfer, and Figure 12 shows the following:
FIG. 2 is a circuit configuration diagram of a main part of a conventional bus arbiter. 1... Bus interface, 2... Bus arbiter, 11... System bus, 13... Local bus.

Claims (1)

[Claims] 1) In a multiprocessor system in which a plurality of CPU boards (CPU_0 to CPU_M) and memory boards (CM_0 to CM_N) are connected to a common system bus (11), each of the boards (CPU_0 to CPU_M, CM_0~C
a bus interface (1) that connects a local bus (13) in M_N) and the system bus (11);
Each board (CPU_0 to CPU_M, CM_0 to C
A bus arbiter (2) that arbitrates the right to use the system bus (11) of M_N), and a command transfer request signal line (L_C_0 to L_C_M) that conveys a command transfer request from the CPU board (CPU_0 to CPU_M) to the bus arbiter (2). and the answer transfer request signal line (L_P_0~
LP_M) and answer transfer request signal lines (L_M_0 to L_M_N) that transmit an answer transfer request from the memory board (CM_0 to CM_N) to the bus arbiter (2), and the bus interface (1) has a Depending on whether it is a command transfer request or an answer transfer request, the command transfer request signal lines (L_C_0 to L_C_M) or the answer transfer request signal lines (L_P_0 to L_P_M, L_M_0
~L_M_N) and the bus arbiter (
2) When a transfer request arrives, it is identified whether it is a command transfer request or an answer transfer request depending on which signal line the transfer request comes from, and the system bus is given priority over the answer transfer request. Permission to use (GR_
P_0~GR_P_M, GR_M_0~GR_M_N)
A bus right request method characterized by granting. 2) Each of the above boards (CPU_0 to CPU_M, CM_0
2. The bus according to claim 1, wherein the command transfer request signal lines (L_C_0 to L_C_M) are not connected to the bus arbiter (2) for boards that do not perform command transfer among the buses (L_C_0 to L_C_M). Rights request method. 3) The bus interface (1) has queue additional information indicating whether the transfer request for the data string is a command transfer request or an answer transfer request for each break in the data string to be transferred, and the queue Based on the additional information, the command transfer request signal lines (L_C_0 to L_C_M) or the answer transfer request signal lines (L_P_0 to L_P_M, L_M_0 to L_M_
2. The bus right request method according to claim 1, wherein the bus request method is enabled. 4) The bus arbiter (2) processes answer transfer requests with priority even during lock transfer, and processes answer transfer requests from other boards than the board that is performing lock transfer. The bus right request method described in 1.