JPH05314063A - Multiple bus control system - Google Patents

Abstract

PURPOSE:To provide the multiple bus control system provided with functions for improving bus use efficiency and memory access throughput in a multiprocessor system equipped with plural buses. CONSTITUTION:A request queue is provided on the request input side in a memory element 2 and a response queue is provided on the response output side so as to execute a request cycle and a response cycle in different bus cycles at the time of access from a processor element 1 to the memory element 2. An arbiter 4 is provided with a load monitor means to monitor the load state of access for each memory element 2 and executes the arbitration and allocation of buses 3 based on the load conditions of respective banks at a storage device obtained from the load monitor means and use requests to the respective buses in the request cycle and the response cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiple bus control system in a multiprocessor system in which a plurality of processors and storage devices are interconnected by a plurality of buses.

[0002]

2. Description of the Related Art Conventionally, in many multiprocessor systems, a bus has been selected as a means for connecting a processor device and a main memory device to each other. This is because it is easy to realize, but on the other hand, when there are bus use requests from a plurality of processor devices at the same time, only one bus use request can be accepted at a time, so that the number of processor devices is large. In this case, there is a problem that the bus use requests frequently collide with each other and desired performance cannot be obtained.

As one solution to this problem, there has been conventionally adopted a system in which the number of buses is plural and a plurality of bus use requests can be accepted at the same time. In the shared memory type multiprocessor system, the bus usage request of the processor device is mainly due to the access request to the main storage device, and when multiple buses are used so that multiple bus usage requests can be accepted at the same time, In order to be able to receive a plurality of memory access requests at the same time, it is general that the main memory device is also made into a plurality of banks. In such a system, as a method of allocating each bus to a bus use request from a processor device, the bus is statically interleaved with an address together with a memory bank,
A method of allocating buses according to access destination addresses, and a method of FCFS (fire) without interleaving with addresses.
There is a method of dynamically allocating an empty bus by using an algorithm such as st come first service. Further, in such a system, the processor unit generally does not release the allocated bus until the response to the request is obtained.

[0004]

However, the above-mentioned conventional example has the following problems. When a bus use request from a plurality of processor devices, that is, a memory access request is for the same memory bank, the method of statically interleaving the bus by address is 1
Only the bus use request from one processor unit is accepted, and the same problem as in the single bus system occurs. Also,
In the method of dynamically allocating a vacant bus, the memory bank side can accept only one request at a time, and in this case, the processor device that issued the request and allocated the bus but has not accepted the request in the memory bank. Does not release the bus until a response is obtained, which affects the allocation of the bus to access requests to other memory banks. Then, in the worst case, all the buses wait for access to the same memory bank, and even the access to the accessible memory bank becomes inaccessible.

The present invention has been made in view of the above conventional problems, and an object of the present invention is to improve the use efficiency of a bus in a multiprocessor system having a plurality of buses and to achieve memory access through. -To provide a multiple bus control method having a function of improving the put.

[0006]

According to the multiple bus control method of the present invention for achieving the above object, in a multiprocessor system including a plurality of processor devices, multiple buses and multiple banked storage devices, the processor is provided. Memory access means for executing a request cycle and a response cycle required for access from the device to the storage device in separate bus cycles; and a load monitoring means for monitoring a load condition which is an access request amount for each bank of the storage device. ,
Bus allocation means for arbitrating and allocating buses based on the bus use requests in the request cycle and the response cycle and the load status of each bank of the storage device obtained from the load monitoring means.

[0007]

With the above structure, the priority of bus usage is determined based on the load status of each memory bank obtained by the load monitoring means and the bus usage request issued from each memory bank of each processor device and storage device. And the bus allocation is dynamically executed in independent request and response cycles.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a multiprocessor system according to the present embodiment. Reference numeral 1 is a processor element, which is n processing units included in the multiprocessor system. Reference numeral 2 denotes a memory element, which is an m-bank storage device provided in the multiprocessor system. Reference numeral 3 denotes k buses, and the n processor elements 1 and the m memory elements 2 are provided.
Are connected. An arbiter 4 arbitrates and allocates the bus 3 in response to bus use requests from the processor element 1 and the memory element 2.

FIG. 2 is an internal block diagram of a processor element 1 which is a processing unit of the multiprocessor system shown in FIG. 1, and 21 is a central processing unit C which is a processing center.
PU (central processing uni)
t), 22 are address decoders, and 23 is a bus interface. The CPU 21 is connected to the arbiter 4 via an address decoder, and is also connected to the bus 3 via a bus interface 23.

FIG. 3 is an internal block diagram of the memory element 2 which is one bank of the storage device of the multiprocessor system shown in FIG. 1, 31 is a bus interface on the request input side from the bus 3, and 32 is a request queue. , 33 is a bus interface on the response output side to the bus 3, 34 is a response queue, 35 is a memory controller, and 36 is a memory IC.

In this embodiment, each processor element 1 accesses each memory element 2. The operation of the processor element 1 inside, the memory element 2 inside, and the entire system at the time of memory access will be described below. To do.

In the processor element 1, when a memory access request is issued, the CPU 21 outputs information such as an address of an access destination as access information. The access information is sent to the bus interface 23 for transmission to the access destination, and is pooled until the use of the bus 3 is permitted by the arbiter 4. In this embodiment, the number of the memory element 2 of the access destination of this access information (hereinafter referred to as the access destination ME number) is notified to the arbiter 4 to request the use of the bus 3. .. Therefore, in order to know which memory element 2 is the memory element 2 of the access destination, the access destination address is sent to the address decoder 22 and is decoded, whereby the access destination M
Get the E number. The obtained access destination ME number is sent to the arbiter 4 as a bus use request signal.

In the arbiter 4, when the bus 3 is arbitrated and assigned by the method described later and a request is accepted, the arbiter 4 sends one bus out of the k buses 3 to the processor element 1. The use of the bus is permitted by selecting and notifying the number of the selected bus. The bus interface 23 of the processor element 1 that is permitted to use the bus outputs the access information to the bus 3 designated by the arbiter 4 for a certain period, and then releases the bus.

On the other hand, in the memory element 2 of the access destination, the processor element 1 of the access source
When the use of the bus 3 is permitted, the number of the bus 3 used by the access source processor element 1 is notified from the arbiter 4 to the request input side bus interface 31 as a fetch instruction signal. The request input side bus interface 31 that has received the notification fetches the access information output from the access source processor element 1 for a certain period of time and transfers it to the request queue 32. The request queue 32 stores this access information. The memory controller 35 takes out the accumulated access information from the head of the request queue 32, accesses the memory IC 36 based on this access information, and transfers the access result to the response queue 34. The response queue 34 stores the access result. The bus interface 33 on the response output side takes out the accumulated response result from the head of the response queue 34 and transfers the access result to the bus designated by the arbiter 4.

The contents of the access result stored in the response queue 34 include the actual access result data and the number of the response destination processor element 1 (hereinafter referred to as the response destination PE number). The interface 33 sends a response destination PE number to the arbiter 4 as a bus use request signal. In the arbiter 4, arbitration and allocation of the bus 3 are executed by a method described later, and if a request is accepted in this case, the arbiter 4 selects one of the k buses for the memory element 2 concerned. The use of the bus 3 is permitted by notifying the bus number. At the same time, the arbiter 4 notifies the processor element 1 of the response destination of the bus number used by the response source memory element 2 as a fetch instruction signal.

The bus interface 33 on the response output side of the response source memory element 2 outputs the access result data to the bus designated by the arbiter 4 for a certain period of time and releases the bus again. The bus interface 23 of the response destination processor element 1 fetches the access result data, and the CPU 21 fetches the access result from the bus interface 23 to complete the memory access.

Further, the memory controllers 35 of all the memory elements 2 notify the arbiter 4 of the number of pieces of access information stored in the request queue 32 as load information. As a result, the arbiter 4 can always grasp the load states of all the memory elements 2.

The arbitration and allocation of the bus 3 is (1) a request from the processor element 1 or a memory element 2, or (2) the processor element 1
Access destination memory element 2 if the request is from
Load weight, which is a priority. The bus use request from the memory element 2 has the highest priority, and the bus use request for accessing the ME having a light load is prioritized in order. Arbiter 4
When a plurality of bus use requests are received at one time, the bus is assigned in order from the bus use request with the highest priority.

When k <m + n, there may be requests that the use of the bus is not permitted, in which case the requests are repeatedly arbitrated until the use of the bus is permitted. However, in most cases, the bus use request for which the permission cannot be obtained is due to the memory access request for the heavily loaded memory element 2, and the use permission of the bus 3 is required until the response of the memory access is obtained. In most cases, it has nothing to do with the time to obtain.

In this embodiment, the address decoder 22 included in the processor element 1 can be included in the arbiter 4, and the memory controller 35 to the arbiter 4 of each memory element 2 can be included.
Load information sent to each processor element 1
It is also possible to calculate in the arbiter 4 according to the access destination information sent to the arbiter in response to the bus use request from the arbiter and the response destination information sent to the arbiter in response to the bus use request from each ME. The load information sent from each memory element 2 to the arbiter 4 can be omitted in order to further improve the function. As described above, the present invention can be variously modified and implemented without departing from the spirit of the present invention.

As is apparent from the above description, according to this embodiment, the bus cycle required for memory access from the processor unit to the main memory unit is the memory access request cycle from the processor unit and the response cycle from the main memory unit. Queues are provided for each of the request input side and response output side bus interfaces of each bank of the main memory to enable pipeline operation, and the arbiter for arbitrating the bus is divided into main memory devices. The bus arbitration request issued from each memory bank of each processor unit and main memory unit including the access destination is made so that the arbiter can monitor the load state of the memory bank. If it is a request from the storage device or (2) a request from the processor device, the load status of the access destination memory bank , Based on the two conditions, for dynamic prioritization to the bus use request, by arbitration, memory access when viewed as a whole system
The effect that the through put can be improved and the bus usage efficiency can be improved is obtained.

[0023]

As described above, according to the present invention, in a multiprocessor system including a plurality of processor devices, multiple buses and multiple banked storage devices, the bus utilization efficiency is improved and the memory access Through put is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a multiprocessor system that implements features of the present invention.

FIG. 2 is an internal block diagram of a processing device PE (processor element) of the multiprocessor system shown in FIG.

3 is an internal block diagram of ME (memory element) which is one bank of the storage device of the multiprocessor system shown in FIG. 1. FIG.

[Explanation of symbols]

 1 Processor Element 2 Memory Element 3 Bus 4 Arbiter 21 CPU 22 Address Decoder 23 Bus Interface 31 Request Input Side Bus Interface 32 Request Queue 33 Response Output Side Bus Interface 34 Response Queue 35 Memory Controller 36 Memory IC

Claims (2)

[Claims] 1. A multiprocessor system comprising a plurality of processor devices, multiple buses, and storage devices arranged in multiple banks, wherein a request cycle and a response cycle required to access the storage devices from the processor devices are provided in different bus cycles. Memory access means for executing, load monitoring means for monitoring a load condition based on an access request amount for each bank of the storage device, bus use requests in the request cycle and the response cycle, and the load monitoring means A multiple bus control system comprising: a bus allocating unit that performs bus arbitration and allocation based on the obtained load status of each bank of the storage device. 2. The memory access means further comprises storage means for executing pipeline operation of each memory bank by storing and extracting access information and access result. Multiple bus control method.