JPH03269588A - Electronic musical instrument - Google Patents

Abstract

PURPOSE:To reduce the scale of hardware and to reduce software processing by providing an arithmetic means which performs specific arithmetic as to phase information among plural pieces of musical sound information to find the read address of a waveform generating means and also performs specific arithmetic at different timing for musical sound information other than the phase information to find a musical sound parameter. CONSTITUTION:Musical sound information generating means 2 and 3 generate plural pieces of musical sound information. The arithmetic means 8 performs the specific arithmetic for the phase information among pieces of musical sound information to find the read address of the waveform generating means 13 and also performs the specific arithmetic for at least one piece of musical sound information other than the phase information at different timing from said arithmetic to find the musical sound parameter. Thus, the one arithmetic means 8 can perform the arithmetic for the pieces of musical sound information on a time-division basis. Consequently, the scale of the hardware is reduced and the software processing is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic musical instrument that efficiently uses a multi-pit arithmetic unit that generates a read address for a waveform memory that stores musical sound waveforms.

``Prior Art'' Traditionally, electronic musical instruments using a waveform memory read method have used a multi-hit adder (calculating unit) to calculate addresses in the waveform memory. On the other hand, the calculation of the musical tone parameters supplied to the EG (envelope generator), which requires various calculations such as scaling depending on the pitch, is performed by software or a specialized computing unit. ing.

"Problem to be Solved by the Invention" By the way, in the conventional electronic musical instruments mentioned above, when the calculation of musical tone parameters supplied to the EG etc. is performed by software, it places too much burden on the CPU (Central Processing Unit). Therefore, a problem arises in that only simple calculations can be performed in order to generate musical tones in real time in response to key presses.

Furthermore, if a dedicated arithmetic unit is used, the scale of the hardware becomes too large, which leads to an increase in cost.

In this invention, in consideration of the above-mentioned problems,
The purpose is to provide an electronic musical instrument with reduced hardware scale and software processing.

"Means for Solving the Problem" In order to solve the above-mentioned problems, the present invention provides an electronic musical instrument that produces musical tones based on a plurality of pieces of musical tone information.
musical tone information generating means for generating the plurality of pieces of musical tone information; waveform generating means for storing a plurality of pieces of waveform information for each address; It is characterized by comprising calculation means for determining successive addresses of the waveform generation means and calculating tone parameters by performing a predetermined operation on at least one piece of musical tone information other than the phase information at a timing different from the operation. do.

"Action Co. A musical tone information generating means generates a plurality of musical tone information.

The calculation means performs a predetermined calculation on the phase information among the plurality of pieces of musical tone information to obtain a read address of the waveform generating means, and performs a predetermined calculation on at least one piece of musical tone information other than the phase information at a timing different from the calculation. Perform calculations to obtain musical tone parameters. Therefore, one calculation means can perform calculations on a plurality of pieces of musical tone information in a time-sharing manner.

``Embodiment'' Next, Embodiment I of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this figure, ■ is a performance information generating section, which is composed of operators such as a keyboard.

This performance information generating section 1 generates a key-on signal KON and a key code KC in response to the operation of the operator.

The key-on signal KON is supplied to the address generator 2, start address memory 3, EC parameter memory 4, EC key scaling parameter memory 5, and delay circuit 6. In addition, the key code KC is stored in the address generator 2 and the EC key scaling parameter memory 5.
supplied to Next, 7 is a timbre specifying section which generates timbre information TC and supplies it to the start address memory 3, EC parameter memory 4 and EC key scaling parameter memory 5.

When the key-on signal K ON rises, the address generating section 2 sequentially generates phase data PH (24 bits: phase information) that changes at a rate corresponding to the key code KC and sends it to the input terminal A1 of the adder 8. supply Next, the start address memory 3 generates a start address 5TA (24 bits) corresponding to the timbre information TC, and outputs the start address 5TA (24 bits) to the input terminal B of the adder 8.
Supply to l. Further, the EC parameter memory 4 stores envelope information for each tone color information TC.

This EC parameter memory 4 stores amplitude change data EGPL and speed change data EGPR in accordance with the timbre information TC.
(8 bits each: musical tone information) and other EC parameters are supplied to input terminals A2, A3 of the adder 8 and the envelope generator 14, respectively. Here, the amplitude change data EGPL is data regarding the amplitude of the envelope, and the speed change data EGPR is data regarding the degree of inclination (velocity) of the envelope.

Next, the EC key scaling parameter memory 5 stores the change rates KSL and KSR (respectively,
8-bit, musical tone information) is memorized. These rates of change KSL and KSR are supplied to inputs B2 and B3 of adder 8, respectively. Here, the rate of change KSL is the rate of change with respect to the amplitude change data EGPL mentioned above,
The above rate of change KSR is the speed change data EGPR mentioned above.
is the rate of change relative to

Next, the adder 8 adds the above-mentioned various data in a time division manner to add the address ADD, the envelope amplitude change data EGL, and the envelope speed change data E.
Calculate GR and latch circuits 10, 11 and 1, respectively.
Supply to 2. The latch circuit IO receives a clock φ.

and φ, are supplied, data is taken in at the rising edge of clock φ, and clock φ. The signal is output to the waveform generator I3 at the rising edge of the signal. In addition, the latch circuit I
1 and 12 are clocks φ. and φ, are supplied and capture data on the rising edge of clock φ, clock φ. At the rising edge of , envelope amplitude change data EGL and envelope velocity change data EGR are output to the envelope generator 14, respectively. Note that the clock φ mentioned above. , φ1. The details of φ will be described later.

Next, the waveform generating section 13 described above stores a plurality of musical tone waveform data WD, and selectively outputs the waveform data Wp corresponding to the address ADD to the multiplier 15. Further, the envelope generator I4 amplitude modulates the waveform data WD output from the waveform generating section I3.
Key-on signal KON supplied through delay circuit 6
At the rising edge of the envelope data ED, according to the envelope amplitude change data EGL, envelope velocity change data EGR and other EG parameters.
is formed and output to the multiplier 15. The multiplier 15 is
The waveform data WD and enherobe data ED are multiplied and output as musical waveform data. In addition, the clocks φADD and φ mentioned above. , φ1 and φ are generated in the timing generating means 16. These clocks φ,
The relationship among φ^DD, φ0°φ, and φ is shown in FIG. In this figure, two periods of the clock φ correspond to an ICH slot cycle, and one period corresponds to one time slot. Further, the clock φADD becomes high level in time slot “1” and becomes high level in time slot “0”.
” has a period of low level.

Also, the clock φ. is equal to the inverted clock φADII. Next, the clock φ1 is the clock φ
has a period in which it becomes high level when is low level and clock φADD is high level.

The last clock φ has a period in which it becomes high level when clock φ is low level and clock φADD is low level. As described above, since there is a phase difference between the rising edges of the clocks φ1 and φ, the latch timings of the latch circuits 10, 11 and 12 described above are different. That is, even if the same data bus is used at the output end of the adder 8 as shown, the address ADD and envelope amplitude change data EGL1 and envelope speed change data EGR can be completely separated.

Next, details of the adder 8 mentioned above will be explained with reference to the block diagram shown in FIG. In this figure, one is an adder, which combines phase data PH and start address S.
TA and output.

In addition, 20.21 is a selector, and one selector 2
0 selectively outputs either phase data PH or amplitude change data EGPL to input terminal A of adder 22 in accordance with clock φADD.

That is, when the clock φADD is at low level,
Amplitude change data EGPL is output, and when clock φADD is at a high level, phase data PH is output. Further, the other selector 21 selectively outputs either the start address STA or the rate of change KSL to the input end B of the adder 22 in accordance with the clock φADD. That is, when the clock φADD is at a low level, the rate of change KSL is output, and when the clock φADD is at a high level, the start address STA is output.

Next, 23.24 is also a selector similar to the above-mentioned selector 20.21, and one selector 23 has a clock φ
Either the speed change data EGPR or the phase data PH is selectively input to the input terminal A of the adder 25 according to ADD.
Output to. That is, when the clock φADD is at a low level, the speed change data EGPR is output, and when the clock φADD is at a high level, the speed change data EGPR is output. Outputs phase data PH. Further, the other selector 24 receives the clock φ^
Start address STA or rate of change KS depending on DD
Either one of R is selectively output to input terminal B of adder 25. That is, when the clock φADD is at a low level, the rate of change KSR is output, and when the clock φADD is at a high level, the start address STA is output.

Further, the carry-in Ci of the adder 19 is
It is connected to the carry-out Co of 2, and a carry is supplied. The carryout Co of the adder 25 is AN
It is supplied to one input terminal of the D gate 26. This AND
The other input terminal of the gate 26 has a N0TOR gate 29
A clock φ^DD is supplied through the circuit and 28. Therefore, the AND gate 26 receives the clock φAl). Only when is at a high level, it becomes "MJ" and the carry of the adder 25 is supplied to the adder 22.

The adder 22 adds the data supplied to input terminals A and B, supplies the lower 7 bits of the addition result to an OR gate 29, and supplies the most significant bit (MSB) to an AND gate 30. The OR gate 29 and ADD gate 30 are circuits for limiting overflow,
As a result of the addition, when the most significant bit stands, all remaining bits are set to "1" to reach the maximum value and saturate. The addition result of this adder 22 is the clock φ
Depending on the level of ADD, it is output as address ADD or envelope amplitude change data EGL. Further, in the same manner as the adder 22, the adder 25 adds the fco data supplied to the input terminals A and B, and supplies the addition result to the OR gate 31 and the AND gate 32. The addition result of this adder 25 is output as address ADD or envelope speed change data EGR depending on the level of clock φADD.

Next, we will discuss the operation of the embodiment with the above-mentioned configuration in the second section.
This will be explained with reference to the timing chart shown in FIG.

First, at time t, when a key is pressed on the keyboard, the key-on signal KON becomes high level, and the key code KC and tone information TC are supplied to each section. Address generation section 2 first outputs phase data P Ho in the first cycle of clock φADD.

Also, the start address memory 3 contains the start address S.
TA is output, and the EG parameter memory 4 stores amplitude change data EGPL, speed change data EGPR, and other E
Output G parameters. Further, the EG scaling parameter memory 5 outputs the rates of change KSL and KSR.

Next, at time tl''t, the adder 8 performs the following operation. First, since the clock φADD is at a low level during this time, the adders 22 and 25 perform the following operations.
The amplitude change data EGPL and the rate of change KSL, and the speed change data EGPR and the rate of change KSR are respectively added. In addition,
In this case, since the ADD gate 26 is closed, the carry of the adder 25 is not supplied to the adder 22. Therefore, in this time slot "0", each of the above operations is performed in each of adders 22 and 25. Each adder 2
The lower 7 bits of the addition results of 2 and 25 are output as envelope amplitude change data EGL and envelope speed change data EGR. These envelope amplitude change data EGL and envelope speed change data EGR are latched by latch circuits I2 and 12, respectively, at the rising edge of clock φ (see time tI° in FIG. 2).

Next, at times t to t3, the adder 8 performs the following operation. First, in the adder 19, the phase data PHo
and start address STA are added. Also, since the clock φADD is at a high level, the adders 22 and 25 add the phase data PHo and the start address STA, and add the phase data PHo and the start address STA, respectively. -ru.

In this case, the AND gate 26 is open, and the carry from the adder 25 is supplied to the adder 22. Therefore, in this time slot "1", adder 19.
22 and 25 are connected to perform the above-mentioned operation in tok form, and the addition results of each adder 19.22 and 25 are output as an address A.D.D.O. This address AD
Do is latched by the latch circuit 10 at the rising edge of the clock φ (see time t in FIG. 2) and output at the rising edge of the clock φ0. The waveform generating section I3 reads out waveform data according to the address A.sub.D.sub.o and supplies it to the multiplier 15.

Then, the clock φ at time t3. At the rising edge of , the latch circuit IO outputs the address ADDo to the waveform generator 13, and the latch circuit 11.degree.l2 outputs the envelope amplitude change data EGL and the envelope speed change data EGR, respectively, to the envelope generator I4. Then, the waveform generating section 13 generates the address A.
DD, the waveform data WD is successively generated and supplied to the multiplier I5. On the other hand, at the rising edge of the key-on KON delayed by the delay circuit 6, the envelope generator 14 generates envelope data ED according to the envelope amplitude change data EGL, envelope speed change data EGR, and other EG parameters.
is generated and supplied to multiplier I5.

Then, in the multiplier 15, the above-mentioned waveform data WD and envelope data ED are multiplied and outputted as musical waveform data.

Next, at time t3, address generator wJ2 outputs phase data PH. In addition, the start address ST
A, amplitude change data EGPL, speed change data EGPR
, rate of change KSL and rate of change KSR do not change. The above phase data PH, amplitude change data EGPL, speed change data EGPR.

The rate of change KSL and the rate of change KSR are supplied to an adder 8. Since the calculation in the adder 8 is performed in a time division manner like the above-mentioned fco calculation, first, in the first half cycle of the clock φADD, the envelope amplitude U conversion data EGL and the envelope speed change data EGR are obtained. In the latter half cycle, address ADD is determined.

In this case, the envelope amplitude change data EGL and the envelope speed change data EGR are from time t1 to t3.
(see Figure 4).

Hereinafter, time t s, ta, t after time t4?
. . ., the address generation unit 2 sequentially outputs phase data PH, PHs, PH, . Finally, the fifth control signal is controlled by the envelope amplitude change data EGL and the envelope speed change data EGR.
Musical waveform data having an envelope as shown in the figure is generated (this figure shows musical waveform data for bass and treble).

In the above embodiment, the time-division operation of the adder 8 has been described, but it is not limited to addition, and various other operations may be performed. Alternatively, a register may be provided at the output of the arithmetic unit, and the output of this register may be returned to the input of the arithmetic unit to be used like an accumulator.

Further, in this embodiment, time-division computation of address information and EG parameters has been described, but the computation target is not limited to this. Further, calculations may be further multiplexed to perform a large number of calculations, and multitone processing may be performed.

"Effects of the Invention" As explained above, according to the present invention, the musical tone information generation means generates a plurality of musical tone information, and the calculation means performs a predetermined calculation on the phase information among the plurality of musical tone information. The readout address of the waveform generating means is determined, and the calculating means is able to time-divisionally perform a predetermined calculation on at least one piece of musical tone information other than the above-mentioned phase information, thereby reducing the scale of the hardware. Also,
Software processing or mitigating benefits are obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
Fig. 2 is a timing chart of various clocks, Fig. 3 is a block diagram showing the configuration of the adder of the same embodiment, Fig. 4 is a timing chart showing the operation of the same embodiment, and Fig. 5 is a timing chart showing the operation of the same embodiment. FIG. 4 is a waveform diagram of musical waveform data of bass and treble tones. ■... Performance information generating section (performance operator), 2... Address generating section (musical tone information generating means), 3... Start address memory (musical tone information generating means), 8...
Adder (calculation means), 13... Waveform generation section (waveform generation means).

Claims (1)

[Scope of Claims] An electronic musical instrument that produces musical tones based on a plurality of pieces of musical tone information, comprising: musical tone information generation means for generating the plurality of musical tone information; and waveform generation means for storing a plurality of waveform information for each address. , calculating a readout address of the waveform generating means by performing a predetermined calculation on phase information among the plurality of pieces of musical tone information, and performing a predetermined calculation on at least one musical tone information other than the phase information at a timing different from the calculation. 1. An electronic musical instrument, comprising: calculation means for determining musical tone parameters by performing calculations.