JPH03268364A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain sufficient read currents at the time of erasing by bringing the film thickness of an insulating film in the extending section of a control gate to 600Angstrom or less. CONSTITUTION:A floating gate 15 composed of polysilicon is formed onto the surface of a semiconductor substrate 11 through a first gate oxide film 14, and a control gate 17 consisting of polysilicon, etc., is formed onto the floating gate 15 and the semiconductor substrate 11 through a second gate oxide film 16. A gate oxide film 18 is extended to the semiconductor substrate 11 at one end section (an offset section) of the control gate 17 at that time, and the thickness of an insulating film 18 in the extending section (the offset section) is brought to 600Angstrom or less. Accordingly, read currents at the time of erasing can be acquired at a sufficiently large value.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a semiconductor memory device.

(Prior Art) Conventionally, the following FE2FROMs are known. Hereinafter, the conventional technology of semiconductor memory devices will be explained with reference to FIG.

An N+ type source region 22 and an N+ type drain region 23 are formed on the surface of a semiconductor substrate 21 made of P-type silicon. A floating gate 25 made of a conductive layer is formed on the surface of the semiconductor substrate 21 sandwiched between the source region 22 and the drain region 23 with a first gate oxide film 24 interposed therebetween. A control gate 27 made of a conductive layer is formed on the floating gate 25 and the semiconductor substrate 21 with a second gate oxide film 26 having a thickness of 750 mm interposed therebetween.

At this time, a gate oxide film 28 having a thickness of 650 mm extends over the semiconductor substrate 41 at one end (offset portion) of the control gate 27 .

In this device, after erasing, holes exist in the floating gate 25 due to overerasing, and an inversion layer is formed on the surface of the semiconductor substrate 21 under the floating gate 25, so the read current is determined by the voltage applied to the offset section. controlled.

However, since the film thickness of the offset portion is 650 mm thick, there was a drawback that a sufficiently large read current during erasing could not be obtained.

(Problems to be Solved by the Invention) As described above, in the semiconductor memory device using the conventional technology, the thickness of the insulating film in the extended portion (offset portion) under the control gate is 650 thick, which causes problems during erasing. There was a problem that a sufficiently large read current could not be obtained.

In view of the above points, the present invention provides a semiconductor memory device that can obtain a sufficiently large read current during erasing.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor memory device according to the present invention includes a semiconductor substrate, a floating gate provided on the semiconductor substrate via a first insulating film, and a second insulating film on the floating gate. a control gate provided through a film, an end of the control gate overlaps at least a portion of the floating gate with an insulating film interposed therebetween, and a gap between the semiconductor substrate and the end of the control gate is provided. A feature is that the thickness of the insulating film is 600 Å or less.

(Function) In such a device, by setting the thickness of the insulating film in the extended portion of the control gate to 600 Å or less, a sufficient read current can be obtained during erasing.

(Example) Hereinafter, an example of a semiconductor memory device according to the present invention will be described with reference to FIG.

An N+ type source region 12 and an N type drain region 13 are formed on the surface of a semiconductor substrate 11 made of P type silicon. A first gate oxide film 14 with a thickness of 280 nm is formed on the surface of the semiconductor substrate 11 sandwiched between the source region 12 and the drain region 13.
Floating gate 1 made of polysilicon through
5 is formed. On this floating gate 15 and semiconductor substrate 11, a film thickness of 320 people is 0/N.
/O(oxide/SiN/oxide)
A control gate 17 made of polysilicon is formed through a second gate oxide film 16 of the structure.

At this time, at one end portion (offset portion) of the control gate 17, a gate oxide film 18 having a 210-layer O/N10 structure extends over the semiconductor substrate 11.

Such a structure is formed through the following steps. First, an oxide film 1 with a thickness of 280 mm is deposited on a P-type silicon substrate 11.
form 4. Next, a first polysilicon layer is formed on the oxide film 14. Next, the first polysilicon layer is PEP
A floating gate 15 is formed by processing, and an N type drain diffusion region 13 is formed using the floating gate as a mask.

Although not shown in the figure, the floating gate 15 and the second
An insulating film is formed between the polysilicon layer and the erase gate. Thereafter, the insulating film other than the insulating film 14 under the floating gate 15 is removed by wet etching. Next, a 320-layer insulating film 16 having a 0/N10 structure is formed on the floating gate 15. At the same time, the offset part has a Bottom with 0/N10 structure.
0x1d thickness 90 people / sIN film thickness 150λ pot Topox
The insulating film I8 is formed to have a thickness of 30 layers and a total thickness of 210 layers. After that, a control gate 17 made of a third polysilicon layer is formed on the insulating film IB, and the N+ type source diffusion region 12 is formed using the control gate 17 as a mask.
form. Note that, unlike this case, there is also a method in which the insulating film 18 in the offset portion is formed separately from the insulating film 16 on the floating gate 15.

In the semiconductor memory device of this embodiment described above, the thickness of the insulating film 18 in the offset portion has been increased from 850 to 210.
Made into a person. As shown in FIG. 3, the effect is that as the thickness of the insulating film in the offset portion becomes thinner, the read current during erasing increases. As shown, by setting the thickness of the insulating film in the offset portion to 600 Å or less, a sufficiently large read current during erasing can be obtained.

[Effects of the Invention] From the above results, by using the present invention, it is possible to obtain a sufficiently large read current during erasing in order to reduce the thickness of the insulating film in the extended portion (offset portion) of the control gate to 600 Å or less. Now you can.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor memory device according to the present invention, and FIG.
This figure is a cross-sectional view of a semiconductor memory device according to the prior art, and FIG. 3 is a diagram showing the relationship between the thickness of an insulating film in an offset part and the cell current in the offset part. IL 21... Semiconductor substrate, 12.22... N source diffusion region, 13.23... N+ drain diffusion region, 14.24... First insulating film, 15.25... Floating gate , 16.26... second insulating film,
17.27...Control gate, 18...Insulating film of offset part.

Claims (1)

[Claims] (1) A semiconductor substrate, a floating gate provided on the semiconductor substrate via a first insulating film, and a control gate provided on the floating gate via a second insulating film; The end portion overlaps at least a portion of the floating gate via an insulating film, and the thickness of the insulating film between the semiconductor substrate and the end portion of the control gate is 600 Å.
A semiconductor memory device characterized by the following.