JPH03266137A - Information processor - Google Patents

Abstract

PURPOSE:To read or modify an internal state optionally by an MPC by providing a scanning circuit which inputs the address signal from a selector, receiving the output of a scan register and an external scan address signal and selects one of them. CONSTITUTION:When a microinstruction at a microprogram control part(MPC) 10 is written in a scan register 16, an MPC mode, a scan mode, and a scan address are written in the scan register 16. When the selector 17 is switched to the internal scan address signal side in this MPC mode, the address which is set inside is inputted to the scan circuit 20 and a state value written in the flip-flop corresponding to the address is outputted to a scan-out (SOUT) termi nal. Then this scan-out value is written in a state holding register 18. Consequent ly, an optional internal state is read by the MPC 10 or altered without increas ing mutual connections between signal lines.

Description

[Detailed Description of the Invention] [Summary] Regarding an information processing device that performs information processing by microprogram control, a microprogram control unit (hereinafter abbreviated as MPC) can control any internal state without increasing the number of interconnections of signal lines. a microprogram control, an input bus connected to the microprogram control, an output bus connected to the microprogram control, A scan register that receives and holds an internal scan address signal output from the program control unit from an output bus, a selector that receives the output of the scan register and an external scan address signal and selects either one, and an address from the selector. It consists of a scan circuit that receives a signal, and a state holding register that receives a scan out signal from the scan circuit and whose output is connected to an input bus.When the microprogram control section sets the processor mode, it controls the selector. Allows the microprogram control unit to set the scan address, and allows the microprogram control unit to read the scan circuit's scan out signal via the state holding register, and instructs and executes the scan operation for its own device. Configure it as follows.

[Industrial Field of Application] The present invention relates to an information processing device that performs information processing under microprogram control.

[Prior Art] FIG. 5 is a block diagram of the configuration of a conventional device. In the figure, 10 is a microprogram control section (MPC).

The MPCIO is a program counter (PC)1.
Control storage (CS) 2, decoder (D)
3. It is composed of an internal register (IR) 4 and a logic operation unit (ALU) 5. C
52 stores a microprogram, and the PCI
A microinstruction stored at an address given by is read out and decoded by the decoder 3, and the operations of the IR 4 and ALU 5 are controlled based on the result. lR4
holds externally provided data or internal data,
Give to ALU5. The ALU 5 performs logical operations based on microinstructions, and the results are fed back to the IR 4 and held there.

11 is an input bus, 12 is an output bus, and 13 to 15 are registers (ER). 13 is input bus 11 and output bus 12
The register 14 holds the external input and provides it to the input bus, and the register 15 holds the internal output and outputs it as an external output. These registers 13-15 are addressed and can be accessed from MPClo.

In a device configured as described above, when reading the internal state, the register 13 is accessed, the contents of the output bus 12 are held, the held result is read to the input bus 11, and the result is read to the IR4 via the input bus 11. Load. When reading an external signal, the register 14 is accessed, the value of the external signal held in the register 14 is read out to the input bus 11, and then read into the IR4 via the input bus 11. When outputting the internal state to the outside, the contents of IR4 are placed on the output bus 12, and the contents of the output bus 12 are held in the register 15 by accessing the register 15. Thus, in the conventional device, in order for MPClo to access the registers, these registers had to be connected to the input bus 11 or output bus 12 to MPCIO.

Furthermore, in recent years, as LSIs have become more highly integrated, scan-in and scan-out methods have been adopted as a means for testing LSI testing procedures and device operation. This method uses scan circuits that use scan registers or flip-flops as registers or flip-flops for hardware failure diagnosis, and operates as ordinary registers or flip-flops during normal operation, and in scan mode, all scan registers are used as registers or flip-flops. can be accessed externally as one shift register or flip-flop,
This allows initialization and debugging of the internal state of the LSI. This scan-in/scan-out method calculates the state value of a specific flip-flop by supplying a scan address to the scan circuit from an LSI diagnostic device when testing the LSI itself, or from a subprocessing device when testing a device. It has the ability to read and change.

[Problems to be Solved by the Invention] In conventional devices, interconnection between registers and buses is required in order for MPCIO to access state values within the device, and in order to access all state values, The number of wiring signals increases. Also, in order to reduce the number of wiring signal lines, state values that are not normally accessed and things that can be processed at low speed, such as exception handling and error handling, are stored in MPCIO.
There is also a request to not have any connection with.

Furthermore, if a logical defect is discovered in highly integrated LSIs, it is possible to access a specific flip-flop even if it is not connected to the input bus 11 or output bus 12 to MPCIO. It is also necessary to resolve the fault by reading or changing the state value.

The present invention was made in view of these problems, and allows a microprogram control unit (MPC) to read any internal state without increasing the number of interconnections of signal lines.
Another object of the present invention is to provide an information processing device that can change internal state values.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. Components that are the same as those in FIG. 5 are designated by the same reference numerals. Note that the figure shows an external input circuit (circuit including the register 14) and an external output circuit (
The circuit including the register 15) is omitted. In the figure, 10 is a microprogram control unit (MPC) whose internal configuration is the same as that in FIG. 11 is an input bus connected to the microprogram control unit 10; 12 is an output bus connected to the microprogram control unit 10; 16;
17 is a scan register that receives and holds an internal scan address signal output from the microprogram control unit 10 from the output bus 12; 17 is a selector that receives the output of the scan register 16 and an external scan address signal and selects either one; 20 is a scan circuit which receives the address signal from the selector 17 at its input (IN); 18;
is a state holding register which receives the scan out (SOUT) signal of the scan circuit 20 and whose output is connected to the input bus 11. The external scan address signal is given, for example, from a sub-processing device (not shown), and the output of the scan circuit 20 is also output to the outside.

[Action control] The microinstruction output from MPCIO is used in MPC mode (a mode in which the MPC itself commands and executes a scan operation) and scan-in mode (in which a specific flip-flop in the scan circuit 20 is accessed and its state value is changed). Provide an area where you can specify the mode. Each of these mode settings can be set using one bit. In other words, when the area is “1”, each M
The PC mode and scan-in mode are used.

FIG. 2 is a diagram showing an example of the format of a microinstruction. The MPC flag has 1 bit, the scan in flag has 1 bit, and the rest is the scan address.

When the MPCIO microinstruction is written to the scan register 16, the MPC mode, scan-in mode, and scan address are written to the scan register 16. When the selector 17 is switched to the internal scan address signal side in this MPC mode, the internally set address enters the scan circuit 20, and the state value written in the flip-flop at that address is scanned out (
SOUT) terminal. This scanout value is written to the status holding register 18. The MPCIO can internally take in this scanout value via the input bus 11.

In addition, in the scan-in mode, if the scan-in mode flag is set to "1°," the flip-flop at the specified address of the scan circuit 20 is accessed, and the next data is transferred from the scan-in (S I N) terminal. This data can also be written to the flip-flop to change its state value.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 3 is an electrical circuit diagram showing essential parts of an embodiment of the present invention. Components that are the same as those in FIGS. 1 and 5 are designated by the same reference numerals. The data portion (8 bits) of the output of the register (ER) 14 that holds external input is connected to the input bus 11, and the data and parity bit P enter a parity checker 30 where a parity check is performed. .

The output of this parity checker 30 is input to a flip-flop 21 at scan address -oooooo in the scan circuit 20. In other words, scan address -ooo
ooo's flip-flop 21 is parity checker 30
The output (state value) is retained.

Of the data held in the scan register 16, MP
The C flag directly switches and controls the selector 17. In other words, when this MPC flag is set to "1", the selector 17 uses the MP
Select scan signals excluding the C flag. In addition,
When the MPC flag is 0'', the external scan signal is selected.

The output from the selector 17 (1 bit of scan-in signal and 6 bits of scan address) enters the scan circuit 20. A decoder 22 decodes the upper three bits of the scan address into eight signals, and a decoder 23 decodes the lower three bits of the scan address into eight signals. The outputs of the decoder 22 are ADHO to ADH7, respectively, and the outputs of the decoder 23 are ADLO to ADL7, respectively.
shall be.

The flip-flop 21 is composed of AND gates G1 to G5 and an OR gate G6. This configuration is the same for the other flip-flops 21 as well. The corresponding decode outputs of the decoders 22 and 23 are input to the AND gate G1, the scan-in signal and the output of the AND gate G1 are input to the AND gate G2, and the data input and clock are input to the AND gate G3. AND gate G4 contains a clock and a feedback signal from AND gate G2 output and OR gate G6. AND gate G5 has OR gate G6 output and AND gate G1
The AND gate G3 output and the AND gate G4 output are input to the OR gate G6. In this way, the flip-flop 2a constitutes a flip-flop whose output is a feedback signal. The output of OR gate G6 is a parity error output, and the output of AND gate G5 is a status output.

The output of AND gate G5 is OR gate G10 G11
State holding register 1 is shown in red for the select circuit consisting of
It is given to 8.

The operation of the circuit configured as described above will be explained as follows.

When the MPC mode, scan-in mode, and scan address are set in the scan register 16, the selector 17
selects and outputs the data output from MPCIO, that is, the data set at scan address 16. When the scan address is -0oooooo, ADHO and ADLO of the decoders 22 and 23 become "1". As a result, the AND gate G1 of the flip-flop 21 is “
In scan-in mode, the scan-in signal also becomes "1", so the output of AND gate G2 also becomes "1".
"become.

Therefore, the output of AND gate G4 becomes "0" and OR gate G6 is opened. On the other hand, external input data is in register 1.
Set to 4. The parity checker 30 checks the parity of external input data, and outputs "1°" when a parity error occurs. Pass G3, or Gate G6
to go into. As mentioned above, since the OR gate G6 is open, its output Q becomes "1" in synchronization with the rising edge of the clock.
”. In other words, it continues to hold “1” in synchronization with the clock. Output Q will output a parity error.

On the other hand, this parity error output Q enters one input of the AND gate G5, but since the other input of the AND gate G5 is open at 1°, this Q output passes through as is, and the OR gate GIO, 011, etc. The state holding register 18 is entered through the OR circuit of .The contents of this state holding register 18 are read into the MPCIO via the input bus 11.

In this way, MPC operation becomes possible.

By the way, when a parity error of "1" occurs, the system cannot proceed further, so there are cases where it is desired to clear this parity error. In this case, the circuit of the flip-flop 21 enters the scan-in mode to
Since AND gate G4 closes, flip-flop 21
The output Q of can be set to "0". Also, as shown in FIG. 4, the parity output is temporarily stored in the state holding register 18.
After holding the parity signal, the parity output is inputted again to the flip-flop 21A, and this parity output is inverted when inputted again. As a result, the Q output from the flip-flop 21A is
The output can be changed from "1°" to "0". In FIG. 4, the same parts as in FIG. Functions are added.

The AND gate G21 contains the value held by the state holding register 18, the scan-in signal, and the output of the AND gate G1. Its output goes into one input of AND gate G4. The AND gate G22 contains the inverted signal of the output of the state holding register 18, the scan-in signal, and the output of the AND gate G1. Its output goes into one input of OR gate G23. or gate 023
The other input of the AND gate G3 and the output of the AND gate G4 are input. And the or gate 02
The output Q of 3 is fed back to the AND gate G4,
It constitutes a flip-flop.

In the circuit configured as described above, when the parity error is "1", the data is temporarily held in the state holding register 18. Its output is the output of Antogame) G21.
1", and as a result, AND gate G4 is closed and its output becomes "0", and is inverted and input to AND gate G22, so the output of OR gate G23 becomes "0" in synchronization with the clock. - Once it becomes "0", it continues to hold that value.The Q output of this OR gate 023 is output as a parity error, but it becomes "0" and the parity error is cleared, so the system does not perform the next operation. You can proceed.

In the above embodiment, the output of the parity checker is scanned in, but it is also possible to scan in the outputs of various other registers connected to the bus by connecting them to the scan-in circuit. .

[Effects of the Invention] As described above in detail, according to the present invention, a microprogram control unit (hereinafter abbreviated as MPC) can read any internal state without increasing the number of interconnections of signal lines.
Alternatively, internal state values can be changed.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention. Figure 2 is a diagram showing an example of the format of a microinstruction. FIG. 3 is an electrical circuit diagram showing the main parts of an embodiment of the present invention; FIG. 4 is an electric circuit diagram showing the main parts of another embodiment of the present invention; FIG. 5 is a block diagram of a conventional device. In Figure 1, 10 is a microprogram control section 11 is an input bus, 12 is the output bus, 13 is a register, 16 is a scan register, 17 is a selector, 18 is a state holding register; 20 is a scan circuit. (MPC)

Claims (3)

[Claims] (1) a microprogram control unit (10), an input bus (11) connected to the microprogram control unit (10), and an output bus (12) connected to the microprogram control unit (10); The internal scan address signal output from the microprogram control unit (10) is output to the bus (12).
a scan register (16) that receives and holds the output from the scan register (16) and an external scan address signal, and a selector (17) that selects either one of the outputs of the scan register (16) and an external scan address signal; The microprogram control unit (10) comprises a scan circuit (20) that receives the scan circuit (20), and a state holding register (18) that receives the scan out signal of the scan circuit (20) and whose output is connected to the input bus (11). When set to processor mode, the selector (17) is controlled to set the scan address to the microprogram control section (10).
) can be set, and also allows the microprogram control unit (10) to read the scan out signal of the scan circuit (20) via the status holding register (18), and instruct the scan operation for its own device. ,
An information processing device characterized in that the information processing device executes the following information. (2) The information processing apparatus according to claim 1, further comprising a scan-in function for changing the state value of the scan circuit (20). (3) The information processing apparatus according to claim 1, further comprising a scan invert function for inverting the state value of the scan circuit (20) and a flip-flop (21A) capable of executing the scan invert function.