JPH03266035A - Microcomputer - Google Patents

Abstract

PURPOSE:To dynamically change the execution sequence and the execution speed of plural tasks by providing a memory which can execute the programming of the execution sequence of plural tasks, and changing dynamically the address sequence for reading the memory. CONSTITUTION:In an execution task control memory 105 which can execute the programming of the execution sequence of plural tasks, a task execution train and control information for controlling the read-out sequence are stored, and the task corresponding to the task number read out by an execution task read-out register 106 is executed selectively and successively. The read-out address of this execution task control memory 105 is generated by the combining values of a first counter 101 and a second counter 102, and a register 103, and by changing this combining method, plural address sequences corresponding to its combining method are changed dynamically. In such a manner, the execution sequence of plural tasks can be changed dynamically.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a microcomputer capable of executing multiple tasks, and more particularly to a microcomputer suitable for changing the sequence of execution tasks. (Conventional technology 1) A so-called pipeline architecture has been known as a technique for speeding up microcomputers. In this pipeline architecture, the number of pipeline stages is increased (the number of pipeline stages is deepened). This reduces the time it takes to advance the pipeline one stage, improving maximum performance. However, as the number of pipeline stages increases, each instruction being executed in the pipeline competes for resources. In order to avoid this, subsequent instructions must be executed with a delay until the time when resources can be used, which degrades the execution performance of the pipeline. A multi-task architecture has been proposed that sequentially executes multiple program sequences that would otherwise not be possible.An example of this architecture is
Discussed in the Proceedings of the 37th (Late of 1988) National Convention, pp. 191 to 192, or the 37th (Late of 1988) National Convention of the Information Processing Society, pp. 123 to 124. It is being Further, as parallel processing microprocessors that execute a plurality of microprograms in a time-sharing manner using a multitasking architecture, Japanese Patent Laid-Open No. 56-99546 and Japanese Patent Publication No. 1-23812 are known.

[Problem to be solved by the invention]

In the conventional technology described above, in order to change the execution order and execution speed of a plurality of tasks, it is necessary to rewrite the program or change the logic of the hardware. Therefore, when the microcomputer operates,
There was a problem in that it was not possible to dynamically change the execution order and execution speed of multiple tasks. An object of the present invention is to make it possible to change the number and types of tasks to be executed, the order of tasks to be executed, and the execution speed of each task in response to various conditions even when a microcomputer is operating. Our goal is to provide microcomputers.

[Means to solve the problem]

The above object is achieved by providing a memory in which the execution order of multiple tasks can be programmed, and a means for dynamically changing the address sequence for reading the memory (i.e., while the microcomputer is operating). be done. That is, as a first means, a register for generating an address for reading the memory and a plurality of counters are provided, and the contents of the register and the plurality of counters are combined for one access to the memory. A plurality of tasks are executed in sequence according to the task execution order read from the memory using this address. As an example of a more specific means, the memory for programming the execution order of the plurality of tasks includes a code for identifying the plurality of tasks as well as a control code for controlling the register and the plurality of counters; The control code is read and the address of the memory is generated. Further, a plurality of address registers are provided for holding a memory for storing execution programs of the plurality of tasks and an address for reading the memory, and a value of the address register and a task identification code corresponding to the address register are provided. A function is provided to generate an address for reading the memory from. Furthermore, the address register has a function that allows a specific value or an arbitrary value to be set regardless of the execution sequence 1 of the task corresponding to the address register.

[effect] According to the above means, it is possible to multidimensionally control the address for reading the memory, which allows programming of the execution order of multiple tasks. That is, by changing the combination of a plurality of counters and registers for generating an address for reading the memory, it is possible to dynamically change a plurality of address sequences corresponding to the combination. Therefore, it is possible to dynamically change the execution order of multiple tasks in accordance with the address sequence. Further, part of the information for controlling the combination of the plurality of counters and registers for generating the address, and the count-up and initialization of the counters is stored in a memory in which the execution order of the plurality of tasks can be programmed in advance. This makes it possible to program it in advance. Furthermore, by changing the value of the register at any time and for any period of time, it is possible to dynamically control address sequences that cannot be programmed in advance. Furthermore, even if the combination of the plurality of counters and registers is changed at any time and for any period of time, or the counters are counted up and initialized by means other than the above control code, the dynamic effect on the above address sequence cannot be changed. control is possible. Furthermore, according to the more specific means described above, it becomes possible to sequentially generate memory addresses in which execution programs for each task are stored, based on the contents of address registers corresponding to each of a plurality of tasks. . Here, when each task commonly uses the memory that stores the execution program, it becomes necessary to determine which task each execution program corresponds to. Therefore, means is provided for generating addresses for the memory using task identification codes so that they do not overlap between tasks. Regarding how to generate addresses, there are two methods: one is to set the execution programs of all tasks in address areas that do not overlap with each other in the memory, and the other is to set only the start address of the execution program of each task, or only a part including the start address, so that it does not overlap with each other. There is a way to set it in the address area. Further, according to the more specific means described above, it becomes possible to dynamically change the sequence of execution programs for each task. That is, it becomes possible to initialize the execution program of a specific task at any time, to stop it at -, or to jump to an arbitrary address. Therefore, it is possible to dynamically change not only the execution task sequence but also the sequence of programs executed by each task, and dynamic sequence control is also possible at the execution program level when multiple tasks are executed in parallel. becomes. 【Example】

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a microcomputer that can sequentially execute multiple tasks in parallel in a time-sharing manner. The execution task control memory 105 stores task execution sequences and control information for read sequence control. Each task is identified by a task number, and the tasks corresponding to the task numbers read into the execution task read register 106 are selectively and sequentially executed. Regarding the data specifications of the execution task control memory 105, ,
This will be explained in detail later with reference to FIG. The read address of the execution task control memory 105 is:
It is generated by combining the values of the first counter 101, the second counter 102, and the register 103. In this example,
The second counter 102 and register 103 are set by the selector 10
Select by 4. Together with the value of the first counter 101, this is used as the read address of the execution task control memory 105. Here, the resetting of the first counter 101, the counting up of the second counter 102, and the control of the selector 104 are performed based on the control information read out to the execution task reading register 106. The control information specifications will be explained in detail with reference to FIG. The address management register file 107 holds microaddresses for the microprogram storage memory 108 corresponding to each task in registers corresponding to each task. The microaddress is generated by selectively reading the register corresponding to the task number based on the task number read into the execution task reading register 106. The detailed operation will be explained later with reference to FIG. The microinstruction of the execution task read out from the microprogram storage memory 108 is stored in the microinstruction reading register 109, decoded by the instruction decoder 110, and executed by the arithmetic execution unit 111. The next address generation unit 112 generates an address corresponding to the next microinstruction to be executed from the operation result 113 and the contents of the next address designation field of the microinstruction. This address is written into the register of the corresponding task in the address management register file 107, and read out the next time it is the task's turn to execute. Next, using FIG. 2, the execution task control memory 105
We will explain the data specifications and its operation. 201 is a task control matrix in which the value of the first counter 101 in FIG. 1 is used as a row address, and the value of the second counter 102 or register 103 is used as a column address. Each grid of the task control matrix 201 is unit data that is read out at one time, and a task number and control information are stored in each grid. The data specifications for one grid are 20
Shown in 2. The grid has n for identifying m tasks.
Bit task number data 205 and R control bit 20
4 and E control bits 203, each consisting of one bit. When 1 is read in the R11J control bit 204, the first counter 101 is reset to all O's, and the second counter 102 is incremented by 1. When the R control bit 204 is 0, the first counter 101 is incremented by 1, and the second counter 102 maintains its current value. When 1 is read into the E control bit 203, the column address of the task control matrix 201 becomes the value of the register 103, and when it is O, the column address becomes the value of the second counter 102. Further, it is assumed that the first counter 101 and the second counter 102 are all reset to O as an initial state when the present microcomputer is reset. That is, R control bit 204 and E control bit 203
are both O, the execution task column is sequentially downward from the first row of the first column of the task control matrix 201, starting from the grid number 0.
The data is read out from the lattice of O101 and 02. If both the R control bit 204 and the E control bit 203 remain O, the grids in the first column are read out in sequence downwards, and when they reach the grid number Oj in the last row, they return to grid number OO and read out again. Read out one row of grids in order. At this time, if 1 is read in the R control bit 204 in any row, the next grid to be read will be grid number 10, which is the first row of the column to the right, that is, the first row of the second column. , and then move down the grid in the second column, grid number 10.11.1
2 and read them in order. Also, when 1 is read in the E control bit 203 in any row, the column address of the next grid to be read is stored in the register 10.
The value is 3. That is, by setting a desired value in the register 103, the grid to be read from the next row can be read from any column. However, the effect of the E control bit is limited to the next line to be read. Therefore,
Unless a 1 is read following the E control bit 203, the column address of the next row read will return to the value of the second counter 102. In other words, without initializing the read sequence of a certain task execution sequence, E
A control bit allows a task execution sequence to be temporarily replaced with another task execution sequence. In this example, since the value of counter 1 is commonly used as the row address, it is possible to set certain conditions for the task execution order even if the column address is changed at any time as described above. It becomes possible. As an example, consider a case where the same task cannot be executed consecutively due to limitations caused by the execution pipeline. In this case, on the task control matrix 201, make sure that the same task does not exist between each vertically adjacent row or the row containing the lattice with the R control bit of 1 and the first row. Even if you change the column address at any time, you can prevent the same task from being executed continuously. As another example, consider a case where the first task and the second task among a plurality of execution tasks must be executed alternately. In this case, on the task control matrix 201, make sure that the first task and the second task do not coexist in each row, and start from the row where either task exists and start with the first task. Or, if there is a row where the second task exists and a row containing a lattice with the R control bit set to 1, go back to the first row, start downwards, and select the first or second task.
In the row where one task exists, only the other task exists. By doing this, even if the column address is changed at any time, the first task and the second task can always be executed alternately. Next, the detailed operation of the address management register file 107 shown in FIG. 1 will be explained using FIG. 3. Reference numeral 301 denotes a register for storing the microaddress of each task, which has a bit length necessary as an address for the microprogram storage memory shown in FIG. 1, and has registers for the number of tasks. Selection at the time of reading and writing of the register is performed based on the task number read out to the execution task readout register 106 in FIG. That is, the task number is decoded by the decoder 302, and the read selector 303 reads out the contents of the register corresponding to the task number. Further, the task number is delayed and held by the delay circuit 306 until a microaddress to be executed next for the task is generated, and after being decoded by the decoder 307, the task number is stored by the write selector 308.
select the register to write the address. Further, it is assumed that all address registers 301 are reset to 0 as an initial state when the microcomputer is reset. The address data read from the read selector 303 is input to an all “0” determination circuit 304 . al
The l"0" determination circuit 304 outputs the task number that selected the address data as it is, if the input address data is all 0, then outputs the address data as a microaddress.
Controls selector 305. In other words, the start address of each task is its own task number, and when starting from the initial state,
Even during operation, by setting the next address to all'''O'', any task can be returned to the first address at any time. Next, a method of setting values for the register 103 in FIG. 1 will be explained using FIG. 4. Reference numeral 401 denotes an interface for input signals from outside the chip, which performs timing control and control of signal input specifications such as edge detection. Input/output interface 401
The signal inputted via the is written to the bit data storage 402 that can control input/output in bit units, and is sent to the register 103 via the priority encoder 403.
will be written to. The priority encoder 403 is a circuit for prioritizing each bit of the pit data storage 402, and prevents multiple selections when generating a column address according to each bit. Further, the value setting in the pit data storage 402 can also be performed by the microcomputer itself via the task execution unit. By doing so, the value of the register 103 can be dynamically changed in response to conditions occurring outside the chip as well as conditions occurring within the chip. In other words, it is possible to dynamically select an execution task sequence corresponding to each condition for the execution task control unit.
A condition that occurs inside the chip can clear a condition that occurred outside the chip, or a new value can be set.

【Effect of the invention】

According to the present invention, in a microcomputer that has a memory that stores a task execution order for executing multiple tasks and executes multiple tasks, the execution sequence of the tasks can be changed without rewriting the values in the memory. It has the effect of being able to change dynamically.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microcomputer that can execute multiple tasks sequentially and in parallel in a time-sharing manner; FIG. 2 is a diagram showing a task control matrix and its data specifications;
FIG. 3 is a detailed block diagram of the register file for address management, and FIG. 4 is a diagram showing task execution sequence changing means using an external bin. Description of symbols 101...First counter for generating an address for the execution task control memory, 102...Second counter for generating an address for the execution task control memory, 103...Execution task control a register for generating an address for the memory for controlling the execution task, 104... a selector for generating an address for the memory for controlling the execution task;
105... Memory for execution task control, 106... Execution task read register, 107... Register file for address management, 201... Task control matrix, 203... E control billet, 204... R control bit, 301...address register, 304 ・=a
ll"O" determination circuit, 305...Selector for micro address generation, 402...Common writable pit data storage, 403...Priority encoder. Figure 1 Figure 2 Value of counter 2 or register 203 204 05 Figure 3 Figure 4

Claims (1)

[Claims] 1. A memory that stores a task execution order for executing a plurality of tasks, a register, a plurality of counters, and a register and a plurality of counters for one access to the memory. and means for generating an address by combining the contents of the counters, and sequentially executes a plurality of tasks according to the task execution order read from the memory using the address. 2. The memory stores a code for identifying a plurality of tasks as well as a control code for controlling the register and a plurality of counters, and reads the control code to generate an address of the memory. The microcomputer according to claim 1, characterized in that: 3. The microcomputer according to claim 2, wherein the control code includes first control information regarding initialization and counting up of the counter, and second control information regarding how to combine the register and counter. . 4. The microcomputer has a plurality of means for setting values in the register, and one of the plurality of means is a means for setting values from outside the chip of the microcomputer. Claims 1 to 3
A microcomputer according to any of the above. 5. As a means for executing multiple tasks, a memory for storing the execution program of the task and a plurality of address registers for holding the address for reading the memory are provided, and the value of the address register and 5. The microcomputer according to claim 1, wherein an address for reading the memory is generated from a task identification code corresponding to the address register. 6. The microcomputer according to claim 5, wherein the address register can be set to a predetermined value regardless of the execution sequence of the task corresponding to the address register.