JPH03265053A - Bus error processing system - Google Patents

Abstract

PURPOSE:To reduce the complication of a bus error processing caused by a software by providing a ROM/RAM bys error processing routine and a ROM subroutine means. CONSTITUTION:When a bus error exception is generated, a CPU 1 refers to a ROM vector table 21 of an address pointed out by a vector base register (VBR) 11, and fetches a bus error exception vector contained therein. An address of the bus error exception vector in the table 21 points out the head address of a ROM bus error processing routine 22, and the CPU 1 executes this bus error processing. The contents of the VBR 11 are rewritten so as to point out the address of a ROM vector table 31 by a ROM/RAM bus error routine processing switching means 33. In this case, when the bus error exception is generated, the CPU 1 refers to the RAM vector table 31 of the address pointed out by the VBR 11, and fetches its bus error exception vector. The CPU 1 executes this error processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device including a CPU, an I'tOM, and a RAM, and particularly relates to a bus error processing method.

[Conventional technology]

Conventionally, this type of bus error processing has not been implemented in the ROM, and even if it were, it was very simple, and the control was tedious for the operating system (hereinafter referred to as O8). In most cases, it was never used again.

Additionally, since the O8 needs to perform detailed recovery from bus errors such as system error processing and task error processing depending on the type of bus error, it is common for the KO8 to have its own path error processing in RAM. Shi, that process is O
In most cases, it was closed within 8.

Furthermore, even in software such as a diagnostic program where recovery from a bus error is not so important, the cause of the bus error can be analyzed by calling the diagnostic program itself when the bus error exception occurs within itself. , a ROM subroutine means that reaps the cause and returns the type of the cause as a code, and a processing start address is registered in the ROM vector table, and by calling the ROM subroutine means, ROM bus error processing routine means for reaping; RAM vector table means having a table in the RAM indicating a start address of exception processing as required by software; By calling the ROM subroutine means, the process 2-factor analysis tatami reaping code is performed.
Equipped with AM bus error handling routine means, a must-have software! ! Depending on the software, the VB
By rewriting R to the start address of the ROM vector table or the start address of the RAM vector table, either the ROM bus error processing routine or the RAM bus error processing routine is executed when a bus error exception occurs. The ROM, RAM, and bus error handling routine switching means are included.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and 1 is a block diagram of an embodiment of the present invention.
PU, 2 is ROM, 3 is RAM, 4 is bus, ', CP
If K VBRI 1 in the UI is blank, it will remain in the ROM vector table 21 until it is rewritten by software.
is pointing to. When a bus error exception occurs, the CPU
refers to the ROM vector table 21 at the address pointed to by VBRII and extracts the bus error exception vector therein. The address of the path error exception vector in the ROM vector table 21 points to the start address of the ROM bus error processing routine 22, and the CPU 9 executes this bus error processing.

The ROM bus error processing routine 22 calls the ROM subroutine 23 to eliminate the Scheller factor, and ends the bus error processing routine.

ROM prepared by software as needed
/RAM bus error routine processing switching means 33 converts the contents of VBRll to the RAM vector table 31.
is rewritten to point to the address of If a bus error exception occurs in this case, CPIJI refers to the RAM vector table 31 at the address pointed to by VBRll,
Extract the path error exception vector in it. The address of the path error exception vector in the RAM vector table 31 points to the start address of the RAM bus error processing routine 32, and the CPU 9 executes this bus error processing.

The RAM bus error processing routine 32 calls the RAM subroutine 23 to analyze, reap, and process Scheller factors. ! Codify the cause. Furthermore, RAM
The bus error:t-processing routine 32 performs recovery processing from a bus error according to the type of encoded error factor.

FIG. 2 shows the ROM bus error handling routine 22 (FI, 221, ROM bus error handling routine 22)! J, 2
22 is a ROM subroutine call instruction, and 223 is an exception return instruction. Since the purpose of ROM bus error processing is to extract the interrupt cause, the code of the interrupt cause is not used.

FIG. 3d shows the RAM bus error processing routine 32, j9.321 is the RAM bus error processing entry, 32
2 is a ROM subroutine call instruction, 323 is a bus error recovery processing routine, and 324 is an exception return instruction. The bus error recovery processing routine 323 allows software to perform detailed recovery processing from bus errors.

FIG. 4 shows the ROM subroutine 23.
1 is a ROM subroutine entry, 232 is a bus error factor analysis routine, and 233 is a bus error factor reaping sill.
Chia, 234 is a bus error factor encoding routine, 23
5 is a return instruction from the subroutine. This routine is commonly called from 22.32.

〔Effect of the invention〕

As explained above, the present invention includes a ROM vector table means having a table in the ROM indicating the start address of an exception handling that occurs before passing control to software, and a ROM vector table means that is called when a bus error exception occurs. ROM subroutine means that analyzes the cause of a bus error, harvests the cause, codes the type of the cause, and returns the code; and a ROM subroutine means in which a processing start address is registered in the ROM vector table; It is equipped with a ROM bus error handling routine means that reaps the cause of the error by calling
RAM vector table means having a table indicating the start address of exception processing and the processing start address are registered in the RAM vector table and call the ROM subroutine means as required by the software. Especially when analyzing and reaping error causes.
A RAM bus 2-processing routine means for encoding is provided, and the software converts the VBR to the starting address of the ROM vector table,
Alternatively, by rewriting the start address of the RAM vector table, when a bus error exception occurs, execution of either the ROM bus error processing routine or the RAM bus error processing routine is switched. By providing a ROM/RAM bus error processing routine switching means, after a bus error occurs, it is necessary to perform detailed recovery processing from the bus error according to the cause of the bus error. Depending on whether or not the software has its own path error handling in RAM,
Even if there is a need to have internal bus error processing, the ROM subroutine means can be used to process processes that are closely related to the hardware. This has the effect of reducing the complexity of bus error processing by software.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
M0M pass error M routine chart 70, Figure 3 is R
70 of the AM bus error handling routine, FIG. 4 is a flowchart of the ROM subroutine. 1...--Central processing unit (CPU), 2...
・Non-volatile memory (ROM), 3...Readable/readable memory (RAM'), 4...Bus, 11°
°'...Vector pace register (VBR), 21.
...ROM vector table, 22...
ROM bus error processing routine, 23...RO
M subroutine, 31... To RAM, 32... RAM bus error processing routine, 33... ROM/RAM path error processing route/switching, 221 ...ROM Ha, x,
Error processing/t1c 222-----ROM subroutine call instruction, 223...Return from exception instruction, 231...ROM subroutine entry, 232...・Bus ``j'' factor N analysis routine, 233 ・Old...Bus r-2-factor reaping reroutine, 234...Path error factor coding routine, 235...Return command from subroutine ,3
21...RAM bus error processing entry, 32
2...ROM subroutine call instruction, 32
3...Path error recovery processing routine, 324.
...Return command from exception.

Claims (1)

[Claims] When a bus error exception occurs, the CPU (central processing unit) is equipped with a VBR (vector base register) that indicates the start address of the vector table that indicates the exception processing start address, and stores the processing up to passing control to software. ROM (non-volatile memory) and read/write RAM (
ROM vector table means having a table indicating a start address of an exception process that occurs before passing control to the software in the ROM; ROM subroutine means that is called when the bus error exception occurs to analyze the cause of the bus error, reap the cause, code the type of the cause, and return the code, and a processing start address stored in the ROM vector table. RO that is registered and performs reaping of error causes by calling the ROM subroutine means.
M bus error processing routine means, RAM vector table means having a table indicating a start address of exception processing in the RAM as required by software, and a processing start address registered in the RAM vector table. and a RAM bus error processing routine means for analyzing, reaping, and coding the cause of the error by calling the ROM subroutine means. By rewriting the start address of the vector table or the start address of the RAM vector table, the ROM/ROM can be switched to execute either the ROM bus error processing routine or the RAM bus error processing routine when a bus error exception occurs. A bus error processing method comprising: RAM bus error processing routine switching means.