JPH03263362A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03263362A JPH03263362A JP2062036A JP6203690A JPH03263362A JP H03263362 A JPH03263362 A JP H03263362A JP 2062036 A JP2062036 A JP 2062036A JP 6203690 A JP6203690 A JP 6203690A JP H03263362 A JPH03263362 A JP H03263362A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- semiconductor chip
- parts
- based board
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000002184 metal Substances 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims description 16
- 238000007789 sealing Methods 0.000 claims description 4
- 238000005452 bending Methods 0.000 claims description 2
- 238000001721 transfer moulding Methods 0.000 abstract description 11
- 239000011347 resin Substances 0.000 abstract description 10
- 229920005989 resin Polymers 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 9
- 239000000853 adhesive Substances 0.000 abstract description 4
- 230000001070 adhesive effect Effects 0.000 abstract description 4
- 238000000465 moulding Methods 0.000 abstract description 3
- 230000017525 heat dissipation Effects 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000004382 potting Methods 0.000 description 2
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は半導体装置の製造方法、特に表面実装用で、多
ピン且つ薄型化を図るとともに、放熱性及びリードの平
坦性、整列性の良好な半導体装置を安価に製造できるよ
うにした半導体装置の製造方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention is directed to a method of manufacturing a semiconductor device, particularly for surface mounting, which aims to reduce the number of pins and thickness, and improve heat dissipation and lead flatness. The present invention relates to a method of manufacturing a semiconductor device, which allows semiconductor devices with good alignment to be manufactured at low cost.
（従来の技術）
従来、多ビン化を図った半導体装置としては、入出力端
子としてリードフレームを用い、このリードフレームの
各リードと半導体チップの各電極とを電気的に接続させ
た後、樹脂等に封止することによって構成したものが一
般に広く知られている。(Prior art) Conventionally, a semiconductor device designed to have multiple bins uses a lead frame as an input/output terminal, and after electrically connecting each lead of this lead frame to each electrode of a semiconductor chip, resin It is generally widely known that the device is constructed by sealing the device.
しかしながら、上記リードフレームを使用した半導体装
置においては、リードフレーム材の板厚等のからみで、
各リード間のピッチ及び各リードの幅には夫々一定の限
界があり、それらは夫々０．２５＋ｎｍ、０．１２−程
度であるのが現状であった。このため、多ピン化を図ろ
うとすると、これに伴ってパッケージ全体の面積の増大
に繋がってしまっていた。However, in semiconductor devices using the above lead frame, due to factors such as the thickness of the lead frame material,
There are certain limits to the pitch between each lead and the width of each lead, which are currently about 0.25+nm and 0.12-nm, respectively. For this reason, when attempting to increase the number of pins, this leads to an increase in the area of the entire package.
また、放熱特性にも問題があり、放熱特性はヒートシン
クを用いなければＩＷ程度が限界であるのが現状であっ
た。Furthermore, there is also a problem with heat dissipation characteristics, and currently the heat dissipation characteristics are limited to about IW unless a heat sink is used.
このため、出願人は先に、特願昭６２−１９８４４３号
として、金属板で補強されたメタルベース基板の上面に
銅箔による配線パターンを形成し、プレス等による絞り
加工を施した後、半導体チップを搭載し該半導体チップ
の各電極と上記各配線パターンとを電気的に接続し、し
かる後ポツティングによって半導体チップを樹脂封止す
るようにしたものを提案した。For this reason, the applicant previously proposed in Japanese Patent Application No. 62-198443 that a copper foil wiring pattern was formed on the top surface of a metal base board reinforced with a metal plate, and after drawing with a press or the like, a semiconductor We have proposed a method in which a chip is mounted, each electrode of the semiconductor chip is electrically connected to each of the wiring patterns, and then the semiconductor chip is sealed with a resin by potting.
（発明が解決しようとする課題）
しかしながら、上記特願昭６２−１９８４４３号に記載
のものは、所望の効果を奏するものの、予めパッケージ
形状に絞り加工を施したメタルベース基板を使用するた
め、一般的に使用されている半導体装置のパッケージ組
立てラインをそのまま使用することができずに、加工コ
ストの増大に繋がってしまうばかりでなく、ポツティン
グによって半導体チップを樹脂封止しているため、パッ
ケージの厚みが均一となならず、かつボッティングは一
般に厚みが増す傾向があるため、これをより薄くかつ均
一な厚さにすることがかなり困難であることが判った。(Problem to be Solved by the Invention) However, although the method described in the above-mentioned Japanese Patent Application No. 198443 has the desired effect, it uses a metal base substrate that has been drawn into a package shape in advance, so it is not commonly used. It is not possible to use the package assembly line for semiconductor devices that is currently used as is, which not only leads to increased processing costs, but also increases the thickness of the package because the semiconductor chips are encapsulated in resin by potting. It has been found that it is quite difficult to make it thinner and more uniform in thickness, since it is not uniform and botting generally tends to increase in thickness.
本発明は上記に鑑み、上記メタルベース基板を使用した
半導体装置の製造方法に更に改良を加え、この種の半導
体装置の有する効果、即ち多ピン化を図ることができ、
かつ高放熱特性が得られるといった効果を保持しつつ、
安価にしかもより薄型化を図ることができようにしたも
のを提供することを目的とする。In view of the above, the present invention further improves the method of manufacturing a semiconductor device using the metal base substrate, and achieves the effect of this type of semiconductor device, that is, increasing the number of pins.
While maintaining the effect of obtaining high heat dissipation characteristics,
The purpose is to provide a product that is inexpensive and can be made thinner.
（課題を解決するための手段）
上記目的を達成するため、本発明に係る半導体装置の製
造方法は、金属板で補強されたメタルベース基板の上に
配線パターンを形成し、半導体チップを搭載し該半導体
チップの各電極と上記各配線パターンとを電気的に接続
した後、トランスファーモールドによって半導体チップ
全体を樹脂封止し、しかる後、外部リード部となるメタ
ルベース基板部分に曲げ加工を施すようにしたものであ
る。(Means for Solving the Problem) In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention forms a wiring pattern on a metal base substrate reinforced with a metal plate and mounts a semiconductor chip. After electrically connecting each electrode of the semiconductor chip and each of the above-mentioned wiring patterns, the entire semiconductor chip is sealed with resin by transfer molding, and then the metal base substrate portion that will become the external lead portion is bent. This is what I did.
（作 用）
上記のように構成した本発明によれは、従来の一般な半
導体装置用のパッケージ組立てラインと同一のプロセス
を使用することができるため、組立てコストを最も安価
に抑えることができるとともに、平板上にマウントした
半導体チップをトランスファーモールドによって樹脂封
止することにより、この平坦性を確保してパッケージの
より薄型化を図ることができる。(Function) According to the present invention configured as described above, it is possible to use the same process as the conventional package assembly line for general semiconductor devices, so that the assembly cost can be kept at the lowest possible cost. By sealing a semiconductor chip mounted on a flat plate with resin using transfer molding, flatness can be ensured and the package can be made thinner.
（実施例） 以下、本発明の実施例を図面を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.
第１図は、第１の実施例を工程順に示すもので、先ず同
図（ａ）に示すように、例えばＡρ等の金属板で補強さ
れた平板でテープ状に一方向に延びるメタルベース基板
１の一面に、接着剤２を介して１／２オンス（厚さ１８
μｍ）または１オンス（厚さ３５μｍ）の銅箔をラミネ
ートし、エツチング等の化学処理を施して、銅箔による
所定の形状の配線パターン３を形成する。このエツチン
グ処理の先立って、またはこの処理の後に、メタルベー
ス基板１にパンチング等を施して、これを所定のフレー
ム形状とする。また、上記各配線パターン３の半導体チ
ップ４の各電極との接続部分にはメツキ処理を施してお
く。FIG. 1 shows the first embodiment in the order of steps. First, as shown in FIG. Apply 1/2 ounce (thickness 18 mm) to one side of 1 with adhesive 2
A copper foil of 1 ounce (35 μm in thickness) or 1 ounce (thickness: 35 μm) is laminated and subjected to chemical treatment such as etching to form a wiring pattern 3 of a predetermined shape using the copper foil. Prior to or after this etching process, punching or the like is performed on the metal base substrate 1 to form it into a predetermined frame shape. Further, the connection portions of each of the wiring patterns 3 to each electrode of the semiconductor chip 4 are plated.
この時、配線パターン３の位置精度は、銅箔のエツチン
グ精度によって決まり、従って、この配線パターン（リ
ード）３の幅およびリード間ピッチを通常の一般的なリ
ードフレームのリードと比較してかなり狭くすることが
できる。At this time, the positional accuracy of the wiring pattern 3 is determined by the etching accuracy of the copper foil, and therefore the width of this wiring pattern (lead) 3 and the pitch between the leads are considerably narrower than the leads of a normal general lead frame. can do.
なお、上記メタルベース基板１として、Ａｉ）基板の他
に銅基板や４２アロイ等の鉄合金基板を使用することで
きことは勿論であり、このようにメタルベース基板１を
使用することにより、半導体チップ４の放熱性の向上を
図ることができる。It is of course possible to use a copper substrate or an iron alloy substrate such as 42 alloy as the metal base substrate 1 in addition to the Ai) substrate, and by using the metal base substrate 1 in this way, semiconductor The heat dissipation of the chip 4 can be improved.
そして、同図（ｂ）に示すように、フレーム形状をした
メタルベース基板１の半導体チップ搭載位置に、接着剤
２を介して半導体チップ４をマウントし、この半導体チ
ップ４の各電極と上記各配線パターン３とをボンディン
グワイヤ５でボンデインクした後、トランスファーモー
ルド装置を使用したトランスファーモールドによって、
主に半導体チップ４の表面を主体としたモールド樹脂６
による樹脂封止を行う。Then, as shown in FIG. 2(b), a semiconductor chip 4 is mounted via adhesive 2 at the semiconductor chip mounting position of the frame-shaped metal base substrate 1, and each electrode of this semiconductor chip 4 and each of the above-mentioned After bonding the wiring pattern 3 with the bonding wire 5, by transfer molding using a transfer molding device,
Mold resin 6 mainly for the surface of semiconductor chip 4
Perform resin sealing.
この時、メタルベース基板１はほぼ平坦であり、平板の
上にトランスファーモールドによって樹脂を封止する形
式となるので、パッケージのより薄型化を図り、例えば
１ｍｍ程度の薄さを確保することができるようになる。At this time, the metal base substrate 1 is almost flat, and the resin is sealed onto the flat plate by transfer molding, so the package can be made thinner, for example, about 1 mm thick. It becomes like this.
しかる後、メタルベース基板１から、外部リード部とな
るメタルベース基板部分を含めて切り離し、この外部リ
ード部となるメタルベース基板部分に所定のリード形状
に曲げ加工を施すか、または逆に外部リード部となるメ
タルベース基板部分に所定のリード形状に曲げ加工を施
した後、これをメタルベース基板１から切り離し、これ
によって同図（ｃ）に示す半導体装置を製造するのであ
る。After that, the metal base board part including the metal base board part that will become the external lead part is separated from the metal base board 1, and the metal base board part that will become the external lead part is bent into a predetermined lead shape, or conversely, the metal base board part that will become the external lead part is bent into a predetermined lead shape. After bending the metal base substrate portion that will become the lead shape into a predetermined lead shape, this is separated from the metal base substrate 1, thereby manufacturing the semiconductor device shown in FIG. 1(c).
このようにして、半導体装置を製造することにより、従
来から一般に使用されている半導体装置製造用のパッケ
ージ組立てラインと同一のプロセスをそのまま使用する
ことができ、これによって組立てコストを最小限に抑え
ることができるようになる。By manufacturing semiconductor devices in this way, it is possible to use the same process as the package assembly line for manufacturing semiconductor devices that has been generally used in the past, thereby minimizing assembly costs. You will be able to do this.
なお、上記トランスファーモールドの際に、トランスフ
ァーモールド装置のキャビティ部分内に予め金属片７を
挿着しいおいてこれを行うことにより、第２図に示すよ
うな半導体チップ５の上方をこの金属片７で覆った半導
体装置を容易に製造るすることができる。Note that during the transfer molding process, by inserting the metal piece 7 in advance into the cavity of the transfer molding device, the metal piece 7 is placed above the semiconductor chip 5 as shown in FIG. It is possible to easily manufacture a semiconductor device covered with .
このようにして、半導体チップ４の両面に金属部分を存
在させることにより、耐熱性および耐湿性を向上させて
、パッケージ特性を向上させることができる。In this way, by providing metal parts on both sides of the semiconductor chip 4, heat resistance and moisture resistance can be improved, and package characteristics can be improved.
本発明は上記のような構成であるので、従来から一般に
実施されている半導体製造用のパッケージ組立てライン
と同一のプロセスを使用して半導体装置を製造すること
ができ、これによって組立てコストも最も安価に抑える
ことができるとともに、平板の上にトランスファーモー
ルドによってモールドすることにより、パッケージのよ
り薄型化を図ることができる。Since the present invention has the above-described configuration, it is possible to manufacture semiconductor devices using the same process as the package assembly line for semiconductor manufacturing that has been generally implemented in the past, and as a result, the assembly cost is also the lowest. In addition, by molding on a flat plate by transfer molding, the package can be made thinner.
しかも、メタルベース基板を使用することによる利点、
即ち、多ピン化に対応することができるとともに、高放
熱特性をを得られるといった利点を損なってしまうこと
もない。Moreover, the advantages of using a metal base board,
That is, it is possible to cope with an increase in the number of pins, and the advantage of high heat dissipation characteristics is not lost.
更に、半導体チップの両面に金属部分が存在するように
なすことも容易にてき、これによって高放熱性及び高耐
湿性を得て、パッケージの特性を向上を図るようにする
こともできるといった効果がある。Furthermore, it is easy to make metal parts exist on both sides of a semiconductor chip, which has the effect of providing high heat dissipation and high moisture resistance, and improving the characteristics of the package. be.
装置を示す断面図である。FIG. 2 is a cross-sectional view showing the device.
１・・・メタルベース基板、２・・・接着剤、３・・・
配線パターン、４・・・半導体チップ、５・・・ボンデ
ィングワイヤ、６・・・モールド樹脂、７・・・金属片
。1... Metal base board, 2... Adhesive, 3...
Wiring pattern, 4... Semiconductor chip, 5... Bonding wire, 6... Molding resin, 7... Metal piece.
Claims (1)
ンを形成し、半導体チップを搭載し該半導体チップの各
電極と上記各配線パターンとを電気的に接続した後、ト
ランスファーモールドによって半導体チップ全体を樹脂
封止し、しかる後、外部リード部となるメタルベース基
板部分に曲げ加工を施すことを特徴とする半導体装置の
製造方法。After forming a wiring pattern on a metal base substrate reinforced with a metal plate, mounting a semiconductor chip, and electrically connecting each electrode of the semiconductor chip to each wiring pattern, the entire semiconductor chip is transferred and molded. 1. A method of manufacturing a semiconductor device, which comprises resin-sealing and then bending a metal base substrate portion that will become an external lead portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2062036A JPH03263362A (en) | 1990-03-13 | 1990-03-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2062036A JPH03263362A (en) | 1990-03-13 | 1990-03-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03263362A true JPH03263362A (en) | 1991-11-22 |
Family
ID=13188539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2062036A Pending JPH03263362A (en) | 1990-03-13 | 1990-03-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03263362A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0817988A (en) * | 1994-06-28 | 1996-01-19 | Hitachi Ltd | Resin-sealed semiconductor device and manufacture thereof |
-
1990
- 1990-03-13 JP JP2062036A patent/JPH03263362A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0817988A (en) * | 1994-06-28 | 1996-01-19 | Hitachi Ltd | Resin-sealed semiconductor device and manufacture thereof |
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