US20180261469A1 - Method for Making Lead Frames for Integrated Circuit Packages - Google Patents

Method for Making Lead Frames for Integrated Circuit Packages Download PDF

Info

Publication number
US20180261469A1
US20180261469A1 US15/955,435 US201815955435A US2018261469A1 US 20180261469 A1 US20180261469 A1 US 20180261469A1 US 201815955435 A US201815955435 A US 201815955435A US 2018261469 A1 US2018261469 A1 US 2018261469A1
Authority
US
United States
Prior art keywords
lead frame
preformed
die attach
attach pad
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US15/955,435
Other versions
US10079162B1 (en
Inventor
You Chye HOW
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to US15/955,435 priority Critical patent/US10079162B1/en
Publication of US20180261469A1 publication Critical patent/US20180261469A1/en
Application granted granted Critical
Publication of US10079162B1 publication Critical patent/US10079162B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4875—Connection or disconnection of other leads to or from bases or plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • Integrated circuit devices generally include an integrated circuit chip and a lead frame which are sealed within a protective enclosure, find wide use in various products, among which are consumer electronics, computers, automobiles, telecommunications and military applications.
  • the lead frame electrically interconnects the integrated circuit chip to circuitry external to the device.
  • the lead frame is typically formed from a highly electrically and thermally conductive material, such as copper or copper alloys.
  • the lead frame material is stamped or etched into a plurality of leads, and a central area, called a die attach pad, onto which the integrated circuit chip is attached.
  • the chip is electrically connected to the leads, usually by wire bonding, and the device is encapsulated to provide mechanical and environmental protection.
  • Conventional lead frames for integrated circuit packages are typically made using metal etching processes to create die attach pads and leads from a conductive layer of material on a bulk substrate or other material. Such process involves etching the conductive layer of material to form discrete conductor structures (e.g., the die attach pads and the leads). The etching process typically limits the spacing between the die attach pads and/or between adjacent leads on these conventional lead frames to at least one thickness of the conductive layer of material due to physical limitations of etching technology. In addition, the portions of the conductive layer removed from the substrate during the etching process generate waste in the manufacturing process. Manufacturer lead times for producing a new lead frame configuration via etching or other processes also can be substantial.
  • the present disclosure sets forth a method of making lead frames that utilizes nearly all of the conductor material (incoming raw material for the lead frame conductor structures) and produces lead frames with conductor structures (and/or other types of structures) having a spacing of less than one conductive layer thickness.
  • the method of the present disclosure also affords rapid generation of new lead frame configurations without the need to retool and can result in reduced manufacturer lead times.
  • preformed die attach pads and preformed leads are arranged on a lead frame carrier to form at least one lead frame.
  • a semiconductor die is then mounted to the die attach pad, wire bonded to the leads, molded and singulated to produce a semiconductor package.
  • Disclosed example methods include singulating a plurality of conductive structures from a sheet of conductive material, arranging the plurality of singulated conductive structures on a lead frame carrier in a predetermined configuration, and arranging at least one die attach pad on the lead frame carrier to form at least one lead frame having the at least one die attach pad and a plurality of leads spaced apart from the at least one die attach pad.
  • the conductive structures include a first group of conductive structures having a first metal composition, size, shape or thickness and a second group of conductive structures having a second metal composition, size, shape, or thickness
  • the arranging the plurality of structures on a lead frame carrier in a predetermined configuration to form at least one lead frame includes using at least one conductive structure from each group in the at least one lead frame.
  • the arranging the plurality of singulated conductive structures on a lead frame carrier can include using a stencil, wherein the stencil includes openings in locations corresponding to the predetermined configuration, and wherein the stencil is applied over the lead frame carrier and the singulated conductive structures are placed on the lead frame carrier through the openings in the stencil.
  • pick-and-place machinery is used to arrange preformed die attach pads and preformed leads on the lead frame carrier.
  • Another example method of making a semiconductor die package comprises arranging at least one preformed die attach pad and at least two preformed leads on a lead frame carrier in a predetermined configuration to form a lead frame, attaching a semiconductor die to the at least one preformed die attach pad, wire bonding the semiconductor die to the at least two preformed leads, forming a molding structure including at least part of the semiconductor die and the at least two preformed leads, and removing the molding structure from the lead frame carrier.
  • Still another example method of making a semiconductor die package comprises singulating a plurality of conductive structures from one or more sheets of conductive material, the conductive structures including at least one die attach pad and at least one lead, arranging the at least one die attach pad and at least one lead on a lead frame carrier in a predetermined configuration to form at least one lead frame, attaching a semiconductor die to the at least one die attach pad, wire bonding the semiconductor die to the at least one lead frame, applying molding over the semiconductor die and lead frame, and removing the molded semiconductor die and lead frame from the lead frame carrier.
  • FIG. 1 is a flow diagram showing an example method of fabricating semiconductor chip package according to one embodiment
  • FIG. 2 is a perspective view of a plurality of die attach pads and leads singulated from a sheet of material in accordance with the method of FIG. 1 ;
  • FIG. 3 is a perspective view of an example lead and die attach pad having a mold-lock feature formed during a singulation step of the method of FIG. 1 ;
  • FIG. 4 is a flow diagram illustrating one example alternative for arranging preformed structures on a lead frame carrier in the arranging step of the method of FIG. 1 ;
  • FIG. 5 is a perspective view of the implementation of the example method of FIG. 4 ;
  • FIG. 6 is a flow diagram illustrating another example alternative for arranging preformed structures on a lead frame carrier in the arranging step of FIG. 1 ;
  • FIG. 7 a perspective view of the implementation of the example method of FIG. 6 ;
  • FIG. 8 is a perspective view illustrating the singulation of a die package with lead frame from a molded strip of die packages in accordance with the present disclosure.
  • the example semiconductor die package in the illustrated embodiment is a quad flat no-lead package (QFN package), but aspects of the present disclosure are applicable to other types of packages.
  • QFN package quad flat no-lead package
  • the method begins with process step 112 , where a sheet of conductive material is obtained.
  • the conductive material can be, for example, copper, aluminum, or any other suitable conductive material.
  • the sheet of conductive material includes a copper layer pre-plated with NiPdAu.
  • the sheet of material can be pre-plated with any desired plating material or plating stack of materials to ensure proper bonding of components during downstream processing.
  • the sheet of material can optionally be plated with various other conductive metals (e.g., NiPdAu), for example, and/or roughened or undergo chemical surface treatment to enhance mold adhesion in later processing steps.
  • individual conductor structures are singulated from the sheet of material.
  • the individual conductor structures can be, for example, preformed die attach pads and/or preformed leads. Singulation of the individual structures can be performed in any suitable manner such as by sawing, etching, laser cutting, or other singulation processes. As will be appreciated, singulation of preformed die attach pads and/or leads from a sheet of material generally facilitates almost 100% utilization of the sheet of material. Further, and as will be described in more detail in connection with FIG. 3 , the singulation step or steps can be used to mill or otherwise create a mold-lock feature, such as a stepped edge or other profile, to enhance integration when the lead frame is molded over.
  • a mold-lock feature such as a stepped edge or other profile
  • a lead frame generally includes at least one die attach pad and a plurality of leads arranged in proximity to the die attach pad.
  • aspects of the present disclosure can be used to make a variety of structures in addition to lead frames, and the method of the present disclosure is, therefore, not limited to any particular lead frame (or other) structure.
  • positioning of the singulated structures can be performed in a number of ways, such as with pick-and-place machinery and/or through the use of stencils. It will further be appreciated that in one embodiment, the singulated structures are secured to the lead frame carrier with an adhesive tape layer or the like that maintains the singulated structures in position for subsequent processing steps. In addition, aspects of the present disclosure can be applied to generate a wide range of lead frame configurations.
  • process step 120 semiconductor dies are attached to the die attach pads of each lead frame in an otherwise conventional approach.
  • the semiconductor dies are then wirebonded to the leads of each respective lead frame in process step 122 .
  • a molding structure is then formed over at least portions of the dies, die pads, leads etc. in process step 124 . After the molding structure is formed, the molding structure is separated from the lead frame carrier and singulated (such as by sawing, for example) in process step 126 to generate individual semiconductor packages.
  • the sheet 210 can be a sheet of conductive material such as copper or the like. As noted above in connection with process step 114 , the sheet 210 can have various plating layers formed thereon and/or can be roughened or otherwise processed (e.g., chemical surface treatment) to enhance mold adhesion in later processing steps. In accordance with process step 116 , the sheet 210 can be separated into a plurality of individual structures, such as a plurality of leads 212 (individual leads identified by reference numeral 214 ) and/or a plurality of die attach pads 216 (individual die attach pads identified by reference numeral 218 ).
  • a plurality of leads 212 individual leads identified by reference numeral 214
  • die attach pads 216 individual die attach pads identified by reference numeral 218
  • the leads 214 and die attach pads 218 can be made of a common material and/or singulated from a common sheet of material. In other embodiments, the leads 214 and die attach pads 218 can be made of different materials and/or singulated from different sheets of material. In either case, once singulated from a sheet of material, the individual structures in the illustrated example comprise preformed die attach pads and/or preformed leads.
  • the mold-lock features can include a lead 314 or die attach pad 318 with one or more stepped edges 316 and 320 , respectively.
  • the stepped edges provide additional structure and/or surface contour for integration of the preformed lead and/or die-attach pad with the molding structure.
  • extra material can be removed from the edge regions of the structures before, during or after separation from the sheet of material.
  • a trench is formed at least partially through the sheet of material and the individual structure is separated from the sheet of material in a location within the trench.
  • the structures are arranged on a lead frame carrier in a predetermined configuration to form lead frames, each having a die attach pad and a plurality of leads spaced apart from the die attach pad and each other.
  • process step 118 is the step wherein the singulated structures are arranged or otherwise placed on a lead frame carrier in a predetermined configuration to generate a plurality of lead frames.
  • FIG. 4 illustrates one example method 418 of carrying out process step 118 using pick-and-place machinery for arranging the singulated structures on a lead frame carrier.
  • Method 418 includes process steps 422 and 424 wherein a preformed die attach pad is picked up and then placed on the lead frame carrier. In process steps 426 and 428 , a lead is picked up and placed on the lead frame carrier. The method 418 continues to decision box 430 , whereat the method reverts to process step 422 until the lead frame carrier is complete (e.g., all lead frames have been formed), at which time the method 418 continues to process step 120 in FIG. 1 .
  • method 418 can include picking and placing multiple die attach pads on the lead frame carrier, and picking and placing a plurality of preformed leads in proximity to each die attach pad to thereby form a plurality of lead frames on the lead frame carrier.
  • each lead frame is assembled in full before the next lead frame is assembled.
  • several or all of the die attach pads are picked and placed on the lead frame carrier and, subsequently, the preformed leads are then picked and placed in proximity to each die attach pad to complete each of the lead frames.
  • the preformed leads for some or all of the lead frames are picked and placed on the lead frame carrier and then the die attach pads are picked and placed to complete the lead frames.
  • any suitable sequence of picking and placing the die attach pads and leads can be used.
  • FIG. 5 illustrates an example arrangement wherein a pick and-place machine 510 is used to arrange the plurality of leads 212 and plurality of die attach pads 216 in a predetermined configuration on lead frame carrier 514 to form a plurality of lead frames 518 . It should be appreciated that a tape or other layer 522 is provided for temporarily securing the leads 214 and die attach pads 218 to the lead frame carrier 514 after being positioned thereon.
  • FIGS. 6 and 7 another example method 618 for carrying out process step 118 of FIG. 1 is illustrated.
  • two stencils are used in succession for positioning the individual structures of each lead frame on the lead frame substrate.
  • a first stencil is positioned on the lead frame carrier.
  • the preformed leads or die attach pads, as the case may be) are deposited onto the lead frame carrier though the openings in the first stencil.
  • a second stencil is positioned on the lead frame carrier.
  • the preformed die attach pads (or leads, as the case may be) are deposited onto the lead frame carrier though the openings in the second stencil in the same manner as described above. Then, the method 618 reverts to process step 120 of FIG. 1 .
  • FIG. 7 schematically illustrates an alternative embodiment of process 618 where only one stencil 710 is illustrated.
  • Stencil 710 includes a plurality of first openings 714 for receiving die attach pads 218 and a plurality of second openings 718 for receiving leads 214 . It will be appreciated that the die attach pads 218 and leads 214 can be guided into the respective openings in the stencil or stencils using any suitable method, such as vibration or the like, for example.
  • each lead frame 518 has a die 806 attached to its respective die attach pad 218 and wirebonded to leads 214 .
  • a molding structure 810 has been formed over the assemblies.
  • the final step to forming a die package 816 is singulation of each die package from the molded strip of die packages.
  • tape 522 is peeled off both the lead frame carrier 514 and the molded structure 810 thereby separating the molded structure 810 from the carrier 514 .
  • the individual die packages are then singulated along singulation ones 832 into a plurality of individual die packages via sawing or any other suitable method.
  • aspects of the present disclosure not only facilitate closer lead spacing than generally achievable using etching or stamping processes, but can also facilitate producing lead frames having a relatively higher power capacity by allowing for the use of die attach pads that are thicker than the leads. Thicker die attach pads can result in improved thermal characteristics for a given lead frame.
  • Other lead frame construction approaches for example etching approaches, have die attach pads and leads of the same thickness.
  • etching processes have an upper limit to the thickness of the base material.
  • the present disclosure can be used to produce lead frames having die attach pads of a wider range of thicknesses and of thicknesses different from that of the leads.
  • different materials can be used for the die attach pads and the leads. All of these features result in a level of lead frame customization not generally available through prior approaches.
  • aspects of the present disclosure are also well-suited to rapid production of new lead frame configurations. Unlike other approaches, the present disclosure does not require the production of any special tooling for producing new lead frame configurations. It will be appreciated that current pick-and-place machinery can be used to produce lead frames of a wide range of configurations without the need to first generate special tooling, such as stamping or etching tools. Current pick-and-place machine capabilities allow for placement at +/ ⁇ 10 microns and ratios less than about 2%. Of course, aspects of the present disclosure are applicable to pick-and-place methods of any accuracy. Similarly, the stencils referred to above can generally be produced more quickly than other specialized tooling that would otherwise be used. This allows new configurations of lead frames to be produced much more quickly than some other approaches.
  • aspects of the present disclosure are well-suited to producing lead frames having a variety of configurations including, but not limited to: a split die attach pad (lead frame with multiple die attach pads and/or die attach pads of different respective materials), different base materials (lead frame with die attach pad of a material different than the leads), thicker die pad (lead frame having a die pad that is thicker than the leads), closely spaced leads (lead frame having leads with horizontal spacing less than one thickness of lead material), integrated passive components with smaller line/spacing (lead frame with passive components mounted adjacent chip on circuit board), fused lead (lead frame with two or more leads fused together), chip on lead (lead frame with chip mounted directly on leads), dual/multiple rows of leads (lead frame having two or more rows of leads, rows may have different heights or thicknesses), flip-chip on lead (lead frame having chip soldered to leads), non-conductive die attach pad (PCB and/or substrate with embedded chip).
  • a split die attach pad lead frame with

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Ceramic Engineering (AREA)

Abstract

Disclosed examples include a method of making a semiconductor die package comprising arranging at least one preformed die attach pad and at least two preformed leads on a lead frame carrier in a predetermined configuration to form a lead frame, attaching a semiconductor die to the at least one preformed die attach pad, wire bonding the semiconductor die to the at least two preformed leads, forming a molding structure including at least part of the semiconductor die and the at least two preformed leads, and removing the molding structure from the lead frame carrier.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a Continuation of and claims priority to U.S. application Ser. No. 15/452,026 filed Mar. 7, 2017, the contents of which is herein incorporated by reference.
    • BACKGROUND
  • Integrated circuit devices generally include an integrated circuit chip and a lead frame which are sealed within a protective enclosure, find wide use in various products, among which are consumer electronics, computers, automobiles, telecommunications and military applications. The lead frame electrically interconnects the integrated circuit chip to circuitry external to the device. The lead frame is typically formed from a highly electrically and thermally conductive material, such as copper or copper alloys. The lead frame material is stamped or etched into a plurality of leads, and a central area, called a die attach pad, onto which the integrated circuit chip is attached. The chip is electrically connected to the leads, usually by wire bonding, and the device is encapsulated to provide mechanical and environmental protection.
  • Conventional lead frames for integrated circuit packages are typically made using metal etching processes to create die attach pads and leads from a conductive layer of material on a bulk substrate or other material. Such process involves etching the conductive layer of material to form discrete conductor structures (e.g., the die attach pads and the leads). The etching process typically limits the spacing between the die attach pads and/or between adjacent leads on these conventional lead frames to at least one thickness of the conductive layer of material due to physical limitations of etching technology. In addition, the portions of the conductive layer removed from the substrate during the etching process generate waste in the manufacturing process. Manufacturer lead times for producing a new lead frame configuration via etching or other processes also can be substantial.
    • SUMMARY
  • The present disclosure sets forth a method of making lead frames that utilizes nearly all of the conductor material (incoming raw material for the lead frame conductor structures) and produces lead frames with conductor structures (and/or other types of structures) having a spacing of less than one conductive layer thickness. The method of the present disclosure also affords rapid generation of new lead frame configurations without the need to retool and can result in reduced manufacturer lead times. In one embodiment, preformed die attach pads and preformed leads are arranged on a lead frame carrier to form at least one lead frame. A semiconductor die is then mounted to the die attach pad, wire bonded to the leads, molded and singulated to produce a semiconductor package.
  • Disclosed example methods include singulating a plurality of conductive structures from a sheet of conductive material, arranging the plurality of singulated conductive structures on a lead frame carrier in a predetermined configuration, and arranging at least one die attach pad on the lead frame carrier to form at least one lead frame having the at least one die attach pad and a plurality of leads spaced apart from the at least one die attach pad. In one example, the conductive structures include a first group of conductive structures having a first metal composition, size, shape or thickness and a second group of conductive structures having a second metal composition, size, shape, or thickness, and the arranging the plurality of structures on a lead frame carrier in a predetermined configuration to form at least one lead frame includes using at least one conductive structure from each group in the at least one lead frame. The arranging the plurality of singulated conductive structures on a lead frame carrier can include using a stencil, wherein the stencil includes openings in locations corresponding to the predetermined configuration, and wherein the stencil is applied over the lead frame carrier and the singulated conductive structures are placed on the lead frame carrier through the openings in the stencil. In another example, pick-and-place machinery is used to arrange preformed die attach pads and preformed leads on the lead frame carrier.
  • Another example method of making a semiconductor die package comprises arranging at least one preformed die attach pad and at least two preformed leads on a lead frame carrier in a predetermined configuration to form a lead frame, attaching a semiconductor die to the at least one preformed die attach pad, wire bonding the semiconductor die to the at least two preformed leads, forming a molding structure including at least part of the semiconductor die and the at least two preformed leads, and removing the molding structure from the lead frame carrier.
  • Still another example method of making a semiconductor die package comprises singulating a plurality of conductive structures from one or more sheets of conductive material, the conductive structures including at least one die attach pad and at least one lead, arranging the at least one die attach pad and at least one lead on a lead frame carrier in a predetermined configuration to form at least one lead frame, attaching a semiconductor die to the at least one die attach pad, wire bonding the semiconductor die to the at least one lead frame, applying molding over the semiconductor die and lead frame, and removing the molded semiconductor die and lead frame from the lead frame carrier.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a flow diagram showing an example method of fabricating semiconductor chip package according to one embodiment;
  • FIG. 2 is a perspective view of a plurality of die attach pads and leads singulated from a sheet of material in accordance with the method of FIG. 1;
  • FIG. 3 is a perspective view of an example lead and die attach pad having a mold-lock feature formed during a singulation step of the method of FIG. 1;
  • FIG. 4 is a flow diagram illustrating one example alternative for arranging preformed structures on a lead frame carrier in the arranging step of the method of FIG. 1;
  • FIG. 5 is a perspective view of the implementation of the example method of FIG. 4;
  • FIG. 6 is a flow diagram illustrating another example alternative for arranging preformed structures on a lead frame carrier in the arranging step of FIG. 1;
  • FIG. 7 a perspective view of the implementation of the example method of FIG. 6; and
  • FIG. 8 is a perspective view illustrating the singulation of a die package with lead frame from a molded strip of die packages in accordance with the present disclosure.
    •  DETAILED DESCRIPTION
  • In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the following discussion and in the claims, the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are intended to be inclusive in a manner similar to the term “comprising”, and thus should be interpreted to mean Including, but not limited to. Also, the term “couple” or “couples” is intended to include indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or is coupled with a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and connections.
  • Referring initially to FIG. 1, an example method 100 for making a semiconductor die package in accordance with the present disclosure is illustrated. The example semiconductor die package in the illustrated embodiment is a quad flat no-lead package (QFN package), but aspects of the present disclosure are applicable to other types of packages.
  • The method begins with process step 112, where a sheet of conductive material is obtained. The conductive material can be, for example, copper, aluminum, or any other suitable conductive material. In one example, the sheet of conductive material includes a copper layer pre-plated with NiPdAu. As will be appreciated, the sheet of material can be pre-plated with any desired plating material or plating stack of materials to ensure proper bonding of components during downstream processing. In addition, in process step 114 the sheet of material can optionally be plated with various other conductive metals (e.g., NiPdAu), for example, and/or roughened or undergo chemical surface treatment to enhance mold adhesion in later processing steps.
  • In process step 116, individual conductor structures are singulated from the sheet of material. The individual conductor structures can be, for example, preformed die attach pads and/or preformed leads. Singulation of the individual structures can be performed in any suitable manner such as by sawing, etching, laser cutting, or other singulation processes. As will be appreciated, singulation of preformed die attach pads and/or leads from a sheet of material generally facilitates almost 100% utilization of the sheet of material. Further, and as will be described in more detail in connection with FIG. 3, the singulation step or steps can be used to mill or otherwise create a mold-lock feature, such as a stepped edge or other profile, to enhance integration when the lead frame is molded over.
  • In process step 118, the singulated conductor structures are arranged or otherwise placed on a lead frame carrier in a predetermined configuration to generate a plurality of lead frames. In this description, a lead frame generally includes at least one die attach pad and a plurality of leads arranged in proximity to the die attach pad. Of course, aspects of the present disclosure can be used to make a variety of structures in addition to lead frames, and the method of the present disclosure is, therefore, not limited to any particular lead frame (or other) structure.
  • As will be described in more detail below, positioning of the singulated structures can be performed in a number of ways, such as with pick-and-place machinery and/or through the use of stencils. It will further be appreciated that in one embodiment, the singulated structures are secured to the lead frame carrier with an adhesive tape layer or the like that maintains the singulated structures in position for subsequent processing steps. In addition, aspects of the present disclosure can be applied to generate a wide range of lead frame configurations.
  • In process step 120, semiconductor dies are attached to the die attach pads of each lead frame in an otherwise conventional approach. The semiconductor dies are then wirebonded to the leads of each respective lead frame in process step 122. A molding structure is then formed over at least portions of the dies, die pads, leads etc. in process step 124. After the molding structure is formed, the molding structure is separated from the lead frame carrier and singulated (such as by sawing, for example) in process step 126 to generate individual semiconductor packages.
  • Turning to FIG. 2, an example sheet of material 210 is illustrated. The sheet 210 can be a sheet of conductive material such as copper or the like. As noted above in connection with process step 114, the sheet 210 can have various plating layers formed thereon and/or can be roughened or otherwise processed (e.g., chemical surface treatment) to enhance mold adhesion in later processing steps. In accordance with process step 116, the sheet 210 can be separated into a plurality of individual structures, such as a plurality of leads 212 (individual leads identified by reference numeral 214) and/or a plurality of die attach pads 216 (individual die attach pads identified by reference numeral 218). In some embodiments, the leads 214 and die attach pads 218 can be made of a common material and/or singulated from a common sheet of material. In other embodiments, the leads 214 and die attach pads 218 can be made of different materials and/or singulated from different sheets of material. In either case, once singulated from a sheet of material, the individual structures in the illustrated example comprise preformed die attach pads and/or preformed leads.
  • With reference to FIG. 3, it will be appreciated that certain mold-lock features can be formed in the singulated structures during the singulation process. In one embodiment, the mold-lock features can include a lead 314 or die attach pad 318 with one or more stepped edges 316 and 320, respectively. The stepped edges provide additional structure and/or surface contour for integration of the preformed lead and/or die-attach pad with the molding structure. To this end, during singulation of the individual structures from the sheet(s) of material, extra material can be removed from the edge regions of the structures before, during or after separation from the sheet of material. In one embodiment, a trench is formed at least partially through the sheet of material and the individual structure is separated from the sheet of material in a location within the trench. This approach produces the stepped edge profile shown on the lead 314 and die 318 in FIG. 3. Other edge shape profiles are also possible, such as beveled or dovetailed, for example. As noted above, regardless of the manner in which the preformed leads and/or die attach pads are formed and/or otherwise obtained, the structures are arranged on a lead frame carrier in a predetermined configuration to form lead frames, each having a die attach pad and a plurality of leads spaced apart from the die attach pad and each other.
  • Referring back to FIG. 1, and with further reference to FIGS. 4 and 5, process step 118 is the step wherein the singulated structures are arranged or otherwise placed on a lead frame carrier in a predetermined configuration to generate a plurality of lead frames. FIG. 4 illustrates one example method 418 of carrying out process step 118 using pick-and-place machinery for arranging the singulated structures on a lead frame carrier.
  • Method 418 includes process steps 422 and 424 wherein a preformed die attach pad is picked up and then placed on the lead frame carrier. In process steps 426 and 428, a lead is picked up and placed on the lead frame carrier. The method 418 continues to decision box 430, whereat the method reverts to process step 422 until the lead frame carrier is complete (e.g., all lead frames have been formed), at which time the method 418 continues to process step 120 in FIG. 1. Thus, method 418 can include picking and placing multiple die attach pads on the lead frame carrier, and picking and placing a plurality of preformed leads in proximity to each die attach pad to thereby form a plurality of lead frames on the lead frame carrier.
  • In one example, each lead frame is assembled in full before the next lead frame is assembled. In another example, several or all of the die attach pads are picked and placed on the lead frame carrier and, subsequently, the preformed leads are then picked and placed in proximity to each die attach pad to complete each of the lead frames. In still other examples, the preformed leads for some or all of the lead frames are picked and placed on the lead frame carrier and then the die attach pads are picked and placed to complete the lead frames. Of course, any suitable sequence of picking and placing the die attach pads and leads can be used.
  • FIG. 5 illustrates an example arrangement wherein a pick and-place machine 510 is used to arrange the plurality of leads 212 and plurality of die attach pads 216 in a predetermined configuration on lead frame carrier 514 to form a plurality of lead frames 518. It should be appreciated that a tape or other layer 522 is provided for temporarily securing the leads 214 and die attach pads 218 to the lead frame carrier 514 after being positioned thereon.
  • Turning to FIGS. 6 and 7, another example method 618 for carrying out process step 118 of FIG. 1 is illustrated. In this method, two stencils are used in succession for positioning the individual structures of each lead frame on the lead frame substrate. Accordingly, in process step 622 a first stencil is positioned on the lead frame carrier. In process step 624, the preformed leads (or die attach pads, as the case may be) are deposited onto the lead frame carrier though the openings in the first stencil.
  • In process step 626, a second stencil is positioned on the lead frame carrier. In process step 628, the preformed die attach pads (or leads, as the case may be) are deposited onto the lead frame carrier though the openings in the second stencil in the same manner as described above. Then, the method 618 reverts to process step 120 of FIG. 1.
  • FIG. 7 schematically illustrates an alternative embodiment of process 618 where only one stencil 710 is illustrated. Stencil 710 includes a plurality of first openings 714 for receiving die attach pads 218 and a plurality of second openings 718 for receiving leads 214. It will be appreciated that the die attach pads 218 and leads 214 can be guided into the respective openings in the stencil or stencils using any suitable method, such as vibration or the like, for example.
  • Turning to FIG. 8, the lead frame carrier 614 with a plurality of lead frames 518 is illustrated after process steps 120, 122, and 124 of FIG. 1. As such, each lead frame 518 has a die 806 attached to its respective die attach pad 218 and wirebonded to leads 214. A molding structure 810 has been formed over the assemblies. As will be appreciated, the final step to forming a die package 816 is singulation of each die package from the molded strip of die packages. To this end, tape 522 is peeled off both the lead frame carrier 514 and the molded structure 810 thereby separating the molded structure 810 from the carrier 514. The individual die packages are then singulated along singulation ones 832 into a plurality of individual die packages via sawing or any other suitable method.
  • It should be appreciated that aspects of the present disclosure not only facilitate closer lead spacing than generally achievable using etching or stamping processes, but can also facilitate producing lead frames having a relatively higher power capacity by allowing for the use of die attach pads that are thicker than the leads. Thicker die attach pads can result in improved thermal characteristics for a given lead frame. Other lead frame construction approaches, for example etching approaches, have die attach pads and leads of the same thickness. In addition, etching processes have an upper limit to the thickness of the base material. The present disclosure can be used to produce lead frames having die attach pads of a wider range of thicknesses and of thicknesses different from that of the leads. Moreover, and as previously noted, different materials can be used for the die attach pads and the leads. All of these features result in a level of lead frame customization not generally available through prior approaches.
  • Aspects of the present disclosure are also well-suited to rapid production of new lead frame configurations. Unlike other approaches, the present disclosure does not require the production of any special tooling for producing new lead frame configurations. It will be appreciated that current pick-and-place machinery can be used to produce lead frames of a wide range of configurations without the need to first generate special tooling, such as stamping or etching tools. Current pick-and-place machine capabilities allow for placement at +/−10 microns and ratios less than about 2%. Of course, aspects of the present disclosure are applicable to pick-and-place methods of any accuracy. Similarly, the stencils referred to above can generally be produced more quickly than other specialized tooling that would otherwise be used. This allows new configurations of lead frames to be produced much more quickly than some other approaches.
  • It should also be appreciated that aspects of the present disclosure are well-suited to producing lead frames having a variety of configurations including, but not limited to: a split die attach pad (lead frame with multiple die attach pads and/or die attach pads of different respective materials), different base materials (lead frame with die attach pad of a material different than the leads), thicker die pad (lead frame having a die pad that is thicker than the leads), closely spaced leads (lead frame having leads with horizontal spacing less than one thickness of lead material), integrated passive components with smaller line/spacing (lead frame with passive components mounted adjacent chip on circuit board), fused lead (lead frame with two or more leads fused together), chip on lead (lead frame with chip mounted directly on leads), dual/multiple rows of leads (lead frame having two or more rows of leads, rows may have different heights or thicknesses), flip-chip on lead (lead frame having chip soldered to leads), non-conductive die attach pad (PCB and/or substrate with embedded chip).
  • The above examples are merely illustrative of several possible embodiments of various aspects of the present disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon reading and understanding this specification and the annexed drawings. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims (20)

1-20. (canceled)
21. A method of making a leadframe comprising:
singulating a plurality of conductor structures from a sheet of conductive material;
forming a plurality of leads by arranging the plurality of singulated conductor structures on a lead frame carrier in a predetermined configuration; and
arranging at least one die attach pad on the lead frame carrier to form at least one lead frame having the at least one die attach pad and the plurality of leads spaced apart from the at least one die attach pad, the at least one die attach pad having no protrusion of the conductive material from any corner.
22. The method of claim 21, wherein the arranging the plurality of singulated conductor structures on a lead frame carrier includes using a pick-and-place robot to position individual conductor structures on the lead frame carrier.
23. The method of claim 22, wherein the conductor structures include a first group of conductor structures having a first metal composition, size, shape or thickness and a second group of conductor structures having a second metal composition, size, shape, or thickness, and the arranging the plurality of singulated conductor structures on a lead frame carrier in a predetermined configuration to form at least one lead frame includes using at least one conductor structure from each group in the at least one lead frame.
24. The method of claim 21, wherein the arranging the plurality of singulated conductor structures on a lead frame carrier includes using a stencil, wherein the stencil includes openings in locations corresponding to the predetermined configuration, and wherein the stencil is applied over the lead frame carrier and the singulated conductor structures are placed on the lead frame carrier through the openings in the stencil.
25. The method of claim 24, wherein the conductor structures include the at least one die attach pad and at least one lead, the at least one die attach pad being larger than the at least one lead, the method further comprising using a first stencil for arranging the at least one die pad on the lead frame carrier and, subsequently, using a second stencil for arranging the at least one lead on the lead frame carrier.
26. The method of claim 21, further comprising securing the conductor structures to the lead frame carrier with an adhesive tape interposed between the conductor structures and the lead frame carrier.
27. The method of claim 21, wherein the singulating a plurality of conductor structures from a sheet of conductive material includes forming a mold-lock feature on the individual conductor structures.
28. The method of claim 27, wherein forming the mold-lock feature includes forming a stepped edge formed by forming a trench in the sheet of material having a first width, and severing the sheet of material at a position within the trench to generate the stepped edge.
29. A method of making a semiconductor die package comprising:
arranging at least one preformed die attach pad and at least two preformed leads on a lead frame carrier in a predetermined configuration to form a lead frame, the at least one preformed die attach pad having no protrusion from any corner;
attaching a semiconductor die to the at least one preformed die attach pad;
wire bonding the semiconductor die to the at least two preformed leads;
forming a molding structure including at least part of the semiconductor die and the at least two preformed leads;
removing the molding structure from the lead frame carrier.
30. The method of claim 29, wherein the preformed die attach pad includes a PCB.
31. The method of claim 29, wherein the at least two preformed leads include a first group of preformed leads in the form of conductor structures having a first metal composition, size, shape or thickness, and a second group of preformed leads in the form of conductor structures having a second metal composition, size, shape, or thickness, and wherein the arranging the at least two preformed leads on a lead frame carrier in a predetermined configuration to form a lead frame includes using at least one conductor structure from each group in the lead frame.
32. The method of claim 29, wherein the arranging at least one preformed die attach pad and at least two preformed leads on a lead frame carrier in a predetermined configuration to form a lead frame includes using a pick-and-place robot.
33. The method of claim 29, wherein the arranging the at least one preformed die attach pad and at least two preformed leads includes using a stencil, wherein the stencil includes openings in locations corresponding to the predetermined configuration, and wherein the stencil is applied over the lead frame carrier and the at least one preformed die attach pad and at least two preformed leads are placed on the lead frame carrier through the openings in the stencil.
34. The method of claim 33, wherein the at least one preformed die attach pad is larger in areal size than the at least two preformed leads, the method further comprising using a first stencil for arranging the at least one preformed die attach pad on the lead frame carrier and, subsequently, using a second stencil to arrange the at least two preformed leads on the lead frame carrier.
35. The method of claim 29, further comprising securing the at least one preformed die attach pad and at least two preformed leads to the lead frame carrier with an adhesive tape interposed therebetween.
36. The method of claim 29, further comprising forming at least one of the at least one preformed die attach pad and the at least two preformed leads by singulating a conductor structure from a sheet of conductive material.
37. The method of claim 29, further comprising wire bonding the semiconductor die to the at least two preformed leads, applying molding over at least a portion of the semiconductor die and lead frame, and removing the molded semiconductor die and lead frame from the lead frame carrier.
38. A method of making a semiconductor die package comprising:
singulating a plurality of conductor structures from one or more sheets of conductive material, the conductor structures including at least one die attach pad and at least one lead, the at least one die attach pad having no protrusion of the conductive material from any corner;
arranging the at least one die attach pad and the at least one lead on a lead frame carrier in a predetermined configuration to form at least one lead frame;
wire bonding a semiconductor die associated with the die attach pad to the at least one lead frame;
applying molding over the semiconductor die and at least one lead; and
removing the molded semiconductor die and lead frame from the lead frame carrier.
39. The method of claim 38, wherein the at least one die attach pad and at least one lead are singulated from sheets of different materials, whereby the at least one lead frame has a die attach pad that is a different material than at least one leads.
US15/955,435 2017-03-07 2018-04-17 Method for making lead frames for integrated circuit packages Active US10079162B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/955,435 US10079162B1 (en) 2017-03-07 2018-04-17 Method for making lead frames for integrated circuit packages

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/452,026 US9978613B1 (en) 2017-03-07 2017-03-07 Method for making lead frames for integrated circuit packages
US15/955,435 US10079162B1 (en) 2017-03-07 2018-04-17 Method for making lead frames for integrated circuit packages

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US15/452,026 Continuation US9978613B1 (en) 2017-03-07 2017-03-07 Method for making lead frames for integrated circuit packages

Publications (2)

Publication Number Publication Date
US20180261469A1 true US20180261469A1 (en) 2018-09-13
US10079162B1 US10079162B1 (en) 2018-09-18

Family

ID=62122165

Family Applications (2)

Application Number Title Priority Date Filing Date
US15/452,026 Active US9978613B1 (en) 2017-03-07 2017-03-07 Method for making lead frames for integrated circuit packages
US15/955,435 Active US10079162B1 (en) 2017-03-07 2018-04-17 Method for making lead frames for integrated circuit packages

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US15/452,026 Active US9978613B1 (en) 2017-03-07 2017-03-07 Method for making lead frames for integrated circuit packages

Country Status (3)

Country Link
US (2) US9978613B1 (en)
CN (1) CN110383471B (en)
WO (1) WO2018165234A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111162016A (en) * 2019-12-27 2020-05-15 长电科技（宿迁）有限公司 Packaging method for temporary bonding reinforcement of lead frame

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6740961B1 (en) * 2000-06-09 2004-05-25 National Semiconductor Corporation Lead frame design for chip scale package
US6794224B2 (en) * 2000-08-31 2004-09-21 Micron Technology, Inc. Semiconductor device including leads in communication with contact pads thereof and a stereolithographically fabricated package substantially encapsulating the leads and methods for fabricating the same
US20140070391A1 (en) * 2012-09-07 2014-03-13 Eoplex Limited Lead carrier with print-formed terminal pads

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4012765A (en) * 1975-09-24 1977-03-15 Motorola, Inc. Lead frame for plastic encapsulated semiconductor assemblies
US4346396A (en) * 1979-03-12 1982-08-24 Western Electric Co., Inc. Electronic device assembly and methods of making same
US5070602A (en) * 1988-04-12 1991-12-10 Lance R. Kaufman Method of making a circuit assembly
KR930024126A (en) * 1992-05-12 1993-12-22 아키라 기타하라 Surface Mount Devices and Their Semifinished Products
KR960006970B1 (en) * 1993-05-03 1996-05-25 삼성전자주식회사 Film carrier and the manufacturing method
TW359880B (en) * 1995-08-30 1999-06-01 Samsung Electronics Co Ltd Method of manufacturing semiconductor chip package
KR0185512B1 (en) * 1996-08-19 1999-03-20 김광호 Column lead type package and method of making the same
JPH1168006A (en) * 1997-08-19 1999-03-09 Mitsubishi Electric Corp Lead frame, semiconductor device provided therewith, and manufacture of them
US6130473A (en) * 1998-04-02 2000-10-10 National Semiconductor Corporation Lead frame chip scale package
US8330270B1 (en) * 1998-06-10 2012-12-11 Utac Hong Kong Limited Integrated circuit package having a plurality of spaced apart pad portions
US6247229B1 (en) * 1999-08-25 2001-06-19 Ankor Technology, Inc. Method of forming an integrated circuit device package using a plastic tape as a base
JP2002076040A (en) * 2000-08-30 2002-03-15 Hitachi Ltd Semiconductor device and manufacturing method thereof
US6664615B1 (en) * 2001-11-20 2003-12-16 National Semiconductor Corporation Method and apparatus for lead-frame based grid array IC packaging
JP4093826B2 (en) 2002-08-27 2008-06-04 富士通株式会社 Clock generator
US20040058478A1 (en) * 2002-09-25 2004-03-25 Shafidul Islam Taped lead frames and methods of making and using the same in semiconductor packaging
US7144517B1 (en) * 2003-11-07 2006-12-05 Amkor Technology, Inc. Manufacturing method for leadframe and for semiconductor package using the leadframe
TWI235440B (en) * 2004-03-31 2005-07-01 Advanced Semiconductor Eng Method for making leadless semiconductor package
TWI244731B (en) * 2004-05-31 2005-12-01 Advanced Semiconductor Eng Method for improving balance of molding flow during assembling semiconductor packages with fail unit
TWI247367B (en) * 2004-12-02 2006-01-11 Siliconware Precision Industries Co Ltd Semiconductor package free of carrier and fabrication method thereof
US20060197199A1 (en) * 2005-03-05 2006-09-07 Lange Bernhard P Leadframe, coining tool, and method
US7160755B2 (en) * 2005-04-18 2007-01-09 Freescale Semiconductor, Inc. Method of forming a substrateless semiconductor package
US7910406B2 (en) * 2005-11-02 2011-03-22 Panasonic Corporation Electronic circuit device and method for manufacturing same
US8492906B2 (en) * 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US8487451B2 (en) * 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8217281B2 (en) * 2007-04-10 2012-07-10 Nxp B.V. Package, method of manufacturing a package and frame
CN101312177A (en) * 2007-05-22 2008-11-26 飞思卡尔半导体（中国）有限公司 Lead frame for semiconductor device
US8035221B2 (en) * 2007-11-08 2011-10-11 Intersil Americas, Inc. Clip mount for integrated circuit leadframes
US7582954B1 (en) 2008-02-25 2009-09-01 National Semiconductor Corporation Optical leadless leadframe package
TWI378515B (en) * 2008-11-07 2012-12-01 Chipmos Technoligies Inc Method of fabricating quad flat non-leaded package
KR101169686B1 (en) * 2008-11-07 2012-08-06 에스케이하이닉스 주식회사 Substrate for semicondouctor package and methode thereof
US8723299B2 (en) * 2010-06-01 2014-05-13 Infineon Technologies Ag Method and system for forming a thin semiconductor device
CN102683221B (en) * 2011-03-17 2017-03-01 飞思卡尔半导体公司 Semiconductor device and its assemble method
US8647966B2 (en) 2011-06-09 2014-02-11 National Semiconductor Corporation Method and apparatus for dicing die attach film on a semiconductor wafer
US9034697B2 (en) * 2011-07-14 2015-05-19 Freescale Semiconductor, Inc. Apparatus and methods for quad flat no lead packaging
JP2014522130A (en) * 2011-08-11 2014-08-28 エオプレックス リミテッド Lead carrier with package components formed by multi-material printing
US20130344657A1 (en) * 2012-06-26 2013-12-26 Nxp B. V. Package assembly using a carrier-free technique
US20140346656A1 (en) 2013-05-27 2014-11-27 Texas Instruments Incorporated Multilevel Leadframe
US20150035130A1 (en) 2013-07-30 2015-02-05 Texas Instruments Incorporated Integrated Circuit with Stress Isolation
US20150053586A1 (en) 2013-08-22 2015-02-26 Texas Instruments Incorporated Carrier tape
US9620388B2 (en) 2013-08-23 2017-04-11 Texas Instruments Incorporated Integrated circuit package fabrication with die attach paddle having middle channels
US9202778B2 (en) 2013-08-23 2015-12-01 Texas Instruments Incorporated Integrated circuit package with die attach paddle having at least one recessed portion
US9123626B1 (en) 2014-02-27 2015-09-01 Texas Instruments Incorporated Integrated passive flip chip package
US9490146B2 (en) * 2014-06-02 2016-11-08 Stmicroelectronics, Inc. Semiconductor device with encapsulated lead frame contact area and related methods
US9379087B2 (en) * 2014-11-07 2016-06-28 Texas Instruments Incorporated Method of making a QFN package
JP2018514947A (en) * 2015-05-04 2018-06-07 イーオープレックス リミテッド Lead carrier structure without die attach pad and package formed thereon
EP3185291B1 (en) * 2015-12-21 2020-09-23 Nexperia B.V. A leadframe and a method of manufacturing a leadframe

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6740961B1 (en) * 2000-06-09 2004-05-25 National Semiconductor Corporation Lead frame design for chip scale package
US6794224B2 (en) * 2000-08-31 2004-09-21 Micron Technology, Inc. Semiconductor device including leads in communication with contact pads thereof and a stereolithographically fabricated package substantially encapsulating the leads and methods for fabricating the same
US20140070391A1 (en) * 2012-09-07 2014-03-13 Eoplex Limited Lead carrier with print-formed terminal pads

Also Published As

Publication number Publication date
CN110383471B (en) 2022-05-24
US9978613B1 (en) 2018-05-22
CN110383471A (en) 2019-10-25
WO2018165234A1 (en) 2018-09-13
US10079162B1 (en) 2018-09-18

Similar Documents

Publication Publication Date Title
US9691688B2 (en) Thin plastic leadless package with exposed metal die paddle
US7112875B1 (en) Secure digital memory card using land grid array structure
US6703696B2 (en) Semiconductor package
US10943885B2 (en) Method for making semiconductor device with sidewall recess and related devices
CN110289248B (en) SMD integration on QFN through 3D stacking solution
US7173321B2 (en) Semiconductor package having multiple row of leads
US7402459B2 (en) Quad flat no-lead (QFN) chip package assembly apparatus and method
US20070278701A1 (en) Semiconductor package and method for fabricating the same
US20050051877A1 (en) Semiconductor package having high quantity of I/O connections and method for fabricating the same
US9136208B2 (en) Semiconductor device and method of manufacturing the same
US20040238923A1 (en) Surface-mount-enhanced lead frame and method for fabricating semiconductor package with the same
US10861828B2 (en) Molded semiconductor package having a package-in-package structure and methods of manufacturing thereof
US10079162B1 (en) Method for making lead frames for integrated circuit packages
CN211125635U (en) Semiconductor device and electronic device
US11107754B2 (en) Electronic device, leadframe for an electronic device and method for fabricating an electronic device and a leadframe
JPH03250756A (en) Outer lead molding process of semiconductor element
US8643156B2 (en) Lead frame for assembling semiconductor device
CN114981940A (en) Packaged electronic device with segmented die pads in robust package substrate
US10840172B2 (en) Leadframe, semiconductor package including a leadframe and method for forming a semiconductor package
US8106489B1 (en) Integrated circuit package and packaging method
US20140315354A1 (en) Package process
US20200258822A1 (en) High i/o density flip-chip qfn
KR100819794B1 (en) Lead-frame and method for manufacturing semi-conductor package using such
CN108962862B (en) Method for manufacturing lead frame with circuit and structure thereof
JP2004266195A (en) Manufacturing method for semiconductor package

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4