JPH03263145A - Magnetic disk controller - Google Patents

Abstract

PURPOSE:To prevent the performance from being deteriorated due to a disk access and to effectively utilize a cache by constituting the controller so that it is not initialized by a smaller value than the present (Least Recently Used) (LRU) value even when accesses of different LRU initial values compete with each other. CONSTITUTION:A magnetic disk controller 101 is constituted of an interface control part (HOST I/F) 103, a CPU 104, a ROM (F/W ROM) 105, a disk cache memory (CACHE MEM) 106, an interface control part (DRIVE I/F) 108, a data transfer control part (DMA CONTROL) 109, a buffer memory (BUFFER MEM) 110, and a (DIR MEM) 111. In such a state, even when accesses of different LRU initial values compete with each other, it does not occur that the controller is initialized by a smaller value than the present LRU value. In such a way, deterioration of the performance can be prevented, and a cache can be utilized effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention has a built-in disk cache memory and uses L RU (L
The present invention relates to a magnetic disk control device using a control method.

(Prior art) In a magnetic disk control device that has a built-in disk cache memory and uses an LRU control method as a cache block replacement algorithm, the initial value of LRH is made variable in order to make effective use of the disk cache. I can think of a way to do it.

As shown in Figure 4, the LRU update is a process in which the LRU is set to a certain initial value when a request is made or a new registration is made, and if a mistake is made, "1" is subtracted from the current value. Making the initial value variable (for example,
By being able to select four levels of initial values), it is possible to control the amount of time the cache remains resident. For data blocks that are used less often and become unnecessary soon, the initial LRU value is set small so that they can be flushed out of the cache in a short time.

On the other hand, if the number of uses is large, the initial LRU value is increased and the residence time in the cache is lengthened (this is just an example).

The initial value can be specified, for example, by providing it as a parameter in the read/write command, or by setting it in a separate command.

(Problem to be Solved by the Invention) However, when multiple different LRU initial values are accessed at the same time for the same block, in the conventional algorithm, when a large initial value is set, access to a small initial value is If it exists, it will be set to a small initial value, and depending on the case, there is a problem that it will be flushed out of the cache within a short time.

FIG. 5 shows this situation and shows the change over time in the LRU value of a certain cache block. Here, the initial value of LRU can be set in four stages from LRUO to LRU3, and a case will be considered in which LRUO and LRU3 conflict with each other.

1), a new registration is made in LRU3 upon access by tO.

2) In accesses from tl to t4, the data is cached and reset to the value of LRU3.

3), there is an LRUO access at t5, and the LRU value is L.
Set to RUO.

4) Since there is no access to the same block until tO, it is evicted from the cache by another block access at t6.

5), there is an access from LRU3 at t7, and a new registration is made in LRU3 due to a miss.

Therefore, in 5) above, disk access occurs, resulting in performance degradation. This is due to the inconvenience in 4) that the LRU value is initialized with a smaller value than the current LRU value. The processing flow according to the prior art at this time is shown in FIG.

As mentioned above, multiple different L
When accesses to the RU initial value overlap, in the conventional algorithm, when a large initial value was set, if there is an access to a small initial value, the initial value is set to a small initial value, and in some cases, the initial value is set to a small initial value. We had a problem with it being kicked out of our cache.

The present invention has been made in view of the above-mentioned circumstances.In a magnetic disk control device that includes a built-in disk cache memory and uses an LRU control method as a cache block replacement algorithm, when accesses of different initial LRU values conflict, It is an object of the present invention to provide a magnetic disk control device equipped with means for solving performance degradation caused by initialization with a value smaller than the current LRU value.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention compares the current LRU value with the initial value during LRU initialization at the time of cash hit and new registration, and determines whether the current LRU value is If it is less than or equal to the initial value, set the initial value, and if the current LRU value is greater than the initial value, set the current LR
By setting a value that subtracts 1 from the U value, different L
Even if access to the initial RU value conflicts, the current LR
Since it is not initialized with a value smaller than the U value, it is possible to prevent performance degradation associated with conventional disk access, and to make effective use of the cache.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a magnetic disk control device in one embodiment of the present invention.

In FIG. 1, 101 is a magnetic disk control device, and 102 to 112 are magnetic disk control devices 1, respectively.
01, and 102 is a component of the host device 11 (
interface line, 103, which serves as a transmission path between
is an interface control unit (HO8T I/F) that exchanges information with the host device 113 via this interface line 102.

A CPU 104 decodes and executes instructions of a program stored in the ROM 105, and here performs processing control as shown in FIGS. 3 and 4. 105 is CPU
Stores the instructions of the program executed by 104!
ROM (F/V ROM) 106 is the disk cache memory (CACHE) that is the subject of control.
MEN). 107 is an internal bus.

108 is an interface control unit (DRIVE I/F) that exchanges information with the magnetic disk device 114.
). 109 is a data transfer control unit (DMAC0) between the magnetic disk device 114, the host device l13, the buffer memory 11O1 and the disk cache memory 106;
NTR0L). 110 is a magnetic disk device 11
This is a buffer memory (BLIFFERMEN) for absorbing the data transfer rate difference between the data transfer rate of the host device 113 and the host device 113.

111 is a memory (DLRMEN) that stores the presence or absence of data in the disk cache memory 106;

Reference numeral 112 denotes an interface line serving as a transmission path between the magnetic disk device 114 and the magnetic disk device 114 . 113 is a host device (host side device), 114 is a magnetic disk device (DRIV)
E).

FIG. 2 is a flowchart showing the processing flow of direct search in the embodiment of the present invention in comparison with the processing flow of direct search according to the prior art shown in FIG.

FIG. 3 is a time chart showing the temporal change in the LRU value of the cache block in the embodiment of the present invention in comparison with the temporal change in the LRU value of the cache block according to the prior art shown in FIG. .

The operation of an embodiment of the present invention will now be described with reference to FIGS. 1 to 3.

The processing flow shown in FIG. 2 is particularly different from the processing flow of the conventional technology shown in FIG. and the initial value is X, then LR
If U≦X, set X (steps S7, S8),
If LRU>X, set LRU-1 (step S9
).

Next, the operation in one embodiment of the present invention will be explained using FIG.

1), a new registration is made in LRU3 upon access by tO.

2), it is cached in the access at tl-t4 and reset to the value of LRU3.

3), there is an access to LRUO at t5, and the current LRU
Since value>LRU, "current value - 1" is set.

4), there is an access from LRU3 at t7, and Hira) (I
T ), it is initialized to LRU3.

The process shown in FIG. 3 differs from the conventional technique shown in FIG. 5 in that LRUO is not set in 3) and that a miss does not occur in 4).

As mentioned above, in LRU initialization at the time of cash hit and new registration, the current LRU value and the initial value are compared, and if the current LRU value is smaller than or equal to the initial value, the initial value is set, If the current LRU value is larger than the initial value, by setting a value that subtracts 1 from the current LRU value, even if accesses of different initial LRU values conflict, initialization is performed with a value smaller than the current LRU value. This prevents the performance from deteriorating as in the conventional case, and makes effective use of the cache.

Note that in the above embodiment, when initializing the LRU, the current L
When the RU value is larger than the initial value, 1 from the current LRU value
For example, when a cache miss occurs, 1 or a specific value is added to the current LRU value. When the current LRU value is smaller than the initial value, 1 (or a specific value) may be added to the current LRU value.

[Effects of the Invention] As detailed above, according to the present invention, a magnetic disk control device incorporating a disk cache memory and using an LRU control method in which an initial value can be variably set as a cache block replacement algorithm is provided. The current LR is
Compare the U value with the initial value, and if the current LRU value is less than or equal to the initial value, set the initial value, and if the current LRU value is greater than the initial value, set the U value to the initial value. The value obtained by subtracting a small specific value (for example, the current LRU
By having a configuration that includes means for setting a value (value minus 1), even if there is a conflict of access to different LRU initial values, the LRU value will not be initialized to a smaller value than the current LRU value. , the cache can be used effectively without degrading performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a magnetic disk control device in one embodiment of the present invention, FIG. 2 is a flowchart showing the processing flow of direct search in the above embodiment, and FIG. 3 is a flowchart showing the processing flow of a direct search in the above embodiment. Figure 4 is a flowchart showing the processing flow of direct search in the conventional technology. 3 is a time chart showing temporal changes in LRU values. 101...Magnetic disk control device, 102, 112
...Interface line, 103...Interface control unit (HOST I/F) 104...
CPU, 105...ROM (P/V ROM)
, 106-... Disk key + Tush memory (CACH
E MAN), 107...internal bus, 108...
・Interface control unit (DI?lVE I/P)
, 109・. Data transfer control unit (DMA C0NTR0L) 1
10...Buffer memory (BUFFERMEN) 1
11...Memory (DIRHEM), 113...
Upper device (host side device), 114... magnetic disk device (DRIVE).

Claims (1)

[Claims] L has a built-in disk cache memory and can variably set the initial value as a cache block replacement algorithm.
In a magnetic disk control device using the RU control method,
In LRU initialization at the time of cache hit and new registration, means for comparing the current LRU value and the initial value, and setting the initial value when the current LRU value is less than the initial value as a result of the comparison, A magnetic disk control device comprising: means for setting a value obtained by subtracting a specific value smaller than the initial value from the current LRU value when the current LRU value is larger than the initial value.