JP2020149597A - Control device and control method - Google Patents

Abstract

To provide a control device ad a control method capable of suppressing processing delay due to switching of OSs.SOLUTION: A control device 1 comprises a processing part 2, a cash memory 4 common to a plurality of OSs, and a cache lock control part 5. The processing part performs processing corresponding to each OS while switching the plurality of OSs. The cash memory common to the plurality of OSs stores data read by the processing part from a memory storing data used by the processing part for processing. The cache lock control part controls cache lock for prohibiting rewrite to a region of the cash memory. In addition, the cache lock control part changes the region subjected to cache lock so that when the switching of the OSs processed by the processing part is performed, a region, from among the regions of the cash memory, including data read from the memory while the OS before switching is processed is cache locked.SELECTED DRAWING: Figure 1

Description

The present invention relates to a control device and a control method.

In recent years, with the increasing complexity of vehicle control, the number of control programs executed by the control device tends to increase, and the operating OS (Operating System) may also differ between the control programs. Then, a so-called multi-OS technology in which one microcomputer executes different OSs is being introduced into the control device (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2018-013587

By the way, when realizing a multi-OS with one microcomputer, it is necessary to share a cache among a plurality of OSs. Regarding this point, in the prior art, the cache hit rate when operating the target OS is improved and the processing speed is increased by cache-locking the data written in the cache by performing the processing operation in advance before starting the processing of the target OS. I am trying to improve.

However, when the OS must be frequently switched by interrupt processing or the like, for example, in vehicle control, the processing cannot be completed in time if the processing operation is performed in advance each time the OS is switched as in the conventional technology. , There was a risk of processing delay.

The present invention has been made in view of the above, and an object of the present invention is to provide a control device and a control method capable of suppressing a processing delay due to switching of an OS.

In order to solve the above-mentioned problems and achieve the object, the control device according to the present invention includes a processing unit, a cache memory common to a plurality of OSs, and a cache lock control unit. The processing unit performs processing corresponding to each OS while switching between a plurality of OSs (Operating Systems). The cache memory common to a plurality of OSs stores data read by the processing unit from a memory for storing data used by the processing unit for processing. The cache lock control unit controls the cache lock that prohibits rewriting of the cache memory area. Further, when the OS to be processed by the processing unit is switched, the cache lock control unit reads data read from the memory when the OS before switching is being processed in the cache memory area. Change the cache-locked area so that the included area is cache-locked.

According to the present invention, it is possible to suppress the processing delay due to the switching of the OS.

FIG. 1 is a block diagram showing a configuration of a control device according to an embodiment. FIG. 2 is a diagram showing an outline of a control method according to an embodiment. FIG. 3 is a diagram showing a control method according to the embodiment. FIG. 4 is a flowchart showing a processing procedure of processing executed by the control device according to the embodiment. FIG. 5 is a diagram showing a control method according to a modified example.

Hereinafter, embodiments of the control device and control method disclosed in the present application will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments shown below.

First, the outline of the control method according to the embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram showing a configuration of a control device according to an embodiment. FIG. 2 is a diagram showing an outline of a control method according to an embodiment.

As shown in FIG. 1, the control device 1 according to the embodiment includes a processing unit 2, a main memory 3, a cache memory 4, and a cache lock control unit 5.

Here, the control device 1 includes, for example, a computer having a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and various circuits.

The CPU of a computer functions as a processing unit 2 and a cache lock control unit 5 by reading and executing a program stored in a large-capacity storage medium composed of RAM, ROM, etc., which is the main memory 3, for example. ..

It should be noted that some or all of the functions of the processing unit 2 and the cache lock control unit 5 can be configured by hardware such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array).

Further, the cache memory 4 is, for example, a storage unit composed of RAM, capable of reading and writing data at a higher speed than the storage medium constituting the main memory 3, but having a lower capacity than the main memory 3. The RAM functions as a work area of the processing unit 2, and can temporarily store information and the like of various programs executed by the processing unit 2.

Here, the virtualization support function is implemented in the processing unit 2. The virtualization support function is to logically divide one CPU (or core) into two or more by hardware virtualization technology, so that the user can see that the two CPUs (cores) are different OSs. It's a feature that seems to work. As a result, the processing unit 2 composed of one CPU can realize a multi-OS in which processing corresponding to each OS is performed while switching a plurality of OSs.

In the example shown in FIG. 1, the processing unit 2 switches between a real-time OS that performs real-time processing and a non-real-time OS that performs non-real-time processing to perform processing. The real-time OS uses, for example, a communication driver of CAN (Controller Area Network), which is an in-vehicle network, and charges / discharges the in-vehicle battery by receiving a sensor signal for controlling the in-vehicle battery and transmitting a control signal. The control process is executed as a real-time process.

In addition, the non-real-time OS uses, for example, a wireless LAN (Local Area Network) communication driver to charge the vehicle outside the vehicle (for example, from outside the vehicle to the vehicle battery, or to supply power from the vehicle battery to the outside of the vehicle). The communication process with the power supply facility) is executed as a non-real-time process.

The real-time processing is not limited to the charge / discharge control processing, and may be, for example, an engine control processing or the like, as long as it is a processing that requires real-time performance. Further, the non-real-time processing is not limited to the communication processing, and may be, for example, processing of a multimedia device, and may be any processing that does not require real-time performance.

For example, the processing unit 2 reads data for real-time processing from the main memory 3 when operating in a real-time OS. At this time, first confirms whether there is data to be read in the cache memory 4 and then cache memory. When there is data to be read in 4, by reading the data in the cache memory 4, access to the main memory 3 is omitted, and the processing time of the processing unit 2 is shortened. When there is no data to be read in the cache memory 4, the main memory 3 is accessed to read the data, and the data to be read is cache-locked in the cache memory 4 (operates in a real-time OS). If it is, it is stored in the free area of the area for storing the data for real-time processing). The data stored in the main memory 3 and the cache memory 4 includes a code for executing real-time processing, data generated by real-time processing, and the like.

Similarly, when operating on a non-real-time OS, the processing unit 2 performs a process of reading data for non-real-time processing from the main memory 3 and the cache memory 4 and rewriting the cache memory 4. The processing at this time is the same as the processing content in the real-time OS described above. The data stored in the main memory 3 and the cache memory 4 includes a code for executing non-real-time processing, data generated by real-time processing, and the like.

When the data is stored in the cache memory 4, if there is no free area in the cache memory 4, the old data in the area of the cache memory 4 (data whose most recently read time is old or written). Overwrite storage (rewriting) is performed in the area in which the old data) is stored, and the original data in the overwritten area is expelled from the cache memory 4.

The cache lock control unit 5 controls the cache lock that prohibits rewriting of the area of the cache memory 4. The details of the cache lock performed by the cache lock control unit 5 will be described later.

Here, in the prior art, the processing data of the target OS is cache-locked by the processing data of another OS by performing the processing operation in advance and cache-locking the processing data written in the cache memory before the processing of the target OS is started. I try not to be kicked out of.

However, when it is necessary to frequently switch the OS by interrupt processing or the like as in vehicle control, if the processing operation is performed in advance as in the conventional technology, the processing may not be in time and a processing delay may occur. Also, if cache lock is not performed, when one OS is operating, the cache memory area will be rewritten to the data of that OS every time data is read, so it was switched to the other OS. In that case, the OS data after switching does not remain in the cache memory, and the cache hit rate decreases, so that the processing may not be in time and a processing delay may occur.

Therefore, in the control method according to the embodiment, when the OS to be processed by the processing unit 2 is switched, the data read from the main memory 3 when the OS before the switching is processed in the area of the cache memory 4. The area to be cache-locked is changed so that the area including is cache-locked. Here, the control method according to the embodiment will be described with reference to FIG.

FIG. 2 describes a cache lock when switching from a real-time OS to a non-real-time OS. Further, in FIG. 2, the area of the cache memory 4 is divided into four areas D1 to D4, and one data is stored in each area D1 to D4.

As shown in FIG. 2, in the control method according to the embodiment, the cache lock control unit 5 switches from the real-time OS to the non-real-time OS when the OS processed by the processing unit 2 is switched. Of the areas D1 to D4 of the cache memory 4, the areas D1 and D2 including the data read from the main memory 3 when the real-time OS is processed are cache-locked.

As a result, even if the non-real-time processing data is stored in the cache memory 4, it is possible to prevent the real-time processing data from being expelled from the cache memory 4.

Therefore, when the non-real-time OS is switched to the real-time OS due to an interrupt such as vehicle control, real-time processing data remains in the cache-locked areas D1 and D2, so that the cache hit rate is improved. , Real-time processing can be performed at high speed.

In other words, in the control method according to the embodiment, it is not necessary to perform the processing operation in advance and write the data to the cache memory before the start of the processing, unlike the conventional technique. Therefore, even when the OS must be switched frequently, processing delay is less likely to occur. Therefore, according to the control method according to the embodiment, it is possible to suppress the processing delay due to the switching of the OS.

Next, the control method according to the embodiment will be specifically described with reference to FIG. FIG. 3 is a diagram showing a control method according to the embodiment. In FIG. 3, it is assumed that the real-time OS is switched to the non-real-time OS at time t1 and the non-real-time OS is switched to the real-time OS at time t2.

Further, as shown in FIG. 3, the cache memory 4 is divided in advance into a dedicated area D10 in which real-time processing data is stored and a dedicated area D20 in which non-real-time processing data is stored. Further, the dedicated area D10 is divided into four areas D11 to D14, and one real-time processing data is stored in each area D11 to D14. Further, the dedicated area D20 is divided into four areas D21 to D24, and one non-real-time processing data is stored in each area D21 to D24.

The cache lock control unit 5 cache locks the dedicated areas D10 and D20 including the data read from the main memory 3 when the OS before switching is processed. Specifically, as shown in FIG. 3, at time t1, the cache lock control unit 5 cache locks the dedicated area D10 corresponding to the real-time OS which is the OS before switching. Further, at time t1, the cache lock control unit 5 releases the cache lock of the dedicated area D20 corresponding to the non-real-time OS which is the OS after switching.

As a result, it is possible to prevent the real-time processing data from being expelled to the main memory 3 during the non-real-time processing, and it is possible to write the non-real-time processing data to the dedicated area D20.

Next, at time t2, the cache lock control unit 5 cache locks the dedicated area D20 corresponding to the non-real-time OS which is the OS before switching. Further, at time t2, the cache lock control unit 5 releases the cache lock of the dedicated area D10 corresponding to the real-time OS which is the OS after switching.

As a result, it is possible to prevent the non-real-time processing data from being expelled to the main memory 3 during real-time processing, and it is possible to write the non-real-time processing data to the dedicated area D10. Further, since the real-time processing data before the time t1 remains in the dedicated area D10 at the time t2, the real-time processing after the time t2 can be speeded up.

In the period from time t1 to time t2, the cache lock of the dedicated area D10 is maintained until time t2 during the idle period after the end of non-real-time processing.

Alternatively, the non-real-time OS may be switched to the real-time OS in advance after the non-real-time processing is completed from time t1. In such a case, at the time of switching, the cache lock of the dedicated area D10 is released and the dedicated area D20 is cache-locked.

In this way, the cache lock control unit 5 switches the cache lock in units of the dedicated areas D10 and D20 divided in advance, so that the data stored in the cache memory 4 can be cache-locked reliably and with a low load. Can be done.

In FIG. 3, the dedicated areas D10 and the dedicated areas D20 are set to substantially the same number of areas D11 to D14 and D21 to D24, but the number of areas of the dedicated areas D10 and D20 may be different, and further, it is arbitrary. The number of areas can be set.

The cache lock control unit 5 may predict the processing load of the next cycle and dynamically change the cache lock area, which will be described later in FIG.

Next, the processing procedure of the processing executed by the control device 1 according to the embodiment will be described with reference to FIG. FIG. 4 is a flowchart showing a processing procedure of processing executed by the control device 1 according to the embodiment.

As shown in FIG. 4, first, the processing unit 2 of the control device 1 determines whether or not the switching timing of the OS has arrived (S101), and if the switching timing has not arrived (S101: No), it has arrived. Step S101 is executed until

When the OS switching timing arrives (S101: Yes), the processing unit 2 performs register save processing corresponding to the OS before switching (S102).

Subsequently, the cache lock control unit 5 determines whether or not the OS before switching is a real-time OS (S103). When the OS before switching is a real-time OS (S103: Yes), the cache lock control unit 5 cache-locks the dedicated area D10 for real time (S104).

Subsequently, the cache lock control unit 5 performs a register restoration process corresponding to the OS after switching (S105), and ends the process. That is, the cache lock control unit 5 cache locks the area of the cache memory 4 between the register save process corresponding to the OS before switching and the register restore process corresponding to the OS after switching. As a result, the cache lock switching process can be reliably performed.

On the other hand, in step S104, when the OS before switching is a non-real-time OS (S103: No), the cache lock control unit 5 cache-locks the non-real-time dedicated area D20 (S106).

As described above, the control device 1 according to the embodiment includes a processing unit 2, a cache memory 4 common to a plurality of OSs, and a cache lock control unit 5. The processing unit 2 performs processing corresponding to each OS while switching between a plurality of OSs (Operating Systems). The cache memory 4 common to the plurality of OSs stores the data read by the processing unit 2 from the main memory 3 that stores the data used by the processing unit 2 for processing. The cache lock control unit 5 controls the cache lock that prohibits rewriting of the area of the cache memory 4. Further, when the OS to be processed by the processing unit 2 is switched, the cache lock control unit 5 reads the data read from the main memory 3 in the area of the cache memory when the OS before the switching is being processed. Change the cache-locked area so that the included area is cache-locked. As a result, it is possible to suppress the processing delay due to the switching of the OS.

Next, a case where the cache lock area is dynamically changed will be described with reference to FIG. FIG. 5 is a diagram showing a control method according to a modified example.

At the time of OS switching, the cache lock control unit 5 predicts the processing load in the switched OS based on the processing cycle corresponding to the switched OS, and cache locks the area in the range corresponding to the predicted processing load. To do. The processing cycle can be grasped from the control contents and the like.

For example, at time t11, the processing unit 2 predicts the processing load of real-time processing from time t11 to time t12 when switching from the non-real-time OS to the real-time OS.

Then, the cache lock control unit 5 reduces the range of the cache lock area (D37, D38) as the processing load of the predicted real-time processing increases. As a result, the areas (D31 to D36) for storing the real-time processing data can be increased, so that it is possible to suppress the occurrence of processing delay.

Further, at time t12, the cache lock control unit 5 predicts the processing load of non-real-time processing from time t12 when switching from the real-time OS to the non-real-time OS.

Then, as shown in FIG. 5, since the predicted processing load of the non-real-time processing is relatively small, the cache lock control unit 5 increases the range of the cache lock area (D31 to D36) of the real-time processing. For example, when the non-real-time processing is relatively small, the cache lock control unit 5 cache-locks so that all the data of the real-time processing remains. As a result, a large amount of real-time processing data can be left, so that real-time processing can be speeded up at the next operation.

In this way, by dynamically changing the cache lock range according to the processing load, the performance of the entire processing in the control device 1 can be improved.

Further effects and variations can be easily derived by those skilled in the art. For this reason, the broader aspects of the invention are not limited to the particular details and representative embodiments expressed and described as described above. Therefore, various modifications can be made without departing from the spirit or scope of the general concept of the invention as defined by the appended claims and their equivalents.

1 Control device 2 Processing unit 3 Main memory 4 Cache memory 5 Cache lock control unit

Claims (7)

A processing unit that performs processing corresponding to each OS while switching between multiple OSs (Operating System),
A cache memory common to a plurality of OSs that stores data read by the processing unit from a memory that stores data used by the processing unit for processing, and
A cache lock control unit that controls a cache lock that prohibits rewriting of the cache memory area,
With
The cache lock control unit
When the OS processed by the processing unit is switched, the area of the cache memory including the data read from the memory when the OS before switching is being processed is cache-locked. , A control device characterized by changing the cache-locked area. The cache memory is
It is divided in advance into a plurality of dedicated areas allocated to each of the plurality of OSs.
The cache lock control unit
The control device according to claim 1, wherein when the OS before switching is processed, the dedicated area including the data read from the memory is cache-locked. The cache lock control unit
At the time of switching the OS, the processing load in the OS after switching is predicted based on the processing cycle corresponding to the OS after switching, and the area in the range corresponding to the predicted processing load is cache-locked. The control device according to claim 1, wherein the control device is characterized by the above. For the plurality of OSs
Includes a real-time OS that performs real-time processing,
The cache lock control unit
One of claims 1 to 3, wherein when switching from the real-time OS to another OS, an area including data read from the memory is cache-locked when the real-time OS is processed. The control device described in. The plurality of OSs
A real-time OS that performs real-time processing and a non-real-time OS that performs non-real-time processing.
The cache lock control unit
When switching from one OS to the other OS, the area containing the data read from the memory when one OS is processed is cache-locked, and is read from the memory when the other OS is processed. The control device according to any one of claims 1 to 4, wherein the cache lock of the area containing the data is released. The cache lock control unit
The invention according to any one of claims 1 to 5, wherein the area is cache-locked between the register save process corresponding to the OS before switching and the register restore process corresponding to the OS after switching. Control device. A control method for a control device having a cache memory common to a plurality of OSs, in which data read from a memory for storing data used for processing of a plurality of OSs (Operating System) is stored.
A processing step of performing the processing corresponding to each OS while switching the plurality of OSs,
A cache lock control step that controls a cache lock that prohibits rewriting of the cache memory area, and
Including
The cache lock control step is
When the OS processed in the processing step is switched, the area of the cache memory including the data read from the memory when the OS before switching is processed is cache-locked. In addition, a control method characterized in that the area to be cache-locked is changed.