JPH03263143A - Buffer storage device - Google Patents

Abstract

PURPOSE:To prevent the instruction processing from being interrupted by executing the read-out requirement of a next block, when the read-out requirement is issued to operand data positioned in the rear in the block. CONSTITUTION:The operand data read-out requirement issued from an instruction processing means 1 is sent to the control part 6 of this buffer storage device 2, compared with address information stored in an address storage part 5, and whether it present on the buffer storage device 2 or not is checked up. When the required operand data is present on the buffer storage device 2, the operand data read out of an operand storage part 4 is sent to an instruction processing means 1, and also, whether the operand data is positioned in the rear of the block or not is checked up, and when it is positioned in the rear, the transfer requirement of the next block is sent to a main storage means 3. In such a manner, the operand data can be supplied continuously, and the break of an instruction processing can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffer storage device that stores operand data, and particularly to a buffer storage device that can speed up the supply of operand data.

[Conventional technology]

Conventionally, this type of buffer storage device checks whether or not the operand data exists in the buffer storage device when there is a request to read operand data from an instruction processing means.
A read request for a block is issued to the main storage means only when the block does not exist, and when the block does exist, the operand data is transferred to the instruction processing means.

[Problem to be solved by the invention]

In the conventional buffer storage device described above, when there is a request to read an operand from an instruction processing means, it is checked whether the operand data exists in the buffer storage device, and only when the operand data does not exist, a block is sent to the main storage means. Since a read request is issued, the supply of operand data to the instruction processing means stops while the operand block is being transferred from the main memory means, causing an interruption in instruction processing. There were drawbacks.

[Means to solve the problem]

The buffer storage device of the present invention is provided between the instruction processing means and the main storage means of an information processing apparatus, which has an instruction processing means for explaining and processing instruction words, and a main storage means for storing operand data. In the buffer storage device, a transfer of a part of the instruction word stored in the main storage means is stored in block units, and when a read request for the operand data is received from the instruction processing means, the operand data is stored. If the operand data has been stored, the operand data is transferred to the instruction processing means, and if the operand data is located at the rear of the block, a read request is made for the block that is continuous with the block. The control circuit is configured to include a control circuit for issuing the information to the main storage means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The buffer storage device 2 in FIG. 1 includes an operand storage section 4, an address storage section 5. It is composed of a control section 6. In FIG. 1, an operand data read request issued from the instruction processing means 1 is sent to the control section 6 of the buffer storage device 2, and is compared with address information stored in the address storage section 5. It is checked whether or not it exists within. When the requested operand data exists in the buffer storage device 2, the operand data read from the operand storage section 4 is sent to the instruction processing means 1, and it is checked whether the operand data is located at the rear of the block. When it is located at the rear, a transfer request for the next block is sent to the main storage means 3.

FIG. 2 is a detailed block diagram of the shock absorber feeding device 2 of FIG. 1. The address register 10 stores the address information of the operand data requested by the instruction processing means 1, and the address register 10 stores the address information of the operand data requested by the instruction processing means 1. Address line 22. 'Address line 23
Output separately. The lower several bits of the address information are sent to the comparator 17 through the address line 21 and compared with a fixed value 16. Here, the fixed value 16 is a value indicating the rear within the block, and when the address sent by the address line 21 is larger than this value, a signal indicating that it is the rear is issued. The middle-order bits of the address information are searched through the address line 22 in the address storage section 5 and the operand storage section 4. The output from the address storage section 5 is compared with the upper few bits of the address information sent through the address line 23 in the address comparator 13, and if they match, the operand data requested from the instruction processing means 1 is stored in the buffer memory. It will exist in device 2. The output from the operand storage section 4 is sent to the buffer 14, and in response to a match signal from the address comparator 13, is sent to the instruction processing means 1 via the operand data transfer line 26. A request line 25 indicates a request to read a block of operand data to the main storage means 3, which is a value obtained by inverting the match signal from the address comparator 13 by the NOT logic circuit 18, that is, the operand requested from the instruction processing means 1. When the data does not exist in the buffer storage device 2, the match signal from the address comparator 13 and the signal from the comparator 17 indicating that the data is at the end of the block are
The value ANDed by the D logic circuit 19, that is, the operand data requested by the instruction processing means 1, is stored in the buffer storage device 2.
This is when the block is located within the block and is located further back within the block.

The OR logic circuit 20 is for ORing the above two conditions. Furthermore, the output of the AND logic circuit 19 is sent to the adder 15 together with its inverted signal. The adder 15 is
It updates the upper few bits of the address information sent through the address line 23. This uses the output of the AND logic circuit 19 to process the request from the instruction processing means 1 when the operand data requested by the instruction processing means 1 exists in the buffer storage device 2 and is located at the rear of the block. The address information of the next block is generated by adding a fixed value 16 to the address information of the operand data where the ``I! 24 to the main storage means 3.

〔Effect of the invention〕

As explained above, in the present invention, when there is a read request for operand data located later in a block, a read request for the next block is made, so that the operand data requested by the instruction processing means is stored in the buffer memory. This has the effect of reducing interruptions in instruction processing because operand data can be supplied without gaps.

FIG.

DESCRIPTION OF SYMBOLS 1... Instruction processing means, 2... Buffer memory, 3... Main memory means, 4... Operand storage section, 5... Address storage section, 6... Control section, 10... Address register, 13...Address comparator, 14...Buffer,
15...Adder, 16...Fixed value, 17...Comparator, 18...NOT logic circuit, 19...AND logic circuit, 20...OR logic circuit, 21-14... -Address line, 25...Request line, 26...Operand data transfer line.

Claims (1)

[Claims] In a buffer storage device provided between the instruction processing means and the main memory means of an information processing apparatus, the information processing apparatus has an instruction processing means for analyzing and processing instruction words, and a main memory means for storing operand data. A copy of a part of the instruction word stored in the storage means is stored in block units, and when a read request for the operand data is received from the instruction processing means, it is checked whether or not the operand data is stored. to transfer the operand data to the instruction processing means when the operand data is located later in the block, and to issue a read request for a block following the block to the main storage means if the operand data is located later in the block. A buffer storage device comprising a control circuit.