JPH03262122A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03262122A
JPH03262122A JP6154490A JP6154490A JPH03262122A JP H03262122 A JPH03262122 A JP H03262122A JP 6154490 A JP6154490 A JP 6154490A JP 6154490 A JP6154490 A JP 6154490A JP H03262122 A JPH03262122 A JP H03262122A
Authority
JP
Japan
Prior art keywords
etching
film
bonding
window
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6154490A
Other languages
Japanese (ja)
Inventor
Shunichi Nagata
永田 俊一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6154490A priority Critical patent/JPH03262122A/en
Publication of JPH03262122A publication Critical patent/JPH03262122A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enhance the reliability of wire bonding, and to make it possible to prevent the lowering of yield of production and reliability of LSI and the like by a method wherein a non-penetrated aperture is formed on an insulating film by etching, an argon sputtering treatment is conducted, and then an aperture is formed by penetrating the non-penetrated aperture. CONSTITUTION:When an insulating film 3 is etched by RIE treatment using a resist film 4 as a mask, the resist component dissolved by the RIE etching is adhered, as the deposited film 7 of polymer to the side wall of the section to be etched, namely, the aperture 5 for etching of the resist film 4 and the side wall of a non-penetrated bonding window 6a which is being formed. At that time, a wire-bonding window 6 is etched to the extent that the window 6 is brought into the state of non-penetrated window 6a having the depth just before penetration, and the etching operation is temporarily discontinued. Then, an argon sputtering treatment is conducted, a polymer deposited film 6 is sputtered by argon particles 8, and after the film 7 is removed by scattering, the coated insulating film 3 is etched again until a bonding pad 2 is exposed, and a wire bonding window 6 is completed.

Description

【発明の詳細な説明】 [概 要] 半導体装置の製造方法、特にLSI等の製造工程におけ
る絶縁膜にワイヤボンディング窓を形成する方法の改良
に関し、 ポンディングパッド上にポリマー等の堆積膜を付着せし
めないワイヤポンディング窓の形成方法を提供すること
を目的とし、 導電性基体(2)上の絶縁膜(3)に、レジスト(4)
をマスクにしてリアクティブイオンエツチングにより該
導電性基体(2)面を表出する開孔(6)を形成するに
際して、該リアクティブイオンエツチングにより該絶縁
膜(3)に未貫通の開孔(6a)を形成する第1次エツ
チング工程と、該レジスト(4)を残したままアルゴン
スパッタ処理を行って該未貫通開孔(6a)の内面に付
着している重合物質(7)を除去するアルゴンスパッタ
工程と、該レジスト(4)をマスクにしてリアクティブ
イオンエッチングにより該絶縁膜(3)の未貫通開孔(
6a)を貫通させ開孔(6)を形成せしめる第2次エツ
チング工程とを有し構成される。
[Detailed Description of the Invention] [Summary] Regarding the improvement of the method of manufacturing semiconductor devices, especially the method of forming a wire bonding window in an insulating film in the manufacturing process of LSI, etc., the present invention involves depositing a deposited film such as a polymer on a bonding pad. The purpose of this invention is to provide a method for forming a wire bonding window that does not interfere with the wire bonding.
When forming an opening (6) exposing the surface of the conductive substrate (2) by reactive ion etching using a mask as a mask, a non-penetrating opening (6) is formed in the insulating film (3) by the reactive ion etching. 6a), and perform argon sputtering while leaving the resist (4) to remove the polymeric substance (7) adhering to the inner surface of the non-through hole (6a). A non-through hole (
6a) to form an opening (6).

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法、特にLSI等の製造工
程における絶縁膜にワイヤボンディング用窓を形成する
方法の改良に関する。
The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for forming a wire bonding window in an insulating film in the manufacturing process of an LSI or the like.

LSI等のチップをパッケージに組み込む際のワイヤポ
ンディングの信頼性は、絶縁膜のワイヤボンディング窓
内に表出しているアルミニウム(AI!、)等導電性基
体によるポンディングパッド表面の清浄度に依存するの
で、ポンディングパッド面に異物を付着せしめないよう
なワイヤボンディング用窓の形成技術が要望される。
The reliability of wire bonding when incorporating chips such as LSI into a package depends on the cleanliness of the surface of the bonding pad made of a conductive substrate such as aluminum (AI!) exposed within the wire bonding window of the insulating film. Therefore, there is a need for a technique for forming wire bonding windows that does not allow foreign matter to adhere to the surface of the bonding pad.

〔従来の技術〕[Conventional technology]

一般にLSI等の製造工程において、ワイヤボンディン
グ窓の形成にはりアクティブイオンエツチング(RIB
 )処理が広く用いられており、従来例えばAn等から
なるポンディングパッド上を覆う絶縁膜に、このポンデ
ィングパッドを表出するワイヤボンディング用窓56を
形成するに際しては、第3図(a)に示すようにポンデ
ィングパッド52が形成された層間絶縁膜51上を覆う
被覆絶縁膜53上に、レジスト膜54を塗布し、フォト
プロセスによりこのレジスト膜54にワイヤボンディン
グ用窓に対応する形状のエツチング用開孔55を形成し
た後、第3図(b)に示すように、上記レジスト膜54
をマスクにしRIE処理を行って、レジスト膜54のエ
ツチング用開孔55の下部の被覆絶縁膜53を選択的に
、ポンディングパッド52が表出するまで一気にエツチ
ングする方法が用いられていた。
Generally, in the manufacturing process of LSI etc., active ion etching (RIB) is used to form wire bonding windows.
) process is widely used, and conventionally, when forming a wire bonding window 56 exposing the bonding pad in an insulating film that covers the bonding pad made of, for example, An, the process shown in FIG. 3(a) is used. As shown in FIG. 3, a resist film 54 is coated on the covering insulating film 53 that covers the interlayer insulating film 51 on which the bonding pad 52 is formed, and a shape corresponding to the wire bonding window is formed on this resist film 54 by a photo process. After forming the etching holes 55, as shown in FIG. 3(b), the resist film 54 is
A method has been used in which a RIE process is performed using the resist film 54 as a mask, and the covering insulating film 53 under the etching opening 55 of the resist film 54 is selectively etched at once until the bonding pad 52 is exposed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら上記従来の方法によると、ポンディングパ
ッド上の被エツチング膜即ち被覆絶縁膜53の膜厚が厚
くなってエツチング時間が長引いた場合、エツチング中
にエツチングガスとレジストとの反応によって生成した
ポリマー(重合物質)57が、第3図(a)に示される
ようにポンディングパッド52の表面に被膜状に再付着
することがある。そのため、上記ポンディングパッド5
2上に例えば金ワイヤ(図示せず)を熱圧着等によりポ
ンディングする際に、上記ポリマー57がポンディング
パッド52と金ワイヤ(図示せず)との間に介在して完
全なポンディングを妨げ、ボンディング剥がれを生じて
LSI等の歩留りや信頼性を低下せしめるという問題が
あった。
However, according to the above-mentioned conventional method, when the film to be etched on the bonding pad, that is, the covering insulating film 53, becomes thick and the etching time becomes long, polymers ( As shown in FIG. 3(a), the polymeric substance 57 may re-deposit on the surface of the bonding pad 52 in the form of a film. Therefore, the above-mentioned pounding pad 5
When bonding, for example, a gold wire (not shown) onto the pad 2 by thermocompression bonding or the like, the polymer 57 is interposed between the bonding pad 52 and the gold wire (not shown) to ensure complete bonding. There is a problem in that the yield and reliability of LSI etc. are reduced due to interference and bonding peeling.

そこで本発明は、ワイヤポンディングの信頼性を高め、
LSI等の製造歩留りや信頼性の低下を防止するために
、ポンディングパッド上にポリマー等の堆積膜を付着せ
しめないワイヤポンディング窓の形成方法を提供するこ
とを目的とする。
Therefore, the present invention improves the reliability of wire bonding and
An object of the present invention is to provide a method for forming a wire bonding window without depositing a deposited film of polymer or the like on a bonding pad, in order to prevent a decrease in manufacturing yield or reliability of LSI or the like.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題は第1図(a)〜(C)の原理説明用工程断面
図に参照されるように、導電性基体(2)上の絶縁膜(
3)に、レジスト(4)をマスクにしてリアクティブイ
オンエツチングにより該導電性基体(2)面を表出する
開孔(6)を形成するに際して、該リアクティブイオン
エツチングにより該絶縁膜(3)に未貫通の開孔(6a
)を形成する第1次エツチング工程と、該レジスト(4
)を残したままでアルゴンスパッタ処理を行って、該レ
ジスト表面と未貫通開孔(6a)の内面に付着している
重合物質(7)を除去するアルゴンスパッタ処理と、該
レジスト(4)をマスクにしてリアクティブイオンエツ
チングにより該絶縁膜(3)の未貫通開孔(6a)を貫
通させ開孔(6)を形成せしめる第2次エツチング工程
とを有する本発明による半導体装置の製造方法によって
解決される。
The above problem is solved by the insulating film (
3), when forming an opening (6) exposing the surface of the conductive substrate (2) by reactive ion etching using the resist (4) as a mask, the insulating film (3) is formed by the reactive ion etching. ) with an unpierced hole (6a
) and a first etching step to form the resist (4).
) is left intact to remove the polymeric substance (7) adhering to the surface of the resist and the inner surface of the non-penetrating hole (6a), and the resist (4) is masked. Solved by the method for manufacturing a semiconductor device according to the present invention, which includes a second etching step of penetrating the non-through hole (6a) of the insulating film (3) by reactive ion etching to form the hole (6). be done.

〔作 用〕[For production]

第1図(a)〜(C)は本発明の原理説明用工程断面図
である。
FIGS. 1(a) to 1(C) are process sectional views for explaining the principle of the present invention.

図において、1は層間絶縁膜、2はポンディングパッド
(導電性基体)、3は被覆絶縁膜(絶縁膜)、4はフォ
トレジス1−膜(レジスト)、5はレジスト膜のエツチ
ング用開孔、6は貫通ボンディング用窓(開孔)、6a
は未貫通ボンディング用窓(未貫通の開孔)、7はポリ
マー等の堆積膜(重合物質)、8はアルゴン(Ar)粒
子を示す。 第1図(a)に示すように、レジスト膜4
をマスクにしてRIE処理によるエツチングを行うと、
RIEエツチングにより分解したレジストの成分が被エ
ツチング部の側壁即ちレジスト膜4の工・ンチング用開
孔5及び形成されつつある未貫通ボンディング窓6aの
側壁にポリマーの堆積膜7となって被着する。この状態
で引続きエツチングを続行すると、被エツチング部はポ
リマーリッチの雰囲気でエツチングされることになり、
パッド表面にポリマーの堆積膜が形成され易(なる。
In the figure, 1 is an interlayer insulating film, 2 is a bonding pad (conductive base), 3 is a covering insulating film (insulating film), 4 is a photoresist film (resist), and 5 is an etching hole in the resist film. , 6 is a through bonding window (opening), 6a
7 indicates a non-penetrating bonding window (a non-penetrating opening), 7 indicates a deposited film such as a polymer (polymerized substance), and 8 indicates an argon (Ar) particle. As shown in FIG. 1(a), the resist film 4
When etching is performed by RIE process using as a mask,
The components of the resist decomposed by the RIE etching form a deposited polymer film 7 on the sidewalls of the etched portion, that is, the etching openings 5 in the resist film 4 and the sidewalls of the non-penetrating bonding windows 6a that are being formed. . If etching is continued in this state, the area to be etched will be etched in a polymer-rich atmosphere.
A deposited polymer film is easily formed on the pad surface.

そこで 本発明の方法においては、第1図(a)に示す
ように、ワイヤボンディング用窓6を貫通直前の深さを
有する未貫通窓6aの状態までエツチングし、そこでエ
ツチングを一次中止し、次いで第1図(1))に示すよ
うに、アルゴンスパッタ処理を行い、上記ポリマーの堆
積膜7をアルゴンの粒子8により叩き、飛散せしめて除
去した後、第1図(C)に示すように、再び被覆絶縁膜
3のエツチングをポンディングパッド2が表出するまで
行い、貫通ボンディング用窓(ワイヤボンディング用窓
)6を完成させる。
Therefore, in the method of the present invention, as shown in FIG. 1(a), the wire bonding window 6 is etched to the state of an unpenetrated window 6a having a depth immediately before being penetrated, the etching is temporarily stopped there, and then As shown in FIG. 1(1)), argon sputtering is performed, and the deposited polymer film 7 is struck with argon particles 8 to scatter and remove, and then as shown in FIG. 1(C), The covering insulating film 3 is etched again until the bonding pad 2 is exposed, and the through bonding window (wire bonding window) 6 is completed.

このようにすると、ワイヤボンディング用窓6内にポン
ディングパッド2面が表出される際に、被エツチング部
上のエツチング雰囲気中に含まれるポリマーの量は大幅
に減少するので、貫通ボンディング用窓6内に、表出す
るボンディングバンド2の表面は、ポリマー等の堆積物
が被着されない清浄な面になる。
In this way, when the surface of the bonding pad 2 is exposed in the window 6 for wire bonding, the amount of polymer contained in the etching atmosphere on the part to be etched is significantly reduced, so that the window 6 for through bonding The exposed surface of the bonding band 2 becomes a clean surface free from deposits such as polymers.

従って、上記ポンディングパッド2上に熱圧着等により
圧着される金ワイヤ等のボンディング強度は、十分に確
保される。
Therefore, the bonding strength of the gold wire or the like bonded onto the bonding pad 2 by thermocompression bonding or the like is sufficiently ensured.

〔実施例〕〔Example〕

以下本発明をワイヤボンディング用窓形成の際の一実施
例について、第2図(a)〜(C)に示す工程断面図を
参照し具体的に説明する。
Hereinafter, one embodiment of the present invention for forming a window for wire bonding will be specifically described with reference to process cross-sectional views shown in FIGS. 2(a) to 2(C).

第2図(a)参照 本発明の方法により、例えば第1の層間絶縁膜11上に
第1のAl膜からなるポンディングパッド12が形成さ
れ、その上にA!の突起を押さえる厚さ2000人程度
0気相成長による酸化シリコン(CVDSiOz)膜1
3が形成され、上層の配線形成面を平坦化するためのス
ピンオングラス(SOG)層14が塗布され、その上に
りん珪酸ガラス(PSG)からなる厚さ1μm程度の第
2の層間絶縁膜15が形成され、その上に第2のAff
i膜からなる上層の配線16が形成され、その上に厚さ
0.7μm程度のPSG膜17Aと厚さ0.3μm程度
の窒化シリコン(SiJn)膜17Bとからなる被覆絶
縁膜17が形成されてなる被処理半導体基板に、前記ポ
ンディングパッド12を表出するワイヤボンディング用
窓を形成するに際しては、先ず、この被処理基板上に3
μm程度の厚さを有するポジレジスト膜18を形成し、
通常のフォトプロセスによりこのレジスト膜18にワイ
ヤボンディング用窓の形状に対応する形状を有するエツ
チング用開孔19を形成する。
Refer to FIG. 2(a) According to the method of the present invention, for example, a bonding pad 12 made of a first Al film is formed on the first interlayer insulating film 11, and A! Silicon oxide (CVDSiOz) film by vapor phase growth 1 with a thickness of about 2000 to suppress the protrusions of
3 is formed, a spin-on glass (SOG) layer 14 is applied to flatten the upper layer wiring formation surface, and a second interlayer insulating film 15 made of phosphosilicate glass (PSG) with a thickness of about 1 μm is applied thereon. is formed, and a second Aff is formed on top of it.
An upper layer wiring 16 made of an i film is formed, and a covering insulating film 17 made of a PSG film 17A with a thickness of about 0.7 μm and a silicon nitride (SiJn) film 17B with a thickness of about 0.3 μm is formed thereon. When forming a wire bonding window that exposes the bonding pad 12 on a semiconductor substrate to be processed, first, three
Forming a positive resist film 18 having a thickness of about μm,
An etching opening 19 having a shape corresponding to the shape of the wire bonding window is formed in this resist film 18 by a normal photo process.

そして第1次のエツチング処理として、このレジスト膜
18をマスクにし、通常の平行平板型エツチング装置を
用い、例えば3弗化メタン(CI(F3)をエツチング
ガスにし0.1〜0.2 Torr程度の減圧中におい
て0.2〜0.3 W/cn+2程度のパワー密度で、
前記被覆絶縁膜17の下層部のPSG膜17Aを100
0人残す程度までリアクティブイオンエツチング(Il
lE)処理を行い、未貫通のワイヤボンディング用窓2
0aを形成する。この際、強いエツチングが行われない
レジスト膜18のエツチング用開孔19及び未貫通ワイ
ヤボンディング用窓20aの側壁面には、レジストの分
解・重合によって生じた100人程人程厚さのポリマー
が堆積膜21となって被着する。
As a first etching process, this resist film 18 is used as a mask, and a normal parallel plate type etching apparatus is used to perform etching using, for example, methane trifluoride (CI (F3)) as an etching gas of about 0.1 to 0.2 Torr. At a power density of about 0.2 to 0.3 W/cn+2 during depressurization,
The PSG film 17A in the lower layer part of the covering insulating film 17 is
Reactive ion etching (Il) until 0 people remain.
lE) Processed and unpierced wire bonding window 2
Form 0a. At this time, on the side wall surfaces of the etching openings 19 and the non-penetrating wire bonding windows 20a of the resist film 18, which are not subjected to strong etching, a polymer with a thickness of about 100 people is generated due to the decomposition and polymerization of the resist. It becomes a deposited film 21 and adheres.

第2図(b)参照 次いで上記被処理基板を通常のバレル型のエツチング装
置内に移し、圧力Q、5 Torr 、パワ−300W
程度で10分間程度アルゴン(Ar)スパッタ処理を行
う。この処理で前記ポリマー堆積膜21はAr粒子22
に叩かれて飛散除去される。
Refer to FIG. 2(b). Next, the substrate to be processed was transferred into an ordinary barrel-type etching apparatus, and the etching process was carried out at a pressure Q of 5 Torr and a power of 300 W.
Argon (Ar) sputtering is performed for about 10 minutes. With this treatment, the polymer deposited film 21 is made of Ar particles 22.
It is struck and scattered.

この際、レジスト膜18の減量は1000人弱程度で0 殆ど問題にならない。At this time, the weight loss of the resist film 18 was about 1,000 people. Almost no problem.

第2図(C)参照 次いで上記スパッタ処理の終わった被処理基板を再び前
記平行平板型エツチング装置に戻し、前記第1次エツチ
ング処理と同一の条件によるRIE処理により前記レジ
スト膜18をマスクにして第2次のエツチング処理を行
って、未貫通ワイヤボンディング窓20aの底部に表出
している前記PSG膜17^、その下部の第2の層間絶
縁膜15及び更にその下部のCVD−3iO□膜13を
除去し、ポンディングパッドI2の上面を表出する貫通
したワイヤボンディング用窓20を完成する。
Refer to FIG. 2(C) Next, the substrate to be processed after the sputtering process is returned to the parallel plate type etching apparatus, and is subjected to RIE processing under the same conditions as the first etching process, using the resist film 18 as a mask. A second etching process is performed to remove the PSG film 17^ exposed at the bottom of the non-penetrating wire bonding window 20a, the second interlayer insulating film 15 below it, and the CVD-3iO□ film 13 below it. is removed to complete a penetrating wire bonding window 20 that exposes the upper surface of the bonding pad I2.

なお、上記実施例により形成されたワイヤボンディング
用窓20内に露出するポンディングパッド12の表面に
は、通常行われる顕微鏡検査によってワイヤボンディン
グに支障を生ずるようなポリマーの付着は殆ど検出され
ていない。
It should be noted that on the surface of the bonding pad 12 exposed within the wire bonding window 20 formed in the above embodiment, almost no polymer adhesion that would interfere with wire bonding was detected by a commonly performed microscopic examination. .

なおまた、第2次のエツチング処理でエツチングする絶
縁膜は2次エツチングに際してのポリマーの生成量を少
なくして2次エツチングにおけるポンディングパッド上
の汚染を回避するために可能な限り薄いことが望ましく
、従ってエツチングに際しての基板内、基板間のエラチ
ングレー1−のばらつきが少なければ、上記実施例にお
&Jる1次エツチングにおいて、第2の層間絶縁膜15
の」−層部を合わせてエツチング除去しても差支えない
Furthermore, it is desirable that the insulating film etched in the second etching process be as thin as possible in order to reduce the amount of polymer generated during the second etching and to avoid contamination on the bonding pad during the second etching. Therefore, if there is little variation in the etching gray 1- within the substrate and between substrates during etching, the second interlayer insulating film 15 can be
There is no problem even if the layers are removed by etching.

なおこの際エツチングレートのばらつきによって、第1
次エツチングのみで部分的に貫通したワイヤボンディン
グ用窓が形成されることは避けなければならない。
At this time, due to variations in etching rate, the first
It must be avoided that a partially penetrating wire bonding window is formed only by subsequent etching.

上記実施例においては、本発明の方法をワイヤボンディ
ング用開孔の形成に用いた場合について説明したが、本
発明の方法は通常の配線コンタクト窓の形成にも勿論適
用される。
In the embodiments described above, the method of the present invention is used to form a wire bonding hole, but the method of the present invention can of course also be applied to the formation of a normal wiring contact window.

〔発明の効果〕〔Effect of the invention〕

以上説明のように本発明によれば、ワイヤボンディング
用窓内に露出するポンディングパッドの表面は、ポリマ
ー等の堆積膜が形成されない清浄な面となるので、熱圧
着等によりボンディング1 2 パッド面に固着される金等のボンディングワイヤのボン
ディング強度は十分に保証され且つそのばらつきも抑え
られて、ボンディングの信頼性が確保される。従って本
発明はLSI等の歩留りゃ信頼性の向上に有効である。
As described above, according to the present invention, the surface of the bonding pad exposed within the wire bonding window is a clean surface on which no deposited film of polymer or the like is formed. The bonding strength of the bonding wire made of gold or the like fixed to the substrate is sufficiently guaranteed and variations thereof are suppressed, thereby ensuring the reliability of the bonding. Therefore, the present invention is effective in improving the yield and reliability of LSIs and the like.

7はポリマー堆積膜(重合物質)、 8はアルゴン(Ar)粒子 を示ず。7 is a polymer deposited film (polymerized substance); 8 is argon (Ar) particle Not shown.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(C)は本発明の原理説明用工程断面図
、第2図(a)〜(C)は本発明の方法の一実施例の工
程断面図、 第3図(a)〜(t))は従来方法の工程断面図である
。 図において、 1は層間絶縁膜、 2はポンディングパッド(導電性基体)、3は被覆絶縁
膜(絶縁膜)、 4はフォトレジスト膜(レジスト)、 5はエツチング用開孔、 6は貫通ボンディング用窓(開孔)、 6aは未貫通ボンディング用窓(未貫通の開孔)、3 4 25 4足来オfジノ(の工1づ乙θ’−’Tr五シβ七]惰 霞 126−
Figures 1 (a) to (C) are process sectional views for explaining the principle of the present invention, Figures 2 (a) to (C) are process sectional views of an embodiment of the method of the present invention, and Figure 3 (a). ) to (t)) are process cross-sectional views of the conventional method. In the figure, 1 is an interlayer insulating film, 2 is a bonding pad (conductive base), 3 is a covering insulating film (insulating film), 4 is a photoresist film (resist), 5 is an etching hole, and 6 is a through bonding. 6a is an unpierced bonding window (unpierced hole), 3 4 25 −

Claims (1)

【特許請求の範囲】[Claims]  導電性基体(2)上の絶縁膜(3)に、レジスト(4
)をマスクにしてリアクティブイオンエッチングにより
該導電性基体(2)面を表出する開孔(6)を形成する
に際して、該リアクティブイオンエッチングにより該絶
縁膜(3)に未貫通の開孔(6a)を形成する第1次エ
ッチング工程と、該レジスト(4)を残したままアルゴ
ンスパッタ処理を行って該未貫通開孔(6a)の内面に
付着している重合物質(7)を除去するアルゴンスパッ
タ工程と、該レジスト(4)をマスクにしてリアクティ
ブイオンエッチングにより該絶縁膜(3)の未貫通開孔
(6a)を貫通させ開孔(6)を形成せしめる第2次エ
ッチング工程とを有することを特徴とする半導体装置の
製造方法。
A resist (4) is applied to the insulating film (3) on the conductive substrate (2).
) is used as a mask to form an opening (6) exposing the surface of the conductive substrate (2) by reactive ion etching. (6a) and the polymer substance (7) attached to the inner surface of the non-through hole (6a) is removed by performing argon sputtering while leaving the resist (4). a second etching step of penetrating the non-through holes (6a) of the insulating film (3) to form holes (6) by reactive ion etching using the resist (4) as a mask; A method for manufacturing a semiconductor device, comprising:
JP6154490A 1990-03-13 1990-03-13 Manufacture of semiconductor device Pending JPH03262122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6154490A JPH03262122A (en) 1990-03-13 1990-03-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6154490A JPH03262122A (en) 1990-03-13 1990-03-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03262122A true JPH03262122A (en) 1991-11-21

Family

ID=13174170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6154490A Pending JPH03262122A (en) 1990-03-13 1990-03-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03262122A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0689883A (en) * 1992-09-08 1994-03-29 Sony Corp Method of forming connecting hole
KR980006179A (en) * 1996-06-24 1998-03-30 김주용 How to remove metal pad stain
US6750149B2 (en) 1998-06-12 2004-06-15 Matsushita Electric Industrial Co., Ltd. Method of manufacturing electronic device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0689883A (en) * 1992-09-08 1994-03-29 Sony Corp Method of forming connecting hole
KR980006179A (en) * 1996-06-24 1998-03-30 김주용 How to remove metal pad stain
US6750149B2 (en) 1998-06-12 2004-06-15 Matsushita Electric Industrial Co., Ltd. Method of manufacturing electronic device
US6960531B2 (en) 1998-06-12 2005-11-01 Matsushita Electric Industrial Co., Ltd. Method of manufacturing electronic device

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