JPH03261376A - Power converter system - Google Patents

Abstract

PURPOSE:To improve the reliability of a system by a method wherein two self-exciting converters which are provided on both the sides of a DC intermediate coupling circuit are controlled together by a controller. CONSTITUTION:Two sets of self-exciting power converters 3 and 5 are provided on both the sides of a DC intermediate coupling circuit 4 and a controller 10 which controls both the power converters 3 and 5 with pulse width control is provided. The first power converter is a three-phase converter 3 composed of six switching devices 31-36. The second power converter is a three-phase inverter 5 also composed of six switching devices 51-56. The controller is a single-chip microcomputer 10 which controls both the converter 3 and the inverter 5 together. If an abnormality is created in a system, a power supply is quickly cut off.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a power converter system composed of two sets of converters with a DC intermediate circuit in between, and particularly relates to a power converter system composed of two sets of converters with a DC intermediate circuit in between. The present invention relates to a power converter system that collectively controls pulse width.

[Prior Art] As a prior art related to a PWM control method for a converter/inverter system, which is a type of conventional self-excited force converter, for example, Japanese Patent Application No. 61-2875 (Japanese Patent Application Laid-open No. 62-287)
Patent Application No. 163579 (Japanese Patent Application No. 163579) describes a technique for independently and efficiently controlling the pulse width of a converter and an inverter using a port that outputs a pulse pattern at high speed built into a one-chip microcomputer. 61=2876 (see Japanese Patent Laid-Open No. 62-163577), a technique related to a method for performing sine wave PWM control of an inverter, Japanese Patent Application No. 10176-1986 (see Japanese Patent Application Laid-Open No. 62-171470) Techniques related to the sine wave PWM control of the converter and the synchronization processing with the power supply voltage described in .

In both of these conventional technologies, the converter and the inverter, which are two self-excited converters, are operated by independent control devices to calculate the output signals, and perform pulse output control.
This is done separately for converters and inverters.

However, these conventional techniques do not give consideration to the reliability of the system.

That is, in this type of power converter system, it is usually necessary to throttle the output of each self-exciting converter when there is an abnormality in the system, for example, when the inverter becomes overcurrent. In addition to the normal command input line, it is necessary to independently provide ports for inputting abnormal signals to the pulse output control device. Furthermore, depending on the failure mode, protection processing must be performed on both converters according to a predetermined procedure.

For this reason, in the conventional technology described above, it is necessary to perform protection processing by transmitting and receiving information via communication lines that connect the respective ports of both converters, and there are multiple control devices themselves, each of which Due to the large number of input lines to the control device, there was room for improvement in the reliability of the overall system in terms of failures and disconnections in the control device itself.

In addition, since the above-mentioned conventional technology controls the converter and inverter independently, it requires a DC reactor with a certain capacity or more in the DC intermediate circuit provided between the converter and the inverter. It has been difficult to miniaturize the circuit and, by extension, the entire power converter system.

On the other hand, as another type of conventional technology related to power converter systems, the technology described in Japanese Patent Application Laid-Open No. 157472/1983 is also known.

This prior art relates to a system in which a thyristor converter, which is a separately excited converter, and an inverter, which is a self-excited converter, are controlled by a control device consisting of a single microprocessor and an interface circuit. In other words, this conventional technology specifically controls the firing angle of the converter during off-peak hours to throttle the output voltage of the converter, and also changes the modulated wave for inverter control accordingly, and compares it with the carrier wave. Create a PWM signal by doing
It attempts to control the inverter.

In this conventional technology, one control device controls two converters, a separately excited converter and a self-excited converter.
It can be said that the system has high reliability in terms of hardware since it requires only a small number of wires for signal input and output.

However, considering the case where the inverter has a short-circuit failure, this conventional technology only has one control device.
Since there is no control delay time caused by handing over the command, processing up to the generation of the converter cutoff command can be carried out smoothly. However, since the power supply side converter is a separately excited converter, instantaneous It is not possible to shut off the power, and it takes time to complete the tightening process.

In other words, in this conventional technology, in the case of an inverter short circuit, if the inverter side has sufficient current interrupting ability, it is sufficient to immediately output an OFF command to the inverter components, but if the inverter side has insufficient current interrupting ability, Since it is not possible to turn off a large current as it is, it is necessary to turn on a negative element to shunt the current and reduce the energy in the intermediate coupling circuit, and then turn off the inverter components. In this case, if the supply of energy from the power converter on the source side to the intermediate coupling circuit is not interrupted promptly, the energy attenuation of the intermediate coupling circuit will not take place immediately and the aforementioned current diversion period will be extended, which will have a negative impact on the components. give.

As described above, the conventional technology in which a single control device controls a plurality of power converters including separately excited converters has improvements in terms of system protection.

[Problems to be Solved by the Invention] The above-mentioned prior art is a PW using a sine wave of a self-excited converter alone.
The M control method is related to the cooperative operation of the PAM control method of separately excited converters and the PWM control method of self-excited converters, and can achieve the effect of reducing noise, but it depends on the type of power converter. , no consideration was given to the reliability of the entire power converter system, including the configuration of the control device, and the miniaturization of the DC intermediate circuit, resulting in poor reliability of the entire power converter system and making it difficult to miniaturize the entire system. It has some problems.

An object of the present invention is to provide a power converter system that solves the problems of the prior art, improves system reliability, and downsizes the DC intermediate circuit to make the entire system compact. It's about doing.

[Means for Solving the Problems] According to the present invention, the object is to provide two self-excited power converters,
This is achieved by providing one control device that controls the pulse width of these converters, and by synchronously controlling the two self-exciting converters.

[Operation] The self-excited power converter on the power supply side operates according to commands from the control device.
In the event of a system abnormality, it operates to immediately cut off the power supply. As a result, the power supply side converter can quickly shut off the power, and a highly reliable power converter system can be realized with a simple control device configuration using one control device.

In addition, by synchronously controlling the two self-excited power converters, the necessary power can be immediately sent from the power converter on the power source side to the power converter on the load side, so the DC reactor in the DC intermediate circuit can be reduced. The capacity can be
The entire system can be downsized.

[Embodiments] Hereinafter, embodiments of the power converter system according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In Figure 1, 1 is a three-phase AC power supply, 2.6 is a capacitor for overvoltage suppression, 3 is a current source converter section, and 31
- 36 are transistors constituting the main switching elements, 4 is a DC reactor, 5 is a current source inverter section, 5
1 to 56 are transistors constituting the main switching elements, 7 is an induction motor shown as an example of a load, 8 is a DC current detector, and 9 is a comparator that compares the primary current command i- and the feedback current value i. , 10 is a one-chip microcomputer for supplying pulse patterns (control signals) to the transistors 31 to 36, and 51 to 56, 12 is a terminal to which the primary current command i- is supplied, and 13.14 is given to the inverter control system. Terminal 15 is a signal line to which a frequency command ω- and zero phase commands are supplied, and a signal line for inputting a signal for synchronizing the power supply.

The one-chip microcomputer 10 includes an input port 101, an internal bus 102, a ROM 103 that stores programs, a pulse width data table, etc., a RAM 104 that is used as a time memory and a register, and an ALU I O5 that executes calculations and the like.
, an event setting register 107 that sets the event necessary to output a control signal consisting of a predetermined pulse pattern (event) to the output port 106, and a time setting register 108 that sets the time to enable this event. , a holding register 109 that connects and holds the contents of both setting registers 107 and 108, an associative memory 110 that sequentially and cyclically stores several sets of setting data set in the second holding register 109, and an actual time. a timer 111 that outputs the time, a comparison unit 112 that compares the time set by the timer 111 with the content of the set time in the associative memory 110, and generates an output when they match;
Receives a trigger from the port 106 and outputs the set event.
The controller is configured to include an execution controller 113 and the like for output control.

Next, the operation of this embodiment will be explained.

FIG. 2 is a schematic flowchart for controlling the operation of an event calculation processing program Fl 000 in the one-chip microcomputer 10 for determining an event to be generated in the converter port 106, that is, an event for the converter out of the pulse pattern.

(1) First, the output current deviation Δi of the converter is taken in from the analog-to-digital conversion port of the input ports 101. Of course, in this case, the 18 current commands are taken in from the digital port, and the feedback current itself is transferred to the analog
The deviation signal may be calculated inside the microcomputer by taking it in from the digital conversion port (step FIOIO).

(2) Find the conduction rate γ and phase PH of the converter, which is the first power converter, corresponding to the current deviation Δi. The conduction rate γ and the phase PH can be determined from predetermined characteristics as shown in FIG. 3, an example of the relationship therebetween (step F1020).

(3) Next, the total phase θtc on the converter side is calculated from the relationship θtc=ΣωC×Δtc×PH. Here, 00 is the frequency of the power supply connected to the converter, and Δtc is the reciprocal of the switching frequency of the switching elements 31 to 36 of the converter (step F1030).
.

(4) With respect to the total phase θtc obtained in step F1030, determine the mode in which switching elements of the transistors 31 to 36 should each be set to N10FF during ΔtC. This mode has an electrical angle of 3
60″′ is divided into 6 modes every 60°, and depending on the overall phase etc., this time it is decided which mode it corresponds to, and the purpose is to select the switch element to be 0N10FF and find its order. Although a detailed explanation will be omitted here, the above-mentioned Japanese Patent Application No. 10176/81
The details are described in Japanese Unexamined Patent Publication No. 171470/1983 (Step F1040).

(5) Reference value of two pulses to be supplied to the DC intermediate circuit according to the total phase θtc ”-+al t2Hu!c
(1,=Δtc-sin(θtc-240''), ta
c=Δtc-sinθtCI T-se=Δtc t
Let-t 2e) is calculated. This T+ Ic+
tle, T, and 3a are reference values when one conduction rate command is the maximum value, and the values actually used in converter control are:
Data is processed and determined by the process of step F1060, which will be described next (step F1050).

(6) Pulse reference value t 1al calculated by F1050
j! For e+f+je, the pulse width is processed using the conduction rate γ. In other words, jle"7 books・L I
e.

jme”γ訃tley u3e”Δtc-the
-j2c is calculated to find the pulse width processed by the conduction rate γ. Here, the periods tle' and tRe' are the power feeding mode from the AC power source to the DC reactor, and t. The period ' is a recirculation mode in which energy is not supplied from the power source and the energy stored in the reactor is recirculated (step F1060).

Through the above processing, data used for 0N10FF control of the converter, which is an example of the first converter (data indicating which switch element is to be turned 0N10FF and when), has been calculated.

FIG. 4 shows an inverter 3 as an example of a second power converter.
12 is a flowchart illustrating the operation of event calculation processing Fil○0 used for control of FIG.

(1) First, frequency command ω-1 used for inverter control
Load θ phase commands. This command value may be obtained by directly taking in a digital quantity or by converting an analog quantity from analog to digital (step FIIIO).

(2) Calculate the total phase θti from the relational expressions θti=Σω−·Δti+θ (step F1120).

(3) Depending on the value of the overall phase θti, the transistor 51
It is determined which switch elements according to .about.56 must each be turned ON10FF during Δti. Although a detailed explanation thereof will be omitted here, the details are as follows:
(Refer to Publication No. 7) (Step F1130
).

(4) Pulse width trl, t, t (t++=Δti−sin(θ
ti−240°), t2+=Δti−sinθti), and the pulse width ta+(=Δti t++ 12
+) is also calculated here (step F1140).

By executing the inverter event calculation process FI100 described above, the inverter pulse width (that is, the time of event change) and the event (which switch element should be set to 0N10 FF) are determined.

FIG. 5 shows a process F2 in which the two items obtained as described above are set in the associative memory 110 for output port control.
2 is a flowchart illustrating the operation of 000.

First, in the process of step F2100, it is determined whether or not the necessary event settings and time settings have been completed for the 12 transistors that make up the converter and inverter.
If so, the corresponding event is set in the process of step F2200, the time of event change is set in the process of step F2300, and this setting process is ended.

FIG. 6 shows the three tasks mentioned above (FlooO.

FIG. 3 is a diagram showing an example of startup timing of FIloo, F2000).

In one embodiment of the present invention, as can be seen from FIG. 6, events for the converter and the inverter are first calculated,
Thereafter, the event is sequentially set in the register to obtain a pulse pattern. Here, suppose that the period Δt of the event setting process is the period Δt of the event calculation process.
c, if equal to Δti, the switching frequencies of the converter and inverter are equal and the frequency is 1/Δt
(Hz).

The power converter system according to one embodiment of the present invention configured as described above can provide the following special effects. In other words, since two self-exciting converters are collectively controlled using one one-chip microcomputer, processing such as emergency shut-off can be performed easily.
This can be done quickly.

This will be explained below with reference to the drawings.

FIG. 7 is a schematic flowchart illustrating the operation of the emergency cutoff processing program F3000.

When this emergency shutdown processing program F3000 receives an interrupt due to an abnormality detected by an abnormality detector (this hardware is omitted in Figure 1), the emergency shutdown processing program It is a task that is started as high.

(1) When this task is activated, the switch that forms the short-circuit phase of the converter (for example, if this activation is performed in the interval where the total phase is 60° from Oo, that is, the interval of mode 1, the switch 32 and 35) are set in registers 107 and 108, and by turning these switches ON, the energy supply from the power supply side to the power converter system is cut off (step F3010).
.

In this example, the power converter system is a current-source inverter-converter system, and from the perspective of suppressing the generation of overvoltage due to current loop loss, the energy supply is cut off by turning on the switch to form a short circuit mode.
If overvoltage suppression means are fully equipped, all switches may be turned off to cut off the energy supply.

In addition, if the power converter system is a voltage source inverter system, energy supply can be stopped by turning off the switch of the converter, and if the current side converter is a chopper, by turning off the chopper, the energy supply can be stopped. It will go into supply cutoff mode. This is because the converter is of a self-excitation type, so that the switch can be turned ON/OFF with almost no delay, regardless of conditions such as the phase of the power supply.

(2) Next, set a command to immediately turn on the switch element (the element that shorts the upper and lower arms) that puts the inverter in short-circuit mode, and immediately turn on the switch element.
In order to consume the energy of the reactor 4, a command is generated to connect a resistor (not shown) to both ends of the reactor 4 via a thyristor or the like. The short circuit mode in this case is also
Similar to the short-circuit mode of the converter described above, this takes into consideration the occurrence of overvoltage due to current loop loss, and if the overvoltage countermeasures are sufficient, short-circuit mode will not occur and immediate OF
It is sufficient to generate the F command to all switch elements (step F
3020).

(3) Next, in order to prevent the event setting process etc. from being performed again and a schedule in which the switch is turned ON, restarting the schedule process is prohibited and the emergency shutdown process is ended (step F3030 ).

As mentioned above, in the embodiment of the present invention, two self-excited converters using switches with a self-shutoff function are collectively controlled by a one-chip microcomputer, which is a single control device.
It is possible to quickly tighten the system in the event of an abnormality, and the system can be protected quickly.

In the embodiments of the present invention described above, an example was explained in which a transistor was used as a switching element with a self-shutoff function, but the present invention can also be applied to cases where a GT○ thyristor, a thyristor with a commutation circuit, etc. are used. This makes it possible to increase the capacity of the power converter system. Furthermore, it is also possible to use an IGBT% FET or the like, and in this case, another effect of enabling high frequency switching of the device can be obtained.

Further, in the above-mentioned emergency shutoff process in the embodiment of the present invention, in the process of step F3010, a command for turning on the switch elements to form a short circuit mode is set in the registers 107 and 108, and the execution controller 113
Although the switch elements were controlled to turn on according to the schedule, if a microcontroller with a function to directly write to the output port 106 is used as a control device, it is possible to write the ON command directly to the output port without going through a register. , it is possible to perform high-speed shutoff.

Further, one embodiment of the present invention shown in FIG.
Since the second power converter is a three-phase converter, there are six switching elements making up the converter, and since the second power converter is a three-phase inverter, there are also six switching elements making up the inverter. have. Therefore, a total of 12 output ports are required for the microcomputer 10, but if the converter is a chopper that receives DC power, the chopper will have one switching element, and if the inverter is single-phase, the inverter will have one switching element. There are 4 switch elements that make up the
If a microcomputer having a total of five output ports is used as a control device, a highly reliable system equivalent to the embodiment of the present invention shown in FIG. 1 can be constructed.

Furthermore, in the example of task activation shown in FIG. 6, the event setting process F2000 is replaced with the event calculation process FIO00 and
The switching frequency of the two power converters can be easily managed by sharing the same frequency with oo at regular intervals. By increasing the ripple component of the power applied to the load, the ripple component of the power applied to the load can be made to have a high frequency and a small value, so another effect of reducing motor noise can be obtained.

Further, in one embodiment of the present invention shown in FIG.
Although the one-chip microcomputer 10 has a built-in CPU core and a plurality of output ports, the present invention may have a configuration in which these are configured as separate chips and connected by an external bus.

Even in this case, the effects of the present invention are not impaired because they are under the control of a common CPU core.

In addition, when separating the CPU core and output ports as mentioned above, the combination of an independent I10 chip with a large number of terminals as an output port and a general-purpose microcontroller that does not have very powerful input/output ports, etc. This makes it possible to eliminate restrictions regarding the number of output port bins when configuring the control device 10, and it is possible to obtain the effect that inexpensive general-purpose products can be used.

FIG. 8 is a flowchart explaining the operation of event calculation processing in another embodiment of the present invention, and FIG.
1-36. It is a figure which shows the state of 0N10FF of 51-56.

Another embodiment of the present invention has the same hardware configuration as the above-described embodiment shown in FIG. 1, but differs in its control method.

That is, another embodiment of the present invention is based on the event calculation process F10 for the converter in the embodiment of the present invention described above.
0O and the event calculation processing FI100 for the inverter are connected and performed simultaneously. Therefore, since the flow shown in FIG. 8 is a combination of the flow shown in FIG. 2 and the flow shown in FIG. 4 described above, the explanation thereof will be omitted here.

In this other embodiment of the present invention, the two event calculation processes are performed in conjunction as described above, so the event setting process F
It is possible to set two event calculation processes to be performed immediately before 2000, and in addition to being able to set the latest pulse width data as an event,
This produces special effects as shown below.

This special effect will be explained using FIG. 9. In FIG. 9, 531-836. S51 to S56 are switch elements 3 constituting a converter and an inverter, respectively.
1 to 36. 0N supplied from the microcontroller to 51 to 56
10FF is the F command signal.

First, converter command signals S31 to S36 will be explained.

FIG. 9 shows the case where the total phase θtc obtained in step F4030 of FIG.
Shown as an example. Therefore, regarding the positive arm, at the beginning of the Δtc section, S33 is turned ON,
Next, S31 is turned on, and finally S32 is turned on. On the other hand, when looking at the negative side arm, only S35 has Δ
During the period of tc, it is always in the ON state, S34, S36
is always in the OFF state.

The relationship between the pulse widths is that 'Llc' is the widest,
Next is Fe' and then tle' (when the conduction rate of 7 lines is relatively large). Furthermore 1. (t].'10t2°') is the power supply section from the power supply l to the reactor 4, and tle' is the section where the power supply is cut off and the energy of the reactor 4 is circulated.

On the other hand, regarding the pulse pattern given to the inverter,
An example is shown in which the total phase θt1 exists in mode 1 and is close to 0°. The order of turning on is S53, 551. S
52, and the section of (lt+t+tz) is motor 7
The section t31 is a recirculation section in which energy is bypassed without being supplied to the electric motor.

In another embodiment of the present invention, S53. S55
The rise of S33. Collective control is performed to synchronize with the rising edge of S35. The reason is that the energy supply section from the converter to the inverter (1+.'+tzc')
, the energy supply section from the inverter to the electric motor (t,
This is because, by wrapping as much as possible (l+ta+), it is possible to reduce the capacity of the reactor 4, which is a DC intermediate circuit that functions to supply energy to the inverter in the freewheeling section of the converter.

That is, when the inverter side needs to supply energy to the motor, the DC intermediate circuit becomes the energy supply source, and the converter serves as the energy supply source to the DC intermediate circuit. Therefore, if the capacity of the DC intermediate circuit is sufficient, the timing of energy supply from the converter to the DC intermediate circuit, etc. will be irrelevant to the control of the inverter.

In the embodiment of the present invention, the converter and inverter are synchronized by going as far as the power supply timing of the PWM signal for controlling the switch elements, so that the output energy of the converter can be used as is as energy for the inverter. , it is possible to reduce the capacity of the reactor of the DC intermediate circuit as an energy storage function.

In addition, in the description of other embodiments of the present invention described above, the case where the overall phase is close to Oo was explained as an example, so the mode No.
becomes 1, and on the converter side, the switch element is turned off.
The order of the signals to be N is S33. Although S31 and S32,
Of course, in this order, if the overall phase changes, the mode No.
also changes, and the order of this 0N10FF also changes. however,
○Even if the element that performs N10FF changes due to a change in mode number, the relationship between the supply section and the reflux section will not change, so the same applies when the overall phase is not only around 0° but also other values. effect can be obtained.

Furthermore, in FIG. 9, even if the order of signals that turn on the switch elements is S32 → S33 → S31, where the freewheeling section comes before the power supply section, the same order will be applied to the inverter side. If they are combined in this manner, the relationship between the supply section and the reflux section by the converter and inverter will not be disrupted, and the same effect can be obtained.

Furthermore, the power supply sections should be overlapped, taking into consideration the operation delay when switching elements ○N/○FF, such as by setting the falling time constant on the converter side to be slower than the falling time constant on the inverter side. By doing so, the gap between the two can be reduced, and the power supply section on the inverter side can be
6, in consideration of current attenuation, set tz+
It is sufficient to make the interval wider than the initially calculated value to compensate for the attenuation of the current.

Further, in other embodiments of the present invention, it is sufficient to control two converters in synchronization, so there is no need to limit the CPU core to one as in the hardware configuration shown in FIG. , it is sufficient if the 0N10FF control of the converter and inverter can be controlled synchronously using two CPU cores. As a means for this purpose, there is a means for synchronizing the microcomputers by using a common clock, or by issuing an interrupt between the microcomputers.

In this way, when configured with multiple microcontrollers, the processing can be divided between two CPUs, so there is no need to use a very high-end microcontroller, and an inexpensive one can be used. can be obtained.

Next, a description will be given of still another embodiment of the present invention in which the DC intermediate circuit can be further downsized by making the freewheeling section on the converter side not overlap with the power feeding section on the inverter side.

In this example, the conductivity of the seven lines on the converter side is set to a value slightly larger than the initially calculated value, and the power supply section is expanded by setting tle' to lc'). Introducing conduction rate control such as process F1060 shown in Fig. 2 to the control, narrowing the power supply section on the inverter side and correcting the point where the conductivity was increased on the converter side, and reducing the amount of power supplied to the motor. The condition is the same as the original state, and the reflux section of the converter does not overlap the power supply section of the inverter. In this way, the reactor, which is a DC intermediate circuit, can be further downsized.

As an effect of the above-described embodiment, the reduction in the capacity of the reactor in the DC intermediate circuit has been described, but the following effect also occurs due to the reduction in the capacity of the reactor.

In other words, in the current source converter/inverter system shown in Figure 1, if the DC reactor 4 is made smaller, the level of overvoltage that occurs during power outages will also be lowered, and the protection circuit to suppress this will be simple. Therefore, it is possible to improve the reliability of the entire system.

[Effects of the Invention] As explained above, according to the present invention, two self-exciting converters sandwiching a DC intermediate coupling circuit can be collectively managed by a control device, so that the self-exciting converter can be quickly and easily controlled. The combination of quick response and simple configuration of the control device results in the ability to construct a power converter system with high reliability.

Furthermore, since the two self-exciting converters can be controlled synchronously, the capacity of the DC intermediate circuit accelerator can be reduced, and the entire device can be downsized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, FIGS. 2 to 7 are diagrams for explaining the operation of one embodiment of the present invention, and FIGS. 8 and 9 are diagrams showing other embodiments of the present invention. FIG. 3 is a diagram for explaining the operation of the embodiment. l...Three-phase AC power supply, 2.6...Capacitor for overvoltage suppression, 3...Current source converter section, 31-36...Main Transistor constituting a switching element, 4... DC reactor, 5... Current source inverter section, 51-56.
...Transistor constituting the main switching element, 7...Induction motor, 8...Direct current detector, 9...Comparator, 10... ...
One-chip microcomputer, 101...Input port,
102...Internal bus, 103...RO
M, 104...RAM, 105...A
LU, 107...Event setting register, 108...
...Time setting register, 109...Holding register, 110...Associative memory, 111...
...Timer, 112...Comparison section, 113...
...Execution controller 113゜Fig.

Claims (1)

[Claims] 1. A first self-exciting converter that receives an AC power source or a DC power source and converts it into DC, a DC intermediate circuit connected to the output of this converter, and this DC intermediate circuit. a second self-exciting converter connected to the output of the converter for exchanging direct current to alternating current; A power converter system comprising a control device and collectively controlling on/off switching elements constituting the first and second self-excited converters. 2. The output port section includes a timer that increases or decreases at fixed time intervals, a first register that sets the time at which the output level of the output terminal is to be changed from the microprocessor, and a second register that sets the output level. and the first
A comparator that compares data between a register value and a timer value, and an output control unit that outputs the contents of a corresponding second register from an output terminal when the comparison results match. A power converter system according to claim 1, characterized in: 3. The on/off control device is a one-chip microprocessor constituted by one CPU core and a pulse output port section incorporating a plurality of comparators, or The power converter system according to item 2. 4. The power converter system according to claim 3, wherein the number of output terminals of the pulse output port section is at least five or more. 5. A patent claim characterized in that the on/off control device has a configuration in which a microprocessor with a built-in CPU core and an I/O chip with a built-in pulse output port section are connected via an external bus. 2. The power converter system according to claim 1 or 2. 6. Claims characterized in that the microprocessor pairs time information and output level information and sets these pieces of information in the first register and the second register at fixed time intervals. The power converter system according to one of items 2 to 5. 7. The first self-excited converter outputs energy greater than the energy that the second self-excited converter should output, and
7. The power converter system according to claim 1, wherein the self-exciting converter circulates surplus energy from the first self-exciting converter. 8. A first converter that takes AC power or DC power as input and converts it into DC, a DC intermediate circuit connected to the output of this converter, and a DC intermediate circuit connected to the output of this intermediate circuit to convert DC to AC. A power converter system comprising a second converter to be replaced, the power converter system comprising a pulse width control device that synchronously performs pulse width control on the first and second converters. 9. A energization mode period from the second converter to the load connected to the second converter overlaps with a energization mode period from the first converter to the DC intermediate circuit;
9. The power converter system according to claim 8, wherein the power converter system performs pulse width control. 10. An operation delay time between a control signal for the first converter and the output of the first converter, and a time delay between the control signal for the second converter and the output of the second converter. The ninth aspect of the present invention is characterized in that pulse width control is performed so that the overlapping occurs in consideration of the operation delay time between
Power converter system as described in Section. 11. The pulse width control device for controlling the first converter and the second converter is characterized by comprising one microprocessor and a pulse signal output port section connected to this microprocessor. A power converter system according to claim 8, 9 or 10. 12. Claim 1, wherein the microprocessor and the pulse signal output port section are configured in the same chip and are coupled to each other via an internal bus.
The power converter system according to item 1. 13. The power converter system according to claim 11, wherein the microprocessor and the pulse signal output port section are mutually coupled via an external bus outside the chip. 14. The pulse width control device includes two separate microprocessors for controlling each of the first converter and the second converter, and a pulse signal output port section connected to these microprocessors. The power converter system according to claim 8, 9, or 10, characterized in that it is configured by: 15. The power converter system according to claim 14, wherein the operating clock signal of at least one of the two microprocessors and the pulse signal output port section is common. 16. The first converter outputs more energy than the second converter should output, and the second converter recirculates the surplus energy from the first converter. Claims 8 to 1, characterized in that
The power converter system according to item 1 of item 5. 17. The output port section includes a timer that increases or decreases at fixed time intervals, a first register that sets the time at which the output level of the output terminal is changed from the microprocessor, and a second register that sets the output level. and a comparator that performs data comparison between the first register value and the timer value, and an output control unit that outputs the contents of the corresponding second register from the output terminal when the comparison results match. A power converter system according to one of claims 8 to 16, characterized in that: 18. Claims characterized in that the microprocessor pairs time information and output level information and sets these pieces of information in the first register and second register at fixed time intervals. The power converter system according to one of items 11 to 17.