JPH03261156A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03261156A JPH03261156A JP5931890A JP5931890A JPH03261156A JP H03261156 A JPH03261156 A JP H03261156A JP 5931890 A JP5931890 A JP 5931890A JP 5931890 A JP5931890 A JP 5931890A JP H03261156 A JPH03261156 A JP H03261156A
- Authority
- JP
- Japan
- Prior art keywords
- line
- chip
- resistance value
- resistance
- measuring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 238000007689 inspection Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 2
- 230000007547 defect Effects 0.000 description 4
- 238000011179 visual inspection Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、半導体素子か形成された半導体基板のチッ
プ上の外周域に抵抗ラインを設けると共に、この抵抗ラ
インの抵抗値を測定するための測定器接続用パットを設
け、上記抵抗ラインの抵抗値を測定することにより、半
導体チップの外観検査を容易に行なうことのてきる半導
体装置に関するものである。Detailed Description of the Invention (Industrial Application Field) The present invention provides a resistance line in the outer peripheral area on a chip of a semiconductor substrate on which a semiconductor element is formed, and a method for measuring the resistance value of this resistance line. The present invention relates to a semiconductor device in which the external appearance of a semiconductor chip can be easily inspected by providing a pad for connecting a measuring device and measuring the resistance value of the resistance line.
（従来の技術）
従来のこの種の半導体装置の例を第４図に示す、同図に
おいて、（１）は半導体チップて、該半導体チップ上に
は例えばトレイン電極（２）、ソース電極（３）および
ゲート電極（４）を含む半導体素子（１０）か形成され
ている。(Prior Art) An example of a conventional semiconductor device of this type is shown in FIG. ) and a gate electrode (4) are formed.
（発明か解決しようとする課８）
従来の半導体装置は上記のように構成されているのて、
半導体チップ（１）の周囲に図示のような例えばひび割
れ（７）や欠け（８）か存在するか否かを外観検査時に
目視によりチエツクし、ひび割れや欠は等の欠損か存在
する場合は、これか許容範囲内にあるか否かを作業員の
目視検査により判定していた。このため、検査時間が゛
長くかかり、また良否の判定基準か作業員の主観により
大きく左右されるという問題があった。(Invention or Problem Solving Section 8) Since the conventional semiconductor device is configured as described above,
Visually check whether there are any cracks (7) or chips (8) as shown around the semiconductor chip (1) during the visual inspection, and if there are defects such as cracks or chips, Visual inspection by workers was used to determine whether this was within the allowable range. For this reason, there was a problem that the inspection time was long and the criteria for determining pass/fail were largely influenced by the subjectivity of the worker.
この発明は上記のような問題点を解消するためになされ
たものて、半導体チップの外観の良否の判定基準を明確
に均一化すると共に、外観検査の作業効率を向上させる
ことのできる半導体装置を得ることを目的とする。This invention has been made to solve the above-mentioned problems, and provides a semiconductor device that can clearly and uniformly standardize the criteria for determining whether the appearance of semiconductor chips is good or bad, and can improve the work efficiency of appearance inspection. The purpose is to obtain.
（ｆａｌｌを解決するための手段）
この発明による半導体装置は、半導体素子が形成された
半導体チップの表面上の外周域に所定の大きさの抵抗値
をもった抵抗ラインを形成し、さらに上記半導体チップ
の表面上に上記抵抗ラインに接続され、該抵抗ラインの
抵抗値を測定するための測定器接続用パッドを設けたも
のである。(Means for Solving Fall) A semiconductor device according to the present invention includes a resistance line having a predetermined resistance value formed in an outer peripheral area on the surface of a semiconductor chip on which a semiconductor element is formed, and further comprising a resistance line having a predetermined resistance value. A measuring device connection pad is provided on the surface of the chip to be connected to the resistance line and to measure the resistance value of the resistance line.
（作 用）
この発明の半導体装置によれば、半導体チップの周囲に
第４図に示すようなひび割れ（７）や欠け（８）か生じ
た場合、抵抗ラインの抵抗値が変化するから、接続用パ
ッド間の抵抗値を測定することにより、半導体チップの
良否を直ちに判定することができる。(Function) According to the semiconductor device of the present invention, when cracks (7) or chips (8) as shown in FIG. 4 occur around the semiconductor chip, the resistance value of the resistance line changes, so that the connection By measuring the resistance value between the pads, the quality of the semiconductor chip can be immediately determined.
（実施例）
第１図はこの発明の半導体装置の第１の実施例を示す図
で、第４図に示す従来の装置と同様に半導体チップ（１
）の表面上には例えばトレイン電極（２）、ソース電極
（３）およびゲート電極（４）を含む半導体素子（１０
）か形成されている。半導体チップ（１）表面には、そ
の外周から一定の距離離れて所定の抵抗値をもった抵抗
ライン（５ａ）か形成されている。また、半導体チップ
（１）の対角線位置には、上記抵抗ライン（５ａ）に接
触して測定器接続用パッド（６ａ）、（６ａ）か形成さ
れている。(Embodiment) FIG. 1 is a diagram showing a first embodiment of the semiconductor device of the present invention. Similar to the conventional device shown in FIG.
) is provided with a semiconductor element (10) including, for example, a train electrode (2), a source electrode (3), and a gate electrode (4).
) is formed. A resistance line (5a) having a predetermined resistance value is formed on the surface of the semiconductor chip (1) at a certain distance from its outer periphery. Furthermore, measuring device connection pads (6a), (6a) are formed at diagonal positions of the semiconductor chip (1) in contact with the resistance line (5a).
上記のような半導体装置において、半導体チップ（１）
の周囲にひび割れや欠は等の欠損か全く無いか、あるい
は欠損かあっても接続用パッド（６ａ）、（６ａ）間の
抵抗ライン（５ａ）に抵抗値の変化を与えない程度のも
のである場合の上記抵抗ライン（５ａ）の抵抗値を基準
値とすれば、接続用パッド（６ａ）、（６ａ）間の抵抗
値を測定して、その抵抗値か実質的に上記基準値を示し
た場合は、その半導体チップは良品であると直ちに判定
することかできる。In the semiconductor device as described above, a semiconductor chip (1)
There are no cracks, chips, etc. around the pad, or if there is any damage, it is to the extent that it does not change the resistance value of the resistance line (5a) between the connection pads (6a) and (6a). If the resistance value of the resistance line (5a) in a certain case is taken as the reference value, the resistance value between the connection pads (6a) and (6a) is measured, and the resistance value substantially indicates the above reference value. If so, it can be immediately determined that the semiconductor chip is a good product.
一方、第２図に示すように、半導体チップの周囲にひび
割れ（７）や欠け（８）か存在し、そのため、抵抗ライ
ン（５ａ）に欠損か生しると、接続用パッド（６ａ）、
（６ａ）か断線状態になるか、あるいはその間の抵抗値
か上記基準値から大きく変化するから、この半導体チッ
プは外周域に許容範囲を越える欠損が存在し、不良品で
ある判定することがてきる。従って、半導体チップ（１
）の外周域のひび割れ（７）や欠け（８）の許容範囲と
なる位置に抵抗ライン（５ａ）を設け、この抵抗ライン
（５ａ）の接続用パッド（６ａ）、（６ａ）間の抵抗値
を測定、評価することにより、従来は作業員の目視と作
業員の判断によって行なっていた上記半導体チップ（１
）の外観検査による良否を作業員の主観を伴なうことな
く電気的に均一に判定することがてきる。On the other hand, as shown in FIG. 2, if there are cracks (7) or chips (8) around the semiconductor chip, and therefore defects occur in the resistance line (5a), the connection pads (6a),
(6a) or the resistance value changes greatly from the above reference value, so it can be determined that this semiconductor chip has defects exceeding the allowable range in the outer peripheral area and is a defective product. Ru. Therefore, the semiconductor chip (1
) A resistance line (5a) is provided at a position that is within the tolerance range for cracks (7) and chips (8) in the outer peripheral area, and the resistance value between the connection pads (6a) and (6a) of this resistance line (5a) is determined. By measuring and evaluating
) can be electrically and uniformly determined by visual inspection without involving the subjectivity of workers.
なお、第１図に示す実施例ては、半導体チッソ（１）の
表面の外周域に１本の抵抗ライン（５ａ）を設けたか、
第３図に示すように、一定の間隔て２本の抵抗ライン（
５ａ）、（５ｂ）を設け、各抵抗ラインに接続する測定
器接続用パッド（６ａ）、 （６ａ）を設けて判定基準
を２段階にしてもよく、さらに多くの抵抗ラインを形成
して、良品と判定されたものについてランク付けを行な
うようにしてもよい。In the embodiment shown in FIG. 1, one resistance line (5a) is provided in the outer peripheral area of the surface of the semiconductor nitrogen (1)
As shown in Figure 3, two resistance lines (
5a) and (5b), and measuring device connection pads (6a) and (6a) connected to each resistance line may be provided to set the judgment criteria to two levels, and more resistance lines may be formed. It is also possible to rank those determined to be non-defective.
〔発明の効果）
以上のように、この発明によれば、接続用バッド間の抵
抗値を測定することにより、半導体チップの外周域に発
生したひび割れ、欠は等の外観検査を作業員の主観を伴
なうことなく均一な判定基準て電気的に行なうことかて
きるから、外観検査の作業効率を向上させて作業時間を
短縮化することかてき、しかも判定基準の明確化か可能
であるという効果かある。[Effects of the Invention] As described above, according to the present invention, by measuring the resistance value between the connection pads, it is possible to visually inspect the appearance of cracks, chips, etc. occurring in the outer peripheral area of a semiconductor chip by an operator. Since it is possible to conduct the inspection electrically using a uniform judgment standard without having to be accompanied by a process, the work efficiency of visual inspection can be improved and the working time can be shortened, and it is possible to clarify the judgment standard. There is an effect.
第１図はこの発明の半導体装置の第１の実施例の平面図
、第２図は第１図の半導体装置にひび割れや欠は等の欠
損か生した状態を示す平面図、第３図はこの発明の半導
体装置の他の実施例の平面図、第４図は従来の半導体装
置の一例を示す平面図である。
（１）・・・・・半導体チップ、（５ａ）、（５ｂ）・
・・・・抵抗ライン、（６ａ）、（６ｂ）・・・測定器
接続用バッド、（１０）・・・・・半導体素子。FIG. 1 is a plan view of a first embodiment of the semiconductor device of the present invention, FIG. 2 is a plan view showing the semiconductor device of FIG. 1 with defects such as cracks and chips, and FIG. FIG. 4 is a plan view of another embodiment of the semiconductor device of the present invention, and FIG. 4 is a plan view showing an example of a conventional semiconductor device. (1)...Semiconductor chip, (5a), (5b)
... Resistance line, (6a), (6b) ... Measuring device connection pad, (10) ... Semiconductor element.
Claims (1)
外周域に所定の大きさの抵抗値をもった抵抗ラインを形
成し、さらに上記半導体チップの表面上に上記抵抗ライ
ンに接続され、該抵抗ラインの抵抗値を測定するための
測定器接続用パッドを設けたことを特徴とする半導体装
置。(1) A resistance line having a predetermined resistance value is formed in the outer peripheral area on the surface of the semiconductor chip on which the semiconductor element is formed, and is further connected to the resistance line on the surface of the semiconductor chip, and A semiconductor device characterized by being provided with a measuring device connection pad for measuring the resistance value of a resistance line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5931890A JPH03261156A (en) | 1990-03-09 | 1990-03-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5931890A JPH03261156A (en) | 1990-03-09 | 1990-03-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03261156A true JPH03261156A (en) | 1991-11-21 |
Family
ID=13109895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5931890A Pending JPH03261156A (en) | 1990-03-09 | 1990-03-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03261156A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005021586B3 (en) * | 2005-05-10 | 2007-02-01 | Infineon Technologies Ag | Semiconductor chip tested for intact flanks and edges, includes electronic test circuit integrated into semiconductor chip |
| JP2008021864A (en) * | 2006-07-13 | 2008-01-31 | Nec Electronics Corp | Semiconductor device |
-
1990
- 1990-03-09 JP JP5931890A patent/JPH03261156A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005021586B3 (en) * | 2005-05-10 | 2007-02-01 | Infineon Technologies Ag | Semiconductor chip tested for intact flanks and edges, includes electronic test circuit integrated into semiconductor chip |
| JP2008021864A (en) * | 2006-07-13 | 2008-01-31 | Nec Electronics Corp | Semiconductor device |
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