JPH0325798B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a speech recognition device, and in particular, a DP matching circuit used when performing DP (dynamic programming) matching, which is configured to reduce the number of candidates prior to DP matching. The present invention relates to a speech pattern matching circuit that can be used for primary matching.

[Technology background]

A speech recognition device has a large number of standard patterns of words to be recognized (for example, words) in a speech dictionary, matches the input pattern with the standard pattern, and uses the matching distance to determine the recognition result of the standard pattern that is most similar to the input pattern. This pattern matching generally involves
A matching method called DP matching is used to normalize temporal fluctuations in speech. By the way, this DP
Since matching requires a large amount of calculation and takes a long time, a dedicated circuit for performing high-speed matrix operations is generally provided to shorten the matching time.

However, even with this, if the number of registered words increases and the number of recognition increases, the matching time becomes slow and it becomes impossible to satisfy the required performance.

Therefore, multiple DP matching circuits are installed to shorten the matching time, and prior to DP matching, a simple primary matching is performed to reduce the number of candidates, thereby significantly reducing the number of standard patterns for DP matching.

[Conventional technology and problems]

By the way, in this matching for reducing candidates, we convert the parameters for DP matching to create fixed-length parameters for reducing candidates with little information, and then calculate the matching distance by linear matching with a small amount of calculation. Ten
The candidate degree was used as the standard pattern for DP matching.

Conventionally, a method with a small amount of calculation is used for matching for candidate reduction, so a special dedicated circuit is not required, and a microprocessor (MPU) for control is used.
etc. were calculated. However, since the calculation speed of such an MPU is not very fast, the total amount of calculation for reducing the number of candidates is significantly at least compared to DP matching, and since no dedicated matching circuit is used, the matching time for reducing the number of candidates is It became quite large,
It was not possible to save enough time.

[Purpose of the invention]

The purpose of the present invention is to improve the drawback that the calculation for reducing the number of candidates takes a long time as described above.
By adding a function that enables multiple linear matching processes to the DP matching circuit, it is possible to perform candidate reduction matching by using the period when the DP matching circuit does not perform DP matching.
To provide a device that uses a DP matching circuit and can match multiple registered words at once.

[Structure of the invention]

In order to achieve the above object, the speech pattern matching circuit of the present invention includes a first pattern holding means for holding the input pattern, a second pattern holding means for holding the standard pattern, and a first pattern holding means for holding the input pattern and the second pattern holding means for holding the input pattern and the standard pattern. A difference calculation unit that calculates the absolute value difference of parameters, an addition means, and G in different frames.
Multiple linear calculation control for switching between linear calculation and DP calculation in a voice pattern matching circuit that includes at least three data holding means for holding values and a comparison unit that detects the minimum value of these G values. means, first selection output means for outputting either the output of the difference calculation unit or a zero value, second selection output means for outputting one of the data of the three data holding means; A third selection output means is provided for outputting either the output of the selection output means or a zero value, and one of the first pattern holding means or the second pattern holding means holds the input pattern for linear calculation, and the other pattern is held. The means holds a plurality of standard patterns for linear calculations, and in the case of linear calculation control, the plurality of linear calculation control means initially outputs zero from the first selection output means and the third selection output means, Next, the first selection output means outputs the calculated value of the difference calculation section, and the collation cumulative value up to the previous frame of the three data holding means is input to the second selection output means. The input pattern for linear calculations and the plurality of standard patterns for linear calculations are simultaneously linearly matched by selecting the input pattern for linear calculations and controlling the third selection output means to output the output thereof. In the case of control, the plural linear arithmetic control means causes the first selection output means to output the calculated value of the difference calculation section, and the three data holding means input to the second selection output means. The minimum value selected by the comparison section among the inputs is output from the second selection output means, and the third selection output means outputs this, so that the addition means calculates the cumulative value of matching. It is characterized by

[Embodiments of the invention]

Before explaining the present invention in detail based on one embodiment, first, an example of processing of a conventional DP matching circuit is shown in FIGS.
This will be explained based on FIG.

DP (Dynamic Programming) is used to detect the matching path that most closely matches the input audio parameters and registered audio parameters.
Perform time normalized matching using the method. This DP
As shown in Fig. 1, the matching operation is performed by matching the corresponding parts of the registered pattern (standard pattern) and the input pattern using the matching path shown by the solid line M, thereby creating a matching result G that absorbs temporal variations in audio. You can get ₀ .

In order to select corresponding parts in this way, in the DP method, for example, 10 parameters obtained from the input pattern and the registered pattern are represented as a two-dimensional table in the frame direction, as shown in Figure 2, and each parameter is Find the absolute value difference d. FIG. 2 shows an example of this d table.

A value G obtained by accumulating the values of d along the matching path indicates the distance between the input parameter and the standard parameter.

In the DP method, the value of d shown in the d table is obtained by scanning from the starting point in the upper left in the input parameter direction (horizontal direction in Figure 3) according to the calculation conditions for G shown in the following formula. go.

The calculation conditions for G are expressed by the following equation.

G=min [G ₀ +2d, G ₁ +d, G ₂ +d] where
G ₀ , G ₁ , and G ₂ are G at other positions with respect to the frame being calculated (G in FIG. 3), as shown in FIG. As shown in Fig. 3, if the frame currently being calculated is G, the previous G is _G2 , the G of the same frame of the previous calculation result (L in Fig. 3) is _G1 ,
The G before G ₁ is called G ₀ .

G ₀ +2d, G ₁ +d, and G ₂ +d are calculated using the values of G ₀ , G ₁ , and G ₂ and d of the frame, and the one with the smallest value is set as G. This selection function matches corresponding patterns.

FIG. 4 shows the result of G operation on the d table in FIG. 2. The arrow in FIG. 4 indicates which G is selected. When selecting G, one or all of G ₀ , G ₁ , and G ₂ may not exist in the frame at the edge of the table, so G that does not exist in such a place is ignored in the calculation. .

The result of DP matching in Figure 4 is at the bottom right end,
"9" is the distance between the input parameter and the standard parameter, and the thick frame indicates the selection order.

Next, an example of a DP calculation circuit that performs this DP matching calculation will be explained with reference to FIG.

1 is i memory, 2 is R register, 3 is d operation section, 4 is addition circuit, 5 is (G ₀ + d) register,
6 is _G1 register, 7 is _G2 register, 8 is G memory section, 9 is comparison section, 10 is G operation control circuit, 11
is a multiplexer.

The input parameters (input pattern) obtained from the input voice are held in the i-memory 1, the standard parameters (standard pattern) output from the dictionary part are held in the R register 2, and the d calculation part 3 stores these parameters. The absolute value difference d (d=|R−i|) between the input pattern and the standard pattern is determined, and first, the adder circuit 4 calculates
G ₁ register 6 holds the previous G ₁ and this d
are added to (G ₀ +d) and set in register 5 (G ₀ +d). That is, as is clear from Fig. 3, G ₁ appears to be G ₀ in the next frame, so in order to calculate (G ₀ + d), the value of G ₁ held in the G ₁ register 6 is used for the G operation. The _signal is outputted via the MPX 11 under the control of the control circuit 10, added to d in the adder circuit 4, and set in the register 5 as (G ₀ +d). Also, the G from last time is actually G ₂ . Therefore, when calculating G, G ₂
The result of this G calculation is also set in register 7. This allows G ₂ to be obtained from the G ₂ register 7. Then, the data is read from the G memory section 8 and set in the _G1 register 6. After setting (G ₀ +d), G ₁ and G ₂ in each register 5, 6 and 7 in this way, the comparison unit 9 selects the smallest value,
This is reported to the G calculation control circuit 10. Based on this report from the comparator 9, the G calculation control circuit 10 outputs the minimum of these from the MPX 11 to the addition circuit 4, adds d, and sets it as G. This G is
Set it in _G2 register 7 and use it for the calculation of the next frame. By repeating such operations, DP matching calculations are performed.

In the present invention, in order to be able to perform multiple linear matching in this DP matching circuit, G ₀ +d
As shown in FIG. 6, the input pattern i and a plurality of registered patterns are linearly matched at once, and a plurality of matching results can be obtained at the same time. Note that these patterns are fixed length patterns.

By the way, in order to perform multiple linear matching using the DP matching circuit, it is necessary to add the following functions.

(1) In the DP operation, a plurality of standard patterns for linear matching are stored in the i-memory where input patterns are stored, and conversely, input patterns for linear matching are stored in the R register. This is because the data stored in the i-memory can be sequentially output.

(2) It is necessary not to accumulate G in the first operation. In DP matching, as shown in No. 4, the first calculation proceeds with the calculation of G = G ₂ + d, but
In multiple linear matching, the calculation of G=d is performed.

(3) For operations other than the first, perform G=G ₀ +d.

In DP matching, G=mid [G ₀ +2d, G ₁ +d, G ₂ +d], but in multiple linear matching, G=G ₀ +d is calculated. However, if G ₀ does not exist, the value of G is invalid and can be any value.

FIG. 7 shows the configuration of an embodiment of the present invention having such a function.

In FIG. 7, 21 is i memory, 22 is R
Registers corresponding to the i-memory 1 and R-register 2 in FIG.
24 is a first multiplexer, 25 is an adder circuit corresponding to adder circuit 4, 26 is a (G ₀ +R) register, 27 is a G ₁ register, 28
are _G2 registers corresponding to (G ₀ +d) register 5, _G1 register 6, and _G2 register 7, 29 is a comparison section and corresponds to comparison section 9, and 30 is G calculation control. 31 is a second multiplexer, 32 is a third multiplexer, 33 is a multiple linear arithmetic control circuit, and 34 is a G memory unit that corresponds to the G memory unit 8. It is.

Next, the operation of the present invention will be explained.

(a) When performing multiple linear calculations First, a plurality of standard patterns for linear calculations are stored in the i-memory 21, as shown in FIG. 6 as standard patterns 1, 2, and so on.
2, an input pattern for linear calculation is set. First, the input pattern set in the R register 22 and standard pattern 1 are linearly matched, and then the input pattern and standard pattern 2 are linearly matched. Thereafter, the input pattern and standard patterns 3, 4, . . . are sequentially linearly matched. In this way, the input pattern is linearly matched against a plurality of standard patterns stored in the i-memory 21 at once. Once this is completed, the next plurality of standard patterns will be linearly matched at once in the same way.

In linear matching with this standard pattern, G
The arithmetic control circuit 31 includes a second multiplexer 31
Control is performed so that only the _G2 register 28 to which _G0 is set is output. However, in the first operation for each standard pattern, _G2 register 2
In order to set G=d without adding d output from the d calculation unit 23 to G ₂ held at 8, multiple linear calculation control is performed so that the third multiplexer 32 outputs zero in this first calculation. A circuit 33 controls. In addition, in the case of linear matching (G ₀ + d)
However, in the case of DP verification, the verification is performed using G ₀ + 2d, so G ₀ is stored in the G ₁ register.
+d has already been set. Therefore, G ₀
To obtain +d, it is necessary to add (G ₀ +d) set in the _G1 register with zero. Therefore, in order to make the output of the d calculation section 23 zero, it is necessary to output zero from the first multiplexer 24 at this time, and this control is also performed by the multiple linear calculation control circuit 33. Furthermore, in order _to perform linear matching, this multiple linear arithmetic control circuit 3
3 controls. By performing such control operations, it is possible to perform multiple linear calculations with the other parts performing the same operations as when performing normal DP calculations.

(b) When performing DP verification calculation When performing DP verification using the circuit shown in Figure 7, the input pattern for DP calculation is held in the i-memory 21 and stored in the R register 22, as in the case of Figure 5.
Set the standard pattern for DP calculation. The multiple linear calculation control circuit 33 controls the first multiplexer 24 to output d, which is the calculation result from the d calculation unit 23, and the third multiplexer 32 to output the data from the second multiplexer 31. For the comparison unit 29, as in the case _{of FIG .}
control to output the smallest of the data.

As a result, the circuit of the present invention shown in FIG. 7 operates in the same manner as the DP verification circuit shown in FIG.

〔Effect of the invention〕

According to the present invention, by using a DP matching circuit, candidates for DP matching can be selected extremely quickly by performing linear matching with a plurality of standard patterns. Since the time for the next verification can be reduced to about one-twentieth, it is possible to significantly speed up the voice recognition response time.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of DP matching, Figure 2 is a d table, Figure 3 is a G table, Figure 4 is an explanatory diagram of the position of G, Figure 5 is a conventional DP calculation circuit, and Figure 6 is multiple standards. FIG. 7, which is an explanatory diagram of pattern linear matching, is a configuration diagram of an embodiment of the present invention. In the figure, 21 is i memory, 22 is R register, 2
3 is a d operation unit, 24 is a first multiplexer, 25
is an adder circuit, 26 is a (G ₀ +d) register, 27
28 is a G ₁ register, 28 is a G ₂ register, 29 is a comparison section, 30 is a G operation control circuit, 31 is a second multiplexer, 32 is a third multiplexer, 33 is a multiple linear operation control circuit, and 34 is a G memory section. .

Claims (1)

[Claims] 1. A first pattern holding means for holding an input pattern, a second pattern holding means for holding a standard pattern, a difference calculation unit for calculating the absolute value difference between each parameter of the input pattern and the standard pattern, and an addition means, at least three data holding means in which G values in different frames are held;
A voice pattern matching circuit equipped with a comparison section that detects the minimum value of the values, a plurality of linear operation control means for switching between linear operation and DP operation, and a second circuit that outputs either the output of the difference operation section or a zero value. 1 selection output means and any one of the three data holding means.
a second selection output means for outputting one data, and a third selection output means for outputting either the output of the second selection output means or a zero value;
One of the pattern holding means or the second pattern holding means holds an input pattern for linear calculations, and the other pattern holding means holds a plurality of standard patterns for linear calculations, and in the case of linear calculation control, the plurality of linear calculations The control means first causes the first selection output means and the third selection output means to output zero, then causes the first selection output means to output the calculated value of the difference calculation section, and the second selection output means Among the three data holding means inputted to the linear output means, the third selection output means selects the one in which the collation cumulative value up to the previous frame is stored, and outputs the output from the third selection output means. The calculation input pattern and a plurality of standard patterns for linear calculations are linearly matched at the same time, and in the case of DP calculation control, the plural linear calculation control means selects the difference calculation section from the first selection output means. A calculated value is outputted, and the minimum value selected by the comparison section among the inputs of the three data holding means inputted to the second selection output means is outputted from the second selection output means, and this is outputted from the second selection output means. A speech pattern matching circuit characterized in that the selection output means is controlled to output, and the addition means calculates a matching cumulative value.