JPH0262879B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a speech recognition device that recognizes speech.

(b) Prior Art When trying to control some kind of equipment by recognizing speech, the response time, which mostly corresponds to the recognition operation, always poses a problem. In order to speed up the response time, it is generally considered to use a CPU, memory, or their peripheral circuits that can operate at high speed, but the entire system becomes expensive and the speed cannot be increased that much.

The existing speech recognition operation is shown in FIG.
A speech input period I ₁ during which the speech to be recognized is input, a silent period N ₁ indicating the end of the input speech, and a recognition period R ₁ during which the input speech is recognized are considered as one cycle, and this recognition cycle I ₁ , N ₁ and R ₁ , the next speech recognition cycle I ₂ , N ₂ , and R ₂ starts. Therefore, as long as the voice input period I, the silent period N, and the recognition period R are arranged in series, there is a limit to the speeding up of the recognition operation as described above.

In view of these points, the present invention and others have proposed a recognition device which aims to increase the speed and is called a condensed continuous recognition system (Japanese Patent Application No. 74932/1982). As shown in Figure 2, this is a system that performs voice inputs I ₁ , I ₂ , I _{3 .} . . and recognition of the input voices R ₁ , R ₂ , R _{3 .} . . in parallel using separate processors. That is.

However, as is clear from Fig. 2, generally the voice inputs I ₁ , I ₂ , I ₃ ...operation time and recognition R ₁ ,
R ₂ , R ₃ ...When comparing the operating time, the recognition R ₁ ,
R ₂ , R ₃ . . . operation time is longer, and as a result, a waiting time T occurs on the processor side responsible for the input operation, which is a waste of time. This phenomenon did not pose much of a problem in the case of recognition based on linear matching because the recognition time was short, but when recognition was performed using the DP matching method etc. developed to improve the recognition rate, it took a considerable amount of time. , and the waste of this waiting time T becomes large.

(c) Problems to be Solved by the Invention The present invention has been made by focusing on these new problems, and it is possible to shorten the waiting time between both processors installed in parallel as described above. , thereby providing a speech recognition device that reduces time wastage.

(d) Means for Solving the Problems The speech recognition device of the present invention causes the first processor section to perform the speech recognition capture operation and the preliminary comparison recognition operation, and the second processor section to perform the full comparison recognition operation. The preliminary comparison recognition processing time in the first processor section is shorter than the full-scale comparison recognition processing time in the second processor section, and the first processor section The time required for the audio signal capture operation and the preliminary comparison recognition operation is set to be approximately equal to the time required for the full comparison recognition operation in the second processor section.

(E) Effect The speech recognition device of the present invention performs the preliminary comparative recognition processing time in the first processor section in a shorter time than the full-scale comparative recognition processing time in the second processor section, and Since the time required for the audio signal acquisition operation and the preliminary comparison recognition operation in the first processor section and the time required for the full comparison recognition operation in the second processor section are set to be approximately equal,
With respect to the results of voice capture/preliminary comparison recognition processing that are sequentially obtained from the first processor,
The second processor can perform full comparison recognition processing with almost no waiting time.

(F) Embodiment FIG. 3 is a block diagram showing the specific configuration of the device of the present invention, in which 1 is a microphone that converts audio into an electrical audio signal, and 2 is an audio signal from this microphone 1. This is a feature extraction circuit that extracts the characteristics of a frequency spectrum parameter using a group of band filters as described in, for example, Japanese Patent Application Laid-open No. 54-145407. A voice characteristic pattern is output. Note that as this feature pattern, a pattern obtained by normalizing the above-mentioned parameter time series to a specific number of samples is generally used. Reference numeral 3 denotes a first buffer memory that stores the characteristic pattern of the input voice obtained from the feature extraction circuit 2. Reference numeral 4 denotes a first reference pattern memory in which a large number of reference patterns for preliminary comparison and recognition of this feature pattern are stored. The reference pattern stored here is a pattern in the same format as the characteristic pattern of the input voice to be compared, and is composed of a frequency spectrum parameter sequence in which the number of time-series samples is normalized. A first recognition circuit 5 performs a preliminary recognition operation by comparing and recognizing the characteristic pattern of the input voice with a large number of reference patterns. The preliminary recognition operation referred to here means that the first reference pattern memory 4
Rather than selecting a specific pattern that is most similar to the characteristic pattern of the input voice from among a large number of reference patterns stored in A linear matching method, etc., in which the distance is short, is adopted. 6 is the recognition result in this first recognition circuit 5,
Reference pattern memory 4 for reference patterns that are relatively similar to the selected feature pattern of the input voice
This is a first address memory that stores an address in . 7 is a feature extraction operation in the voice extraction circuit 2, loading of the extracted feature pattern into the buffer memory 3, a detection operation for detecting the end of the voice from a silent state of the input voice, or preliminary recognition in the first recognition circuit 5. The first CPU controls operations, etc., and these microphones 1 to 7 constitute a first processor _P1 .

Further, reference numeral 10 denotes a second buffer memory to which the characteristic pattern of the input voice stored in the buffer memory 3 of the first processor _P1 is transferred and stored;
is a second reference pattern memory in which a reference pattern for fully recognizing input speech is stored, and this reference pattern may be the same as that used in the first processor _P1 . .
However, in order to perform comparative recognition processing with high accuracy in the second processor P2, the number of samples of the reference pattern in this second reference pattern memory is made larger than that in the first one to prepare a highly accurate reference pattern. You can also do that. Reference numeral 12 indicates the addresses of a plurality of reference patterns in the first address memory 6 that are preliminarily selected as a result of preliminary comparison recognition in the first processor _P1 among the reference patterns in the second reference pattern 11. This is the second address memory that is transferred and stored. Reference numeral 13 denotes a second recognition circuit that performs a full-scale recognition operation of comparison between the reference pattern designated by the second address memory 12 and the characteristic pattern of the input voice stored in the second buffer memory 10. Recognition operations are performed using methods such as the DP method (dynamic programming method), which takes time to perform, but performs rigorous recognition operations. Reference numeral 14 denotes an output port for outputting the voice specified as a result of the recognition operation in this second recognition circuit 13 to an external circuit. Reference numeral 15 denotes a second CPU which controls the recognition operation in the second recognition circuit 13 and the output operation at the output port 14, and the second buffer memory 10 to the second CPU
15 constitutes a second processor _P2 .

Next, the operation of the apparatus of the present invention shown in FIG. 3 will be explained with reference to FIG. 4.

The audio input period I in Figure 4 is usually 200 msec~
1500 msec, which is a typical time range in word speech recognition. Also, the silent period N
is normally 200 msec, and this is because the interruption time in the voice, for example, the interruption time at the consonant "tsu" when uttering "totsutori" is about 150 mseo.
In order not to consider this as the end of the audio, a value of 200 msec, which is at least 30% longer than this interruption time, is appropriate. Further, if the number of recognized words is 64 using linear matching as in this embodiment, the preliminary comparison recognition period SR will be approximately 300 msec, although it depends on the processing speed of the hardware.

On the other hand, in the full-scale comparative recognition period MR, when DP matching is used as in this example and the number of recognized words is 20 (the result of the preliminary selection of the above 64 words),
Although it depends on the processing speed of the hardware, approximately 600 msec will be required.

First, in the first processor _P1 , the voice input from the microphone 1 is processed by the feature extraction circuit 2.
However, if a certain silent period N ₁ continues after the input audio I ₁ is interrupted, the first
The CPU 7 detects the end of the input voice I ₁ , extracts the feature pattern of the input voice that has been taken into the feature extraction circuit 2 up to that point, and stores it in the first buffer memory 3 . On the other hand, the first recognition circuit 5
performs preliminary comparison recognition SR ₁ between the reference pattern stored in the first reference pattern memory 4 and the feature pattern stored in the first buffer memory 3;
Some reference patterns that are relatively similar to the characteristic pattern are selected, and the pattern memory 4 of the selected reference patterns causes the first address memory 6 to store an address thereof. As mentioned earlier, the preliminary comparison recognition _SR1 operation by the first recognition circuit 5 does not necessarily require a strict recognition operation, so the linear matching method, in which the recognition operation is performed in a relatively short time, Adopted. Note that this first processor
All operations in P ₁ are controlled by the first CPU 7.

When this preliminary recognition SR ₁ operation is completed, the second processor P ₂ stores the address information that is the result of the preliminary recognition SR ₁ introduced into the first address memory 6 into the second processor P 2 .
The block pattern is transferred to the second address memory 12 of the processor P ₂ , and based on the address information, only the block pattern selected in the preliminary recognition SR ₁ from the second reference pattern memory 11 storing reference patterns is transferred to the second address memory 12 of the processor P 2. The full-scale recognition MR 1 operation is performed by reading the input voice into the second recognition circuit 13 and comparing it with the characteristic pattern of the input voice that has been previously transferred from the first buffer memory 3 to the second buffer memory 10 by the recognition circuit ₁₃ .
Strict comparative recognition between a reference pattern and a feature pattern is performed, and for this purpose, for example, the DP method is adopted. As mentioned earlier, this full-scale comparative recognition
Normally, the MR ₁ operation takes more time than the preliminary recognition SR ₁ in the first processor P ₁ , but the reference pattern that is compared with the feature pattern in this recognition circuit 13 is Since the number of patterns selected in advance in P ₁ is small, the time required for recognition is shorter than when comparing with all the reference patterns stored in the reference pattern memory 11, and the result is Generally speaking, as shown in FIG. 4, it is approximately equal to the total period of the input voice capture period I, the preliminary comparison recognition SR, and the silent period N in the first processor _P1 . However, since this relationship depends in part on the length of the audio material and the human utterance time, it must be said that it is a relatively rough and approximately equal relationship that includes uncertain factors.

For example, in the case of short audio input (I=
200 msec), the processing time (I+N+SR) of the first processor P1 is about 700 msec, which is of course approximately equal to that of the _second processor MR2 (600 msec).

However, in the case of long speech input (I=
1500 msec), the processing time (I+N+SR) of the first processor P1 is about 200 msec, which cannot be said to be completely equal to that of the second processor P2, but there is no problem as it can be regarded as approximately the same range.

In other words, rather than setting the above two temporal relationships to be equal when targeting audio with a long input time, it is better to set the above two temporal relationships to be equal when targeting audio with a short input time. If you keep it,
Continuous recognition can be performed effectively for continuous input of short-term input speech that requires higher-speed processing.

On the other hand, in parallel with this, in the first processor _P1 , when the preliminary recognition _SR1 is completed, the capture _I2 of the next input voice is started. As described above, this capture _I2 operation, the subsequent silent period _N2 , and preliminary recognition _SR2 are approximately equal to the preceding full-scale recognition _MR1 period in the second processor _P2 of the input speech.
Therefore, at the time when the first processor P ₁ completes the capture I ₂ of the second input voice and the preliminary recognition SR ₂ , the second processor P ₂ also completes the full-scale recognition operation MR ₁ for the first input voice. Both processors P ₁ and P ₂ perform predetermined operations on the next audio without any waiting time, that is, the first processor P ₁ performs the third input audio input operation I ₃ , and
Further, the second processor _P2 shifts to full-scale recognition operation _MR2 of the second input voice.

In the above embodiment, the linear matching method was explained as a preliminary comparison recognition process, and the DP matching method was explained as a full-scale comparison recognition process.
The present invention is not limited to these methods, and a preliminary method can use a method that can narrow down the reference patterns to some extent in a short processing time even if the recognition accuracy is lower than that of a full-scale method. For example, as a preliminary comparative recognition process, a method using only the maximum and minimum points of voice power (Japanese Patent Laid-Open No. 56-55995) can be used, and as a full-scale comparative recognition process,
Method using recognition functions (Book ``Speech Recognition'' 117~
118 pages, written by Niimi, published by Kyoritsu Shuppan, October 10, 1978), etc. can be used.

(g) Effects of the Invention As is clear from the above description, the present invention divides the recognition operation for input speech into two into preliminary recognition and full-scale recognition, and prepares two processors that operate independently. The capture operation and preliminary recognition operation are executed by one processor, and the full recognition operation is executed by the other processor.
Although it depends to some extent on the time length of the input audio, the execution times of both processors can be set approximately equal. Therefore, depending on the time length of the input audio, although it may not be possible to completely eliminate waiting time in both processors, it is possible to effectively reduce wasted idle time in each processor, and as a result, This can speed up speech recognition operations.

[Brief explanation of drawings]

1 and 2 are schematic diagrams showing the operation of existing speech recognition devices, FIG. 3 is a block diagram showing the configuration of the device of the present invention, and FIG. 4 is a schematic diagram showing the speech recognition operation according to the present invention. It is. _P1 , _P2 ...Processor, 3, 10...Buffer memory, 4, 11...Reference pattern memory, 5, 13
...Recognition circuit, 6,12...Address memory, 7,15...
CPU.

Claims (1)

[Claims] 1. A microphone that converts audio into an electrical audio signal, a feature extraction circuit that captures the audio signal and extracts its features, and a preliminary feature pattern extracted by the feature extraction circuit. a first reference pattern memory storing a reference pattern for comparative recognition; a first recognition circuit for performing preliminary comparative recognition between the reference pattern and the feature pattern; and a first recognition circuit for performing preliminary comparative recognition between the reference pattern and the feature pattern; a first processor section consisting of a buffer memory for storing results, a first CPU for controlling these feature extraction operations and preliminary comparison recognition operations; A second reference pattern memory is used to carry out full-scale comparative recognition between the reference pattern preliminarily recognized by the first processor and the feature pattern among the reference patterns in the second reference pattern memory. 2 recognition circuit and an I/I that outputs the recognition result of this second recognition circuit to an external circuit.
O port and this full-scale comparison recognition operation and I/O
A second CPU that controls port operations; This process is performed in a shorter time than the full-scale comparison recognition processing time in the second recognition circuit, and the time required for the audio signal acquisition operation and the preliminary comparison recognition operation in the first processor section and the second processor section A speech recognition device characterized in that the time required for a full-scale comparative recognition operation is set to be approximately equal to the time required for a full-scale comparative recognition operation.