KR0135503B1 - Key input method and device - Google Patents

Abstract

In the system function mode selection key recognition processing method, the first key including the function key data is used as a reference value, and the input key is searched by comparing the first data with the input key data as the second data. The key function processing range is set from the first data.

The membership degree value is read from the value corresponding to the first data and a key processing enable and disable signal is generated, and the key recognition process is performed as the output value.

Description

Key Recognition Method and Circuit

1 is a conventional circuit diagram.

FIG. 2 is a detailed circuit diagram of the minimum computation part of FIG.

3 is a circuit diagram according to the present invention.

The present invention relates to a key input processing method for a desired operation function in a fuzzy controller, and more particularly, to a key recognition method and a circuit which can promptly recognize a key by directly including an encoded key value in a rule memory. will be.

FIG. 1 is a circuit diagram of a conventional digital purge controller using a maximum and minimum processing scheme. The input key 101 is keyed through the keypad 108 so that a value encoded by the key encoder 107 is the same as that of the data input terminal. It is input to and buffered. The output of the input buffer 101 is calculated by the degree of belonging calculation unit 102, the minimum calculation unit 103 calculates the output value of the regular memory unit 106 and outputs the minimum value. The minimum value is processed by the maximum operation unit 104 to obtain the maximum value thereof, and then outputted through the output buffer 105. FIG. 2 is a concrete circuit diagram of the minimum calculation unit 103 of FIG. 1 and AND gates A1-An logically multiply the output of the degree of belonging calculation unit 102 and the output of the rule memory unit 106 to the rule memory unit 106. The output of the regular memory unit 106 is provided as an enable / disable signal EN / DN of the minimum calculation unit 103 and processed.

The conventional method described above has a problem that it is considerably inefficient because it calculates the degree of belonging according to each key value and extracts the key value using this value, resulting in more hardware configuration and processing complexity.

Accordingly, an object of the present invention is to provide a method and a circuit which can include an encoded key value directly in a regular memory data value and process the corresponding key quickly and efficiently.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram according to the present invention. In FIG. 3, a key encoder 107 is connected to 108, and key information about a corresponding key is stored separately in the rule memory 303 as rule information. The value keyed in at 108 is encoded in the key encoder 107 to be a first comparison value, and the corresponding key information in the rule memory 303 is set as a second comparison value. Compare the two comparison values to generate accurate information on the corresponding key value when the first and second comparison values match, and select the key processing in the oragate 304 from the key information of the key rule memory 303. A signal, which enables the output of the degree of belonging calculation unit 102 to be accepted from a value corresponding to the key information of the rule memory 303 and at the same time an enable / disable control signal for extracting a key value ( The AND gate (Al-An) that generates EN / DN) of the minimum computation unit 302 The rule memory 303 is enabled by a rule decoder 201 to output key information and a corresponding rule value on the rule memory 303, and the rule decoder 201 is a timing signal generator. The output of 202 is configured to control.

Therefore, if a specific embodiment of the present invention will be described in detail with reference to FIG. 3, the i-value of FIG. 3 when the number of keys (Play, Record, STart, STop ...) for selecting a function of an electronic device is 6 or more Can be three. The m value of the regular memory 303 is also 3, which is about 3 bits, and k is 5 in the output value of the membership degree calculating unit 102.

Therefore, when the user keyes in the play key through the keypad 108, for example, the key encoder 107 is encoded to generate first comparison data of about 3 bits for the key in.

Meanwhile, the rule memory 303 periodically enables the rule memory 303 to output the value of the rule memory 303 when decoding the signal output from the timing unit 202 by the rule decoder 201. The upper 3 bits of the value enabled in the rule memory 303 are generated as second comparison data as the function-related key information and input to the comparator 301. When there is upper 3 bit information that is the second comparison data of the rule memory 303 (when it has a value other than 000b), a function key must be included in the enabled rule memory 303 so that the comparator 301 The output of is 11111b if the second comparison data is equal to the first comparison data, and 00000b if it is different from the first comparison data. In the case where the function key is not included in the rule memory 303, if the upper 3 bits are set to 000b, it is disabled by the output of the ORA gate 304, so that the minimum operation unit 302 is not included.

Accordingly, among the enabled rule memory 303, bn-b0 can select whether or not to input values output from the degree of belonging calculation unit 102 to the minimum calculation unit 302, and selects an AND gate (Al-An). Through the degree of belonging calculation unit 102 is to be received. That is, in order to receive the output of the membership calculating unit 102, each signal of the bn-b0 of the rule memory 303 is high, and the high state is the enable signal EN of the minimum calculating unit 302. ) And Al-An's AND gate, respectively, so that each degree of belonging value is input to the minimum calculation unit 302.

If the first and second comparison data are the same, the comparator 301 makes the output high and if it is not the same, makes the output low and outputs the output to make it low (0). It is confirmed.

Therefore, the OA gate 304 outputs selection information according to key processing from the second comparison data of the rule memory 303, and the corresponding key information is output when the output of the comparison unit 301 is output 5 bits high. Is input to the minimum computation unit 302. When there is data other than the upper 3 bits of the rule memory 303 according to predetermined information data bn-b0, the minimum operation unit 302 is provided as an enable / disable signal (EN / DN) and an AND gate. The value supplied to (Al-An) and output from the degree of belonging calculation unit 102 is input to the minimum calculation unit 302. The outputs of the comparator 301 and the end gate Al-An are all 5 bits (k), and the output of the oragate 304 and the output of the degree of belonging calculation unit 102 are calculated using this. To extract the corresponding key value.

Accordingly, it can be seen that the corresponding key information input through the keypad 108 can be recognized based on this value while including the corresponding key information in the rule memory 303.

As described above, since the corresponding key information is stored in the rule memory and the key-in value is extracted from the input key by comparison, the key information is simplified, thereby improving efficiency and simplifying the hardware configuration.

Claims (2)

A system function mode selection key recognition processing method, comprising: a first data having first data including the function key data as a reference value and searching for an input key by comparing the first data with the input key data as the second data; And a second step of setting a key function processing range from the first data of the first step; and reading a degree of belonging value from a value corresponding to the first data and generating a key processing enable and disable signal. And a fourth process of performing a key recognition process using the output values of the first to third processes. In the key input processing circuit of the system including the cap 103, the key encoder 107, the degree of belonging calculation unit 102, the rule memory 303, and the minimum calculation unit 302, the rule memory 303 An AND gate (Al-An) for generating an enable / disable signal (EN / DS) of the minimum calculator 302 from the key information for the corresponding key, and controlling to receive the output of the belonging degree calculator 102; The first and second comparison values are encoded by using the key encoder 107 as a first comparison value and encoding the key information of the rule memory 303 as a second comparison value. The comparison unit 301 for generating accurate information on the corresponding key value in the minimum operation unit 302 and the key of the minimum operation unit 302 from the key information of the key rule memory 303 when comparing and matching. Key in, characterized by consisting of an oragate 304 to provide a selection signal for processing Processing circuit.