JPH03257819A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a sufficiently large crystal grain to be formed in a short time by performing plasma treatment within an environment where an inactive gas is added to an insulation amorphous material or either PH3 or B2H6 or both is added to hydrogen as a pre-treatment when forming an amorphous silicon. CONSTITUTION:An amorphous silicon layer 102 is formed on an insulation amorphous material 101. The amorphous silicon layer 102 is formed by a parallel plane type plasma CVD device, etc. In this case, plasma treatment is performed within an environment where either PH3 or B2H6 or both is added to an inactive gas or hydrogen. Then, heat treatment is performed to an amorphous silicon layer and crystallization is made, thus forming a polycrystal silicon layer 103. Further, a pattern is formed at the polycrystal silicon layer 103 and it is subjected to heat oxidation, thus forming a gate insulation film 104. Finally, a semiconductor element (TFT) is formed by using a normal self-alignment process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor element on an insulating amorphous material.

[Prior Art] In recent years, insulating amorphous substrates such as glass and quartz and SiO2 have been developed due to the need for large, high-resolution liquid crystal display panels, high-speed, high-resolution contact image sensors, three-dimensional ICs, etc.
There is a need for a technology for forming high-performance semiconductor elements on insulating amorphous materials such as.

Taking the case of forming a thin film transistor (TPT) on an insulating amorphous material as an example, (1) the element material is amorphous silicon formed by plasma CVD method, etc.; (2)
) A device using polycrystalline silicon formed by a CVD method or the like as an element material, and (3) A device using a single crystal silicon formed by a melt recrystallization method or the like as an element material are being considered. Among these TPT methods, the melt recrystallization method using a laser beam, etc. is still not a fully developed technology, and has problems such as large variations in the characteristics of each element and low yield. There is. For this reason, it is technically difficult to use, particularly in applications where elements need to be formed over a large area, such as liquid crystal display panels.

On the other hand, devices using amorphous silicon or polycrystalline silicon as the element material have achieved good results in terms of variation in characteristics of each element and yield, but The field effect mobility is significantly lower than that (the mobility of TPT using amorphous silicon as the element material < 1 cm2/V-SEC1 The mobility of TPT using polycrystalline silicon as the element material ~10 cm2/V, 5EC),
It was possible to apply this to drive circuits that require high performance.

In recent years, a method that improves the properties of TPT by forming large-grain polycrystalline silicon by solid-phase growth of amorphous silicon has attracted attention as a simple and practical method that can solve these problems. and research is underway.

(Synsolid Films 100 (1983) p.
p, 227, Javanese Journal of Applied
Physics Vo1.25 No. 2 (1986)
pp, L121) [Problem to be solved by the invention] However, in order to obtain a polycrystalline silicon film with large grain size, the conventional method requires a very long annealing time after forming an amorphous silicon film. For example, when an amorphous silicon film is formed by plasma CVD and annealed at 600°C, it takes 100 hours for sufficient crystal growth to occur. Close time is required.

The speed of crystal growth using solid-phase growth can be increased by increasing the annealing temperature, but in that case, a large number of crystal nuclei are likely to occur, making it difficult to grow individual crystals to a sufficient size. It becomes difficult to do so. For example, when an amorphous silicon film formed by the plasma CVD method is annealed at 650°C as in the above example,
Although the crystal growth is almost completed in less than 600℃
The particle size was only about 1/10 that of the one annealed.

The present invention is intended to solve these problems, and provides a manufacturing method that forms crystal grains of sufficient size with short annealing time.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the method for manufacturing a semiconductor device of the present invention includes: (a) injecting an inert gas or hydrogen into an insulating amorphous material;
(b) forming a semiconductor layer mainly composed of silicon; (c) crystallizing the semiconductor layer by heat treatment. The method is characterized in that it has at least a step of causing.

[Embodiment] FIGS. 1(a) to 1(d) show an example of the manufacturing process of a semiconductor device in an embodiment of the present invention. Note that this example shows a case where a thin film transistor (TPT) is formed as a semiconductor element.

FIG. 1(a) shows a process of forming an amorphous silicon layer 102 on an insulating amorphous material 101. Examples of the insulating amorphous material 102 mentioned here include glass, quartz,
Although an Si02 layer formed on a substrate such as alumina or ceramic or a silicon substrate can be considered, in this embodiment, a 5i02 layer formed on a quartz substrate by atmospheric pressure CVD is used.

The amorphous silicon layer 102 is formed by parallel plate plasma CVD.
The film was formed using a device, but at that time ■ PH3 was added to the hydrogen.
■Plasma treatment in an atmosphere in which B p Hs is added to hydrogen ■Plasma treatment in an atmosphere in which PH3 is added to Ar ■Plasma in an atmosphere in which B 2He is added to Ar Samples were prepared in which four types of pretreatment were introduced.

Processes (1), (2), (2), and (3) were all carried out for 10 minutes at a substrate temperature of 220° C. and an internal pressure of I Torr. Also, the temperature of the added gas (PHs and B 2 Ha) is hydrogen or A
It was set to 11000pp with respect to r. For comparison, a sample in which amorphous silicon was deposited without any pretreatment was also prepared, and the following steps were performed to examine the effects.

The above-mentioned pretreatment for forming the amorphous silicon film was carried out in a plasma CVD apparatus and the film was formed continuously, but a dedicated plasma processing apparatus such as a single-wafer plasma processing apparatus or a barrel-type plasma processing It is thought that similar results can be obtained even if the treatment is performed using a device. Although plasma CVD is used as a method for forming an amorphous silicon film, other film forming methods may be used, such as thermal CVD, vacuum evaporation, EB evaporation, MBE, sputtering, and polycrystalline silicon film. It is thought that similar results can be obtained with respect to an amorphous silicon film formed by a method such as implanting silicon ions into the film.

FIG. 1(b) shows a step of heat-treating the amorphous silicon layer and crystallizing it to form a polycrystalline silicon layer 103. Such a process will be referred to as a solid phase growth process. Heat treatment was performed at 600℃ and 650℃ in N2 atmosphere.
The crystallization was conducted at two levels of °C, and the state of crystallization was examined at 6 hours, 17 hours, and 72 hours. Before this solid phase growth, each sample was annealed at 400° C. for 1 hour to remove hydrogen from the film and densify the film.

When a sample that was not pretreated was annealed at 600'C, crystal nuclei began to be generated in the amorphous silicon in 17 hours, and crystallization was almost completed in 72 hours.

In the case of annealing at 650° C., many crystal nuclei were already generated in 6 hours, and crystallization was almost completed in 17 hours. In this case, because a large number of nuclei were generated, the size of the final polycrystalline silicon crystal grains was 600".
Compared to the case of annealing at C, tJl was much smaller.

■,■,■, where pretreatment was performed during amorphous silicon film formation.
In all of the samples (2), when annealed at 600° C., only a small number of crystal nuclei were generated within 17 hours compared to the samples that were not pretreated. but,
At 72 hours, crystallization had progressed to almost the same level as that without pretreatment. When annealing at 650° C., crystal nuclei were observed to occur in all samples after 6 hours, but their density was lower than that without pretreatment. At this time, the density of crystal nuclei generated depends on the pretreatment during amorphous silicon film formation, and
〉■,■ (The density of crystal nuclei generated in ■, ■ is lower than that of ■, ■, and the density of crystal nuclei generated in ■ and ■, and ■ and ■ are almost the same.) Ta. At 17 hours, crystallization of all samples was almost completed, but the size of crystal grains was larger than that of samples that were not pretreated.

FIG. 1(c) shows a step of forming a gate insulating film 104 by thermally oxidizing the polycrystalline silicon layer 103 after patterning. The gate oxidation temperature is 1150°C. 1o3 is crystallized by the solid phase growth method in step (b), but the crystallization rate is not necessarily sufficient, and there are considerable uncrystallized regions left between the crystal grains, resulting in rapid gate oxidation. If the temperature is raised to a temperature of
Thermal oxidation was performed at a predetermined temperature.

FIG. 1(d) shows a state in which a semiconductor element (TPT) is formed from the state of FIG. 1(c) using a normal self-line process. In this step, starting from the state shown in FIG. 1(c), a gate electrode 105 is formed using polycrystalline silicon by low pressure CVD, a source/drain region 106 is formed by implanting P ions, and an interlayer insulating film 107 is formed.
After forming a film, a contact hole is opened to form a wiring 109. An Sio2 film is deposited by low pressure CVD on the interlayer insulating film, and an Al-3 film is deposited on the wiring layer by sputtering.
An i-Cu film was used.

By fabricating TPT using the process described above using a sample annealed for 17 hours and a sample annealing for 72 hours in the process shown in FIG. 1(b), and comparing the characteristics, it was found that The effects of pretreatment were compared.

When annealing was performed at 600° C., almost no difference was observed due to the pretreatment during the formation of the amorphous silicon film. On the other hand, it was confirmed that there were differences depending on the annealing time, and the characteristics of the sample annealed for 72 hours were significantly improved compared to the sample annealed for 17 hours.

When annealing was performed at 650° C., a large dependence on the pretreatment during the formation of the amorphous silicon film was observed. That is, it was confirmed that the samples subjected to the pretreatments (■, ■, ■, ■) had improved characteristics compared to the samples that were not subjected to any pretreatment. The degree of improvement is ■,
■〈■,■ (The degree of improvement is greater for ■, ■ than for ■, ■.

Also, ■ and ■, and ■ and ■ have the same degree of improvement in characteristics.

), and there was a correspondence with the size of the polycrystalline silicon crystal grains confirmed in the step (b).

In particular, those subjected to the treatments (1) and (2) obtained very good characteristics almost the same as those obtained by annealing at 600° C. for 72 hours. On the other hand, almost no dependence on annealing time was observed. This can be considered to mean that the crystallization by solid phase growth was almost completed at the stage of annealing for 17 hours.

In this way, as a pretreatment for forming the amorphous silicon film,
By introducing treatments such as , ■, ■, and ■, even if the temperature during solid phase growth is increased to 650 °C and the speed of solid phase growth is accelerated, if annealing is performed at 600 °C for a long time. It has become possible to obtain properties similar to those of Therefore, the time required for annealing for solid phase growth can be reduced to approximately 1/4 compared to the case where these pretreatments are not performed.

In the above example, specific values were used for the internal pressure during the pretreatment, the substrate temperature, the ratio of added gas, and the temperature during solid phase growth, but the effects confirmed in the examples were It is not necessarily restricted to these values. Effects have been recognized when the internal pressure during the pretreatment is about 0.01 to 10 Torr, the substrate temperature is from room temperature to about 400°C, and the ratio of gas added is in the range of several tens to 4000 ppm.

In particular, the internal pressure is 0.5 to 5 Torr, the substrate temperature is 180°C or more, and the ratio of gas added is 500°C.
Good results have been obtained in the range of ~3000 ppm.

The annealing temperature in the solid phase growth step is 650
Particularly remarkable effects have been observed in the range of ~750°C.

Further, although the description has been made using Ar as the type of inert gas used, similar effects have been confirmed using other inert gases such as N2, Ne, and He. However, among these inert gases, the best results have been obtained when Ar is used.

In addition, in the examples, the effect of the pretreatment was explained as the effect when the annealing temperature of the solid phase growth step was increased from 600°C, but the pretreatment was Needless to say, it can be widely used as a means for controlling the generation of crystal nuclei. That is, lower temperatures (e.g. 600°C)
temperature below. ) is also useful when attempting to improve device characteristics by performing long-term annealing.

[Effects of the Invention] As described above, according to the present invention, when attempting to produce polycrystalline silicon with a large grain size by solid phase growth, the production time can be significantly shortened. As a result, it has become possible to eliminate the large throughput required when manufacturing a semiconductor device using the solid phase growth method, and it has become possible to apply the solid phase growth process to mass production. This makes it possible to form low-cost, high-performance semiconductor elements on insulating amorphous materials, making it possible to form large, high-resolution liquid crystal display panels, high-speed, high-resolution contact image sensors, three-dimensional ICs, etc. It has become possible to produce it at a practical cost.

In addition to the TPT shown in the examples, the present invention can be applied to insulated gate semiconductor devices in general, as well as photoelectric conversion devices such as bipolar transistors, static induction transistors, solar cells, and optical sensors. This is an extremely useful manufacturing method when forming a crystalline semiconductor as an element material.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) are cross-sectional views showing the manufacturing process of a semiconductor device in an embodiment of the present invention. 01 02 03 04 05 06 07 08 09 Insulating amorphous material Amorphous silicon layer Polycrystalline silicon layer Gate insulating film Gate electrode Source/drain region Interlayer insulating film Contact hole Wiring and above.

Claims (1)

[Claims] 1) (a) Insulating amorphous material with inert gas or hydrogen with PH_
(b) forming a semiconductor layer mainly composed of silicon; (c) crystallizing the semiconductor layer by heat treatment. A method for manufacturing a semiconductor device, comprising at least the following.