CN1333447C - Method for forming polysilicon layer and polysilicon film transistor - Google Patents
Method for forming polysilicon layer and polysilicon film transistor Download PDFInfo
- Publication number
- CN1333447C CN1333447C CNB031556051A CN03155605A CN1333447C CN 1333447 C CN1333447 C CN 1333447C CN B031556051 A CNB031556051 A CN B031556051A CN 03155605 A CN03155605 A CN 03155605A CN 1333447 C CN1333447 C CN 1333447C
- Authority
- CN
- China
- Prior art keywords
- layer
- amorphous silicon
- opening
- sacrifice
- silicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The present invention discloses a method for forming polycrystalline silicon layers and polycrystalline silicon film transistors, which defines silicon crystal seeds for forming a polycrystalline silicon layer. The method comprises the following procedures: firstly, forming a sacrificial layer on a baseplate; patterning the sacrificial layer to form an opening in the sacrificial layer; then forming a first amorphous silicon layer on the sacrificial layer and the baseplate; etching the first amorphous silicon layer and leaving silicon crystal seeds in the opening; then removing the sacrificial layer, and forming a second amorphous silicon layer on the silicon crystal seeds; at last, making the second amorphous silicon layer crystallize into a polycrystalline silicon layer. The present invention can accurately control the silicon crystal seeds to be produced in a channel region position, can increase crystal grain size, and can reduce crystal boundary numbers contained in the channel region.
Description
Technical field
The relevant a kind of method that forms polysilicon layer of the present invention, relevant especially a kind of silicon seed that defines is to form the method for polysilicon layer.
Background technology
Because polycrystalline SiTFT (polysilicon thin film transistor; Poly-Si TFT) compared with amorphous silicon (amorphous silicon) TFT higher electron mobility, reaction time, higher resolution are faster arranged, therefore, at present multi-crystal TFT widespread usage in LCD to drive LCD.The manufacture method of multi-crystal TFT generally adopts low temperature polycrystalline silicon method for making (LTPS; Low temperaturepolysilicon).
Fig. 1 a to 1b shows traditionally and to form the process section of polysilicon layer with the LTPS method in the tft array technology.With reference to Fig. 1 a, on a substrate 100, form a barrier layer 120 and an amorphous silicon layer 200 in regular turn.The formation method of amorphous silicon layer 200 generally is to adopt chemical vapour deposition technique (CVD; Chemical Vapor deposition).
Then, make amorphous silicon layer 200 carry out crystallization, for example use quasi-molecule laser annealing (ELA; Excimer laser annealing) mode is carried out crystallization, and forms polysilicon layer 300 (shown in Fig. 1 b).
Tradition becomes the amorphous silicon layer grow when directly carrying out laser crystallization via CVD, nucleation (nucleation) position is uncontrollable, therefore crystallite dimension is inhomogeneous, and average grain size (grain size) is usually all less than 1 μ m, cause crystal boundary (grain boundary) number that raceway groove (channel) zone is contained to differ, therefore influence electric property and the stability thereof of TFT.
Summary of the invention
In view of this, the objective of the invention is to address the above problem and provide a kind of silicon seed that defines to form the method for polysilicon layer.
Another object of the present invention provides a kind of silicon seed that defines to form the method for polysilicon layer, can be accurately and systematicness ground control and provide individual die carrying out heterogeneous nucleation required crystal seed position and seed sized during the stage, thereby make crystal grain on the position that has determined in advance, to grow up.
Another object of the present invention provides consistent the reaching uniformly of seed sized and distributes.
Another purpose of the present invention provides the silicon seed of diameter less than 1 μ m, and and then increase crystallite dimension, and reduce the crystal boundary number that channel region is contained, thereby the crystal boundary number that the raceway groove of each TFT is contained can be controlled in the identical scope.
For reaching purpose of the present invention, the present invention forms silicon seed and may further comprise the steps with the method that forms polysilicon layer.At first, form a sacrifice layer on a substrate, this sacrifice layer of patterning is to form an opening in this sacrifice layer.Then, on sacrifice layer and substrate, form one first amorphous silicon layer, this first amorphous silicon layer of etching, and in opening, stay silicon seed.Then, remove sacrifice layer, on silicon seed, form one second amorphous silicon layer.At last, make the second amorphous silicon layer crystallization and form a polysilicon layer.
The present invention also provides a kind of method of making polycrystalline SiTFT, and it is included in and forms a channel region, source area, drain region, gate dielectric and grid on the substrate.Wherein the generation type of channel region may further comprise the steps, and at first, forms a sacrifice layer, and this sacrifice layer of patterning is to form an opening in this sacrifice layer.Then, on sacrifice layer and substrate, form one first amorphous silicon layer, etching first amorphous silicon layer, and in opening, stay silicon seed.Then, remove sacrifice layer, on silicon seed, form one second amorphous silicon layer.At last, make the second amorphous silicon layer crystallization and form a polysilicon layer, this polysilicon layer of patterning mixes to the polysilicon layer of patterning, and forms a channel region and one source/drain region.
Description of drawings
Fig. 1 a to 1b shows traditionally and to form the process section of polysilicon layer with the LTPS method in the tft array technology;
Fig. 2 a to 2i shows according to the process section of preferred embodiment of the present invention definition silicon seed with the method for formation polysilicon layer; And
Fig. 3 is the top view with respect to Fig. 2 b, the profile of Fig. 2 b for looking along the A-A ' line of Fig. 3.
Description of reference numerals in the accompanying drawing is as follows:
Prior art
100～substrate, 120～barrier layer,
200～amorphous silicon layer, 300～polysilicon layer,
The present invention
10～substrate, 12～barrier layer,
20～sacrifice layer, 22～photoresist pattern,
25～patterned sacrificial layers, 27～opening,
30～the first amorphous silicon layers, the slight crack of 30a～first amorphous silicon layer 30,
32～silicon seed, 35～the second amorphous silicon layers,
40～polysilicon layer, 42～channel region,
45,46～source/drain region, 50～gate dielectric,
60～grid layer, 52～interlayer dielectric layer,
53～opening, 65,66～source/drain electrode.
Embodiment
Can't be for fear of the photoetching process analytic ability less than the problem of 1 μ m, so directly expose on amorphous silicon layer, development and etching method, the size of silicon seed can't reach the required critical dimension of heterogeneous nucleation.
Therefore, the present invention utilizes photoetching process to form an opening in a sacrifice layer, forms one first amorphous silicon layer in opening, this first amorphous silicon layer of etching again, and can in opening, obtain silicon seed less than 1 μ m.So, the undersized silicon seed of the present invention can reach the required critical dimension of heterogeneous nucleation, when carrying out crystallization, next formed second amorphous silicon layer then with this silicon seed and according to the mode of heterogeneous nucleation crystallization gradually, thereby can form the crystal grain of large-size.
Below especially exemplified by a preferred embodiment to describe technology of the present invention in detail.Fig. 2 a to 2i shows according to the process section of preferred embodiment of the present invention definition silicon seed with the method for formation polysilicon layer.For convenience of description, present embodiment is an example to make gate type (top-gate) multi-crystal TFT.
At first, with reference to Fig. 2 a, on a substrate 10, form a barrier layer 12 and a sacrifice layer 20 in regular turn.Then, on sacrifice layer 20, form a photoresist pattern 22.Substrate 10 can be transparency carrier, for example glass or plastic cement.Barrier layer 12 can be silicon nitride or silica, perhaps, can comprise two-layer: the combination of silicon nitride layer and silicon oxide layer.Sacrifice layer 20 can be metal or metal alloy, for example, can be Cr-Al alloy (Cr/Al alloy).Sacrifice layer 20 also can be silica.The thickness of sacrifice layer 20 can be between 1.5 μ m to the 2.5 μ m, for example can be 2 μ m.
Then, with reference to Fig. 2 b, be mask with photoresist pattern 22, sacrificial patterned 20 and the patterned sacrificial layers 25 that forms, and sacrifice layer 25 in formation one opening 27.Fig. 3 is the top view with respect to Fig. 2 b, the profile of Fig. 2 b for looking along the A-A ' line of Fig. 3.The diameter of opening 27 can be between 1.5 to the 2.0 μ m, preferably 1.6 μ m.The depth-to-width ratio of opening 27 (aspect ratio) can be between 2 to 1.5, and preferably 1.8.Moreover the next positions of silicon crystal seeds that forms in opening 27 of control is used in the position of may command opening 27 of the present invention.For example, the position-controllable of opening 27 built in TFT that future, desire formed in the position of channel region (channel region) roughly the same, so, can make next in opening 27 formed silicon seed be positioned at the scope of channel region.
Then, with reference to Fig. 2 c, on sacrifice layer 25 and barrier layer 12, form one first amorphous silicon layer 30.First amorphous silicon layer 30 preferably forms with sputtering method (sputtering), and thickness can be between 1000 to 3000 , for example 1000 .Because the step coverage (step coverage) of sputtering method is bad, and cooperate the bigger depth-to-width ratio of opening 27 again, can make that formed first amorphous silicon layer 30 is in the phenomenon of bottom generation slight crack (crack) 30a opening 27 in.
Then, etching first amorphous silicon layer 30 for example, carries out wet etching.As mentioned above, the bottom of first amorphous silicon layer 30 produces slight crack 30a, and when carrying out wet etching, therefore the easiest erosion that is subjected to etching solution of this slight crack 30a, can stay silicon seed 32 (shown in Fig. 2 d) after the etching in the opening 27.
Then, remove sacrifice layer 25, and form the structure shown in Fig. 2 e.
Then, with reference to Fig. 2 f, on silicon seed 32, form one second amorphous silicon layer 35.Second amorphous silicon layer 35 can use silicomethane (silane; SiH
4) be reacting gas, with chemical vapour deposition technique (CVD; Chemical vapor deposition) forms, for example plasma auxiliary chemical vapor deposition method (PECVD; Plasma-enhanced chemical vapor deposition) or Low Pressure Chemical Vapor Deposition (LPCVD; Low pressure chemical vapor deposition).
Then, still consult Fig. 2 f, make second amorphous silicon layer 35 carry out crystallization, and form a polysilicon layer 40, shown in Fig. 2 g.First amorphous silicon layer 30 (silicon seed 32) and second amorphous silicon layer 35 can be when using distinct methods to form, and for example, first amorphous silicon layer 30 can form by sputtering method, and second amorphous silicon layer 35 can form by chemical vapour deposition technique.
The present invention can use many conventional methods to carry out crystallization, comprises carrying out quasi-molecule laser annealing (ELA at low temperatures; Excimer laser annealing), at high temperature carry out solid-phase crystallization (SPC; Solidphase crystallization), discontinuous crystal grain flop-in method (CGG; Continuous grain growth), metal induced crystallisation (MIC; Metal induced crystallization), metal induced side crystallization method (MILC; Metal induced lateral crystallization) and continous way lateral solidification method (SLS; Sequentiallateral solidification) etc.
The present invention can utilize photoetching process and control the diameter of opening 27, thereby can make the size that forms silicon seed 32 in opening 27 less than 1 μ m.So, the undersized silicon seed 32 of the present invention can reach the required critical dimension of heterogeneous nucleation, when carrying out crystallization, 35 of second amorphous silicon layers with this silicon seed 32 and according to the mode of heterogeneous nucleation crystallization gradually, thereby can form the crystal grain of large-size (for example greater than 1 μ m).
Then, with reference to Fig. 2 h, use photoetching and etching method patterned polysilicon layer 40, the polysilicon layer for patterning mixes again, for example mixes with phosphorus, and forms channel region 42 and n type source/ drain region 45 and 46.
Then,, form a gate dielectric 50, form a metal level (not shown) again, carry out photoetching and etching for metal level again, and on the correspondence position of channel region 42, form a grid layer 60 with reference to Fig. 2 i.So far, finish TFT.
Then,, form an interlayer dielectric layer (interlayer dielectric) 52, in interlayer dielectric layer 52, form the opening 53 that reaches source/ drain region 45 and 46 more still with reference to Fig. 2 i.Then, metal is inserted in the opening 53, and formation source/ drain electrode 65 and 66.
In sum, the present invention utilizes photoetching process to form an opening in a sacrifice layer, forms one first amorphous silicon layer in opening, this first amorphous silicon layer of etching again, and in opening, obtain silicon seed less than 1 μ m.So, when carrying out crystallization, second amorphous silicon layer can be a nucleating point and with the mode of heterogeneous nucleation crystallization gradually with this silicon seed, thereby formed polysilicon layer can have the large-size crystal grain of (as greater than 1 μ m).
Moreover the present invention can desire forms in the channel region of TFT by opening being controlled in the future, and makes silicon seed to form in channel region.So, because the bigger and uniform crystal grain of size is arranged, can reduce the crystal boundary number that channel region is contained, and the crystal boundary number that the raceway groove of each TFT is contained can be controlled in the identical scope, and can make TFT have good electric property and stability.
Though the present invention with preferred embodiment openly as above; but it is not in order to restriction the present invention; without departing from the spirit and scope of the present invention, those skilled in the art can do and change and retouching, so protection scope of the present invention is when being as the criterion so that claims are determined.
Claims (19)
1. one kind forms silicon seed to form the method for polysilicon layer, and it comprises:
On a substrate, form a sacrifice layer;
This sacrifice layer of patterning is to form an opening in this sacrifice layer;
On this sacrifice layer and this substrate, form one first amorphous silicon layer;
This first amorphous silicon layer of etching, and in opening, stay silicon seed;
Remove this sacrifice layer;
On this silicon seed, form one second amorphous silicon layer; And
Make this second amorphous silicon layer crystallization and form a polysilicon layer.
2. formation silicon seed as claimed in claim 1 is to form the method for polysilicon layer, and wherein this sacrifice layer is a metal or metal alloy.
3. formation silicon seed as claimed in claim 2 is to form the method for polysilicon layer, and wherein this sacrifice layer is a Cr-Al alloy.
4. formation silicon seed as claimed in claim 1 is to form the method for polysilicon layer, and wherein this sacrifice layer is a silica.
5. formation silicon seed as claimed in claim 1 is to form the method for polysilicon layer, and wherein the depth-to-width ratio of this opening is between 2 to 1.5.
6. formation silicon seed as claimed in claim 1 is to form the method for polysilicon layer, and wherein first amorphous silicon layer forms with sputtering method.
7. formation silicon seed as claimed in claim 1 is to form the method for polysilicon layer, and wherein the thickness of this first amorphous silicon layer is between 1000 to 3000 .
8. formation silicon seed as claimed in claim 1 is to form the method for polysilicon layer, and wherein etching first amorphous silicon layer carries out with wet etch method.
9. formation silicon seed as claimed in claim 1 is to form the method for polysilicon layer, and wherein second amorphous silicon layer forms with chemical vapour deposition technique.
10. method of making polycrystalline SiTFT, it comprises:
On a substrate, form a channel region, source area, drain region, gate dielectric and grid,
Wherein the generation type of this channel region may further comprise the steps:
Form a sacrifice layer;
This sacrifice layer of patterning is to form an opening in this sacrifice layer;
On this sacrifice layer and this substrate, form one first amorphous silicon layer;
This first amorphous silicon layer of etching, and in opening, stay silicon seed;
Remove this sacrifice layer;
On this silicon seed, form one second amorphous silicon layer;
Make this second amorphous silicon layer crystallization and form a polysilicon layer;
This polysilicon layer of patterning; And
Polysilicon layer to patterning mixes, and forms a channel region and one source/drain region.
11. the method for manufacturing polycrystalline SiTFT as claimed in claim 10, wherein this sacrifice layer is a metal or metal alloy.
12. the method for manufacturing polycrystalline SiTFT as claimed in claim 11, wherein this sacrifice layer is a Cr-Al alloy.
13. the method for manufacturing polycrystalline SiTFT as claimed in claim 10, wherein this sacrifice layer is a silica.
14. the method for manufacturing polycrystalline SiTFT as claimed in claim 10, wherein the depth-to-width ratio of this opening is between 2 to 1.5.
15. the method for manufacturing polycrystalline SiTFT as claimed in claim 10, wherein first amorphous silicon layer forms with sputtering method.
16. the method for manufacturing polycrystalline SiTFT as claimed in claim 10, wherein the thickness of this first amorphous silicon layer is between 1000 to 3000 .
17. the method for manufacturing polycrystalline SiTFT as claimed in claim 10, wherein etching first amorphous silicon layer carries out with wet etch method.
18. the method for manufacturing polycrystalline SiTFT as claimed in claim 10, wherein second amorphous silicon layer forms with chemical vapour deposition technique.
19. the method for manufacturing polycrystalline SiTFT as claimed in claim 10, wherein the position of the position of this opening and this channel region is roughly the same.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031556051A CN1333447C (en) | 2003-08-29 | 2003-08-29 | Method for forming polysilicon layer and polysilicon film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031556051A CN1333447C (en) | 2003-08-29 | 2003-08-29 | Method for forming polysilicon layer and polysilicon film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1591801A CN1591801A (en) | 2005-03-09 |
| CN1333447C true CN1333447C (en) | 2007-08-22 |
Family
ID=34598166
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031556051A Expired - Lifetime CN1333447C (en) | 2003-08-29 | 2003-08-29 | Method for forming polysilicon layer and polysilicon film transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1333447C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103515200A (en) * | 2012-06-15 | 2014-01-15 | 无锡华润上华半导体有限公司 | Preparation method of thick polysilicon |
| CN109860109A (en) * | 2019-02-28 | 2019-06-07 | 武汉华星光电半导体显示技术有限公司 | A kind of thin film transistor and its manufacturing method, display panel |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02188499A (en) * | 1989-01-13 | 1990-07-24 | Ricoh Co Ltd | Production of polycrystal silicon film having large crystal grain diameter |
| JPH03257819A (en) * | 1990-03-07 | 1991-11-18 | Seiko Epson Corp | Manufacture of semiconductor device |
| US5393682A (en) * | 1993-12-13 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Method of making tapered poly profile for TFT device manufacturing |
| JPH1197692A (en) * | 1997-09-18 | 1999-04-09 | Toshiba Corp | Polycrystal and liquid crystal display |
| JP2001093853A (en) * | 1999-09-20 | 2001-04-06 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| US6326286B1 (en) * | 1998-06-09 | 2001-12-04 | Lg. Philips Lcd Co., Ltd. | Method for crystallizing amorphous silicon layer |
| US6372612B1 (en) * | 1999-09-24 | 2002-04-16 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor circuit |
-
2003
- 2003-08-29 CN CNB031556051A patent/CN1333447C/en not_active Expired - Lifetime
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02188499A (en) * | 1989-01-13 | 1990-07-24 | Ricoh Co Ltd | Production of polycrystal silicon film having large crystal grain diameter |
| JPH03257819A (en) * | 1990-03-07 | 1991-11-18 | Seiko Epson Corp | Manufacture of semiconductor device |
| US5393682A (en) * | 1993-12-13 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Method of making tapered poly profile for TFT device manufacturing |
| JPH1197692A (en) * | 1997-09-18 | 1999-04-09 | Toshiba Corp | Polycrystal and liquid crystal display |
| US6326286B1 (en) * | 1998-06-09 | 2001-12-04 | Lg. Philips Lcd Co., Ltd. | Method for crystallizing amorphous silicon layer |
| JP2001093853A (en) * | 1999-09-20 | 2001-04-06 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| US6372612B1 (en) * | 1999-09-24 | 2002-04-16 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1591801A (en) | 2005-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6867074B2 (en) | Method of fabricating a polysilicon layer | |
| US7919777B2 (en) | Bottom gate thin film transistor and method of manufacturing the same | |
| JP4095064B2 (en) | Thin film transistor and manufacturing method thereof | |
| US20070065998A1 (en) | Polysilicon thin film fabrication method | |
| US20050106841A1 (en) | Method of fabricating a polysilicon layer | |
| CN100487878C (en) | Method of fabricating semiconductor device and semiconductor fabricated by the same method | |
| CN1307690C (en) | Method for making polysilicon layer | |
| US20060113596A1 (en) | Single crystal substrate and method of fabricating the same | |
| TWI220073B (en) | Method for manufacturing polysilicon film | |
| CN100565824C (en) | The manufacture method of semiconductor device and the semiconductor device of making by this method | |
| KR20100100187A (en) | Fabrication method of polycrystalline silicon | |
| US6426246B1 (en) | Method for forming thin film transistor with lateral crystallization | |
| JP4549842B2 (en) | Thin film transistor manufacturing method | |
| CN1333447C (en) | Method for forming polysilicon layer and polysilicon film transistor | |
| US7863621B2 (en) | Thin film transistor | |
| US7682950B2 (en) | Method of manufacturing laterally crystallized semiconductor layer and method of manufacturing thin film transistor using the same method | |
| US7560317B2 (en) | Method of forming single crystalline silicon layer, structure including the same, and method of fabricating thin film transistor using the same | |
| KR100785019B1 (en) | A bottom gate thin film transistor and method of manufacturing thereof | |
| CN100413016C (en) | Multicrystalline silicon film manufacturing method | |
| KR101031759B1 (en) | Method for crystallizing of Si, and methode for fabricating of poly-TFT | |
| KR20000074451A (en) | Thin film transistor, liquid crystal display device and the method of fabricating the same | |
| KR100366959B1 (en) | crystallization method | |
| KR100367638B1 (en) | Method of producing a poly-Si thin film transistor by using a layer of CeO2 and an A/R coating layer | |
| US20040248346A1 (en) | Inducing semiconductor crystallization using a capillary structure | |
| CN100524656C (en) | Production of thin-film transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20070822 |