JPH03257515A - Current consumption control system for information processor - Google Patents

Abstract

PURPOSE:To effectively reduce the current consumption by providing a clock switch control part to switch the clock frequency based on a prescribed signal. CONSTITUTION:A control part consists of a clock dividing circuit 28, a switch circuit 29, and a clock selection circuit 30. The circuit 21 outputs a 2-divided clock 31 and a 4-divided clock 32 with the basic clocks A/B 11 and 21 used as the inputs. The circuit 29 switches the clocks A/B 11 and 21, the clock 31 or the clock 32 based on the clock switch signals 33 and 34 and outputs the action clocks A/B 14 and 25. The circuit 30 uses an interface signal C22, a microinstruction d23, a microinstruction e24 or the microinstruction a12 and b13 as the inputs and outputs the signals 33 and 34. Thus the current consumption can be effectively reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a current consumption control method for an information processing device.

[Conventional technology]

Conventionally, in the current consumption control method of this type of information processing device,
Current consumption is suppressed by applying a normal operating voltage to each circuit that makes up an information processing device during periods when they need to operate, and applying a low voltage that maintains the circuit state during periods when they do not need to operate. was. That is, in the conventional current consumption control method, the current consumption is suppressed by completely stopping the operation of the circuit when it is not necessary.

[Problem to be solved by the invention]

By the way, when the circuit is configured with three CMO elements, the current consumption of the circuit changes in proportion to its switching frequency. In addition, in circuits that constitute an actual information processing device, there are cases in which the operation can be completely stopped, and there are cases in which the operation can be operated at a reduced operating speed. Therefore C
In an information processing device configured using MO3 elements, current consumption can be further suppressed by lowering the operating speed and switching frequency depending on the state.

However, with conventional current consumption control methods, it is not possible to suppress current consumption by lowering the operating speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a current consumption control method for an information processing device that can eliminate such drawbacks and suppress current consumption more effectively than conventional methods.

[Means to solve the problem]

The present invention is a current consumption control method for an information processing device configured using 0MO3 elements and operated by a predetermined clock, characterized in that a clock switching control section for switching the frequency of the clock based on a predetermined signal is provided. do.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram showing an embodiment of an information processing apparatus using the current consumption control method of the present invention.

The central processing unit 1 includes a microinstruction address calculation circuit 2, a microprogram storage unit 3. Microinstruction decoding circuit 4. Data calculation circuit 5. It consists of a clock switching control section A6, and the microinstruction at the address indicated by the output of the microinstruction address arithmetic circuit 2 is read from the microprogram storage section 3 and input to the microinstruction decoding circuit 4.

The microinstruction decode circuit 4 sends an address calculation control signal 7 to the microinstruction address calculation circuit 2. Data calculation control signal 8 for data calculation circuit 5. Microinstruction signal group 9 for microinstruction signal bus 26, and microinstruction a12 . Microinstruction b13 is output. In addition, the basic clock All is input to the clock switching control section 6, and the operation clock A14 of the output signal is input to the microinstruction address calculation circuit 2.
．． Microprogram storage section 3. Microinstruction decoding circuit 4. The signal is supplied to the data calculation circuit 5 and serves as an operating clock for each.

The peripheral device control section 15 includes a peripheral device control circuit 16. Peripheral Device Interface 17. The data bus 27 is connected to the peripheral device control circuit 16 by a data input/output line 19, and the data bus 27 is further connected to the data calculation circuit 5 of the central processing section 1. The peripheral device 20 is connected to the peripheral device control circuit 16 via the peripheral device interface circuit 17.

The clock switching control section 818 has a basic clock B21. Interface signal C22 and further microinstruction signal bus 2
The microinstruction d23 and microinstruction e24 from 6 are input, and the output signal operating clock B25 is supplied to the peripheral device control circuit 16 and serves as an operating clock.

In FIG. 1, it is assumed that all logic circuits except the peripheral device interface circuit 17 and the peripheral device 20 use 0MO3 elements.

FIG. 2 is a detailed block diagram of the clock switching control section A6 and the clock switching control section 81B shown in FIG. Since the clock switching control section A6 and the clock switching control section 81B have the same configuration except for the presence or absence of the interface signal C22, they are commonly expressed in two block diagrams. These control sections include a clock frequency divider circuit 28. Switching circuit 29. Consisting of a clock selection circuit 30 and a clock frequency dividing circuit 28
inputs the basic clock A/B 11.21 and outputs a 2-frequency divided clock 31 and a 4-frequency divided clock 32. Switching circuit 2
9 is a basic clock A/Bll according to clock switching signals 33 and 34;

21, the frequency-divided clock 31, or the frequency-divided clock 32 is switched and outputted as the operating clock A/B 14.25. The clock selection circuit 30 receives the interface signal C22 and the microinstruction d23. Microinstruction e24 (in case of clock switching control section 81B), or microinstruction a12. It inputs the microinstruction b13 (in the case of clock switching control section A6) and outputs a clock switching signal 3334.

FIG. 3 is a timing diagram of the clock frequency divider circuit 28 in FIG.
The relationship between the frequency-divided 2-frequency clock 31 and the 4-frequency-divided clock 32 that is further frequency-divided is shown.

Next, the operations shown in FIGS. 1 and 2 will be explained with reference to FIGS. 4 and 5.

FIG. 4 is a diagram showing a change in the frequency of the operating clock A14 in FIG. 1 and a corresponding change in the current consumption of the central processing unit 1. While the central processing unit l is processing valid data, the microinstruction address calculation circuit 2. Microprogram storage section 3. Microinstruction decoding circuit 4. Since the data calculation circuit 5 inherently requires high-speed processing, an operating clock A14 having the same frequency as the basic tally clock All is supplied from the clock switching control section A6. At this time, since the operating clock frequency of the current consumption A of the central processing unit 1 is high, the current value is high. Next, when the central processing unit 1 is in an idle state and high-speed processing is no longer required, the microinstruction a12 is output from the microinstruction decoding circuit 4, and the clock selection circuit 30
outputs a clock switching signal 33.34 to switch to the 4-frequency divided clock 32, and the switching circuit 29 switches the operating clock A14 from the basic clock All to the 4-frequency divided clock 32 in accordance with the clock switching signal 33.34. Since the operating clock A14 is set to a low frequency by the microinstruction a12, the processing speed is slowed down, but the processing function is maintained, and the switching frequency of the circuit is lowered, so the current consumption A becomes a low current value.

Next, when the central processing unit 1 enters a state that requires high-speed processing, the microinstruction b13 is output from the microinstruction decoding circuit 4, and the clock selection circuit 30 outputs clock switching signals 33 and 34 to switch to the basic clock All, and the switching circuit At 29, the operating clock A14 is divided into 4 clocks 32 and 32 to the basic clock A according to the clock switching signals 33 and 34.
Switch to ll. The microinstruction b13 causes the operating clock A14 to have a high frequency, allowing high-speed processing, but the current consumption A also returns to its original high current value.

FIG. 5 is a diagram showing a change in the frequency of the operating clock B25 in FIG. 1 and a corresponding change in the current consumption B of the peripheral device control section 15. The peripheral device control unit 15 is the peripheral device 2
Operation clock B25 while the control state for 0 is not changed.
The 4-frequency divided clock 32 is output, and the current consumption B of the peripheral device control unit 15 is a low current value. Next, when the state of the peripheral device 20 changes, the peripheral device interface circuit 17 outputs an interface signal C22, and the clock selection circuit 3° outputs clock switching signals 33 and 34 to switch to the divided-by-2 clock 31, and the switching circuit 29 Then, according to the clock switching signals 33 and 34, the operating clock B
25 is switched from the 4-frequency divided clock 32 to the 2-frequency divided clock 31. Since the operating clock B25 supplied to the peripheral device control circuit 16 has a medium frequency, it is possible to execute medium-speed processing according to the state of the peripheral device 20, but the current consumption also becomes a medium current value.

Next, when a state requires high-speed control between the peripheral device 20 and the peripheral device control circuit 16, the microinstruction d23 is manually input to the clock selection circuit 30. Clock selection circuit 30
outputs clock switching signals 33.34 to switch to the basic clock B21, and the switching circuit 29 switches the operating clock B25 from the frequency-divided clock 31 to the basic clock B21 in accordance with the clock switching signal 33.34. Since the operating clock B25 supplied to the peripheral device control circuit 16 has a high frequency, it is possible to execute high-speed processing requested by the microprogram, but the current consumption B also increases in proportion to the increase in speed.

Next, when the high-speed processing is completed and the low-speed processing becomes satisfactory, the microinstruction e24 is input to the clock selection circuit 30.

The clock selection circuit 30 outputs clock switching signals 33 and 34 to switch to the 4-frequency divided clock 32, and the switching circuit 2
9, the operating clock B25 is divided into four clocks 32 from the basic clock B21 according to the clock switching signals 33 and 34.
Since the supplied operating clock B25 has a low frequency, the peripheral device control circuit 16 can only perform low-speed processing, but there is no problem because there is no processing that should be executed at high or medium speed. At this time, the current consumption also returns to its original low current value in proportion to the frequency.

In addition, in the above-described embodiment, if the operating clock supplied from the clock switching control section A6 and the clock switching control section B18 is not only switched to a lower frequency but also the supply of the operating clock is stopped, each section stops operating. Stop.

Therefore, during a period in which the operation of each section can be stopped, current consumption can be further suppressed by stopping the supply of the operating clock from the clock switching control section.

〔Effect of the invention〕

As explained above, the present invention provides a clock switching control section that switches the frequency of the clock based on a predetermined signal in a current consumption control method for an information processing device configured using three CMO elements and operated by a predetermined clock. It is set up.

Therefore, in the information processing device based on the current consumption control method of the present invention, if the operating speed can be reduced depending on the operating state, by switching the clock frequency to a lower frequency, the current consumption control method can more effectively control the current consumption than the conventional method. can be suppressed.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of an information processing apparatus using the current consumption control method of the present invention, and FIG. 2 is a block diagram of the clock switching control section A6. A detailed block diagram of the clock switching control unit BIB, FIG. 3 shows the clock frequency dividing circuit 28 of FIG.
4 is a timing diagram showing the frequency change of the operating clock A14 in FIG. 1 and the corresponding change in current consumption of the central processing unit 1. FIG. 5 is a timing diagram showing the frequency change of the operating clock B25 in FIG. FIG. 3 is a timing chart showing changes in current consumption of the peripheral device control unit 15 in response to this. 1...Central processing unit 2...Micro instruction address calculation circuit 3...
・Micro program storage section 4... Micro instruction decoding circuit 5... Data calculation circuit 6 ・ ・ ・ 10. 19 ・ 15 ・ ・ 16 ・ ・ 17 ・ ・ 18 ・ ・ 20・ ・ 26. Command signal path data bus clock divider circuit switching circuit clock selection circuit

Claims (1)

[Claims] (1) A current consumption control method for an information processing device configured using a CMOS element and operated by a predetermined clock, characterized by providing a clock switching control section that switches the frequency of the clock based on a predetermined signal. Current consumption control method for information processing equipment.