JP2606248B2 - Disk controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a disk controller, and more particularly, to a disk controller that selects and controls an arbitrary disk drive from a plurality of disk drives. [Prior Art] Any disk drive among a plurality of disk drives
In a disk controller that selects and controls drives,
When a reference clock for defining the data transfer rate is supplied from each disk drive, the disk controller uses the reference clock supplied from the selected disk drive to transfer data to and from the disk drive. Need to be controlled. In this case, the reference clock input to the data transfer control unit is also switched according to the switching of the disk drive selection signal. However, since the reference clocks supplied from the respective disk drives are asynchronous with each other, switching using a simple multiplexer may cause a glitch in the reference clock input to the data transfer control unit. Normally, the data transfer control unit operates based on the reference clock,
The input reference clock on which the glitch is superimposed may adversely affect the operation of the data transfer control unit. Therefore, in order to switch these reference clocks without generating a glitch, it has been conventionally performed to provide a clock switching means to guarantee an input reference clock to a data transfer control unit. [Problems to be Solved by the Invention] However, when a disk control device is configured using the above-described conventional clock switching means, switching of the reference clock accompanying switching between the disk drives is performed before and after switching. When the number of disk drives to be controlled is increased because the operation is performed directly between the drives, there is a disadvantage that the configuration of the clock switching means is rapidly complicated. For example, in the case of a disk controller that controls N disk drives, the selection signal is switched from the currently selected disk drive to the remaining (N-1) disk drives by the remaining (N-1) disk drives. -1) It occurs with equal probability for each of the tables. For this reason, the clock switching means needs to perform clock switching of N! / 2 combinations without glitches,
The configuration of the clock switching means becomes complicated and required hardware increases. [Differences of the Invention from the Prior Art

[Means for solving the problem]

The disk control device according to the present invention selects and selects a disk drive corresponding to an external selection signal from a plurality of disk drives supplying a first reference clock for defining a data transfer rate. Disc
A disk control device for controlling data transfer of a disk drive by using a first reference clock supplied by a drive, wherein the disk control device selects one of the first reference clocks output by the plurality of disk drives. The first output from the disk drive selected by the selection signal
And a second reference clock supplied to the disk drive control device, and switching between the output of the multiplexer and the second reference clock as a reference clock of the disk control device. A switching circuit for outputting, the switching circuit switching the output from the output of the multiplexer to the second reference clock in response to a change in the selection signal, and the multiplexer receiving a change in the selection signal in response to the change in the selection signal. Upon receiving a signal indicating that the reference clock of the corresponding disk drive has been selected, the second reference clock is switched to the output of the multiplexer. Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. The present embodiment is a control device for controlling four disk drives. 11 is a controller for controlling the selection of the disk drive and the reference clock switching associated therewith. 12 is a clock switching circuit for switching clocks in an asynchronous relationship between two systems without generating a glitch. 13 is a 4-input 1-output circuit. The multiplexers 14-17 are
It is a disk drive. 101 is an external disk drive selection signal, 102 is a disk drive selection signal delayed by a certain time by the controller 11, 103
Is a disk drive switching notice signal, 104 is a disk drive switching completion signal, 105 is an output clock of the clock switching circuit 12, 106 is an output signal of the multiplexer 13, and 107 is a stable signal in the disk controller. The supplied clocks 108 to 111 are reference clocks for data transfer output from the disk drives 14 to 17, respectively. Hereinafter, the operation of this embodiment will be described with reference to the disk drive 15.
The case where the disk drive is switched from to the disk drive 17 will be described. When the disk drive selection signal 101 transits to select the disk drive 17 while the disk drive 15 is selected, the controller 11 first outputs the disk drive switching notice signal 103. The clock switching circuit 12 is selected by the multiplexer 13 from the disk drive 15 and the multiplexer output 106
The reference clock supplied through the
According to the instruction of the drive switching notice signal 103, the clock 107 is switched to the clock 107 stably supplied in the disk controller without glitch, and is output to the reference clock 105. Next, the controller 11 outputs a disk drive selection signal 102 and selects the disk drive 17. At the same time, the multiplexer 13 switches the reference clock to be output to 106 from 109 to 111 in accordance with the instruction of the disk drive selection signal 102. There is a possibility that a glitch may occur in the multiplexer output 106 at the timing of switching the disk drive. In this case, the clock 107 selected by the clock switching circuit 12 is the reference clock 1.
It is output to 05 and there is no problem. After outputting the disk drive selection signal 102, the controller 11 outputs a disk drive switching completion signal when the reference clock output from the disk drive 17 output to the multiplexer output 106 becomes stable after a certain period of time. Outputs 104. The clock switching circuit 12 converts the reference clock output to 105 into the multiplexer output 106 from the clock 107.
Then, switching is performed without a glitch using the disk drive switching completion signal 104. Switching from the disk drive 15 to the disk drive 17 is performed as described above. FIG. 2 shows an example of the configuration of the controller 11 shown in FIG. 21 is a delay means for delaying the disk drive selection signal for a certain time, 22 is a signal transition detection means for detecting a transition of the disk drive selection signal, that is, switching of the disk drive, and 23 is an output of the signal transition detection means 22 Is a delay time longer than the delay time by the delay means 21 and the switching time required for switching the disk drive. Further, as described above, 101 is an external disk drive selection signal, 102 is a disk drive selection signal delayed by a certain time by the delay means 21, 103
Is a disk drive switching advance notice signal detected by the signal transition means 22, and 104 is a disk drive switching completion signal indicating completion of disk drive switching as a result of the delay by the delay means 23. When the configuration shown in FIG. 2 is adopted, the operation of the controller 11 is as follows. When the disk drive selection signal 101 from the outside transits, the transition of the disk drive selection signal is detected by the signal transition detection means 22, and the disk drive switching notice signal 103 is output. Next, the disk drive selection signal delayed by the delay means 21 is output. On the other hand, the disk drive switching notice signal 103
Is delayed by the delay means 21 and the delay means 23 having a delay time longer than the sum of the time required for switching the disk drive, and outputs a disk drive switching completion signal 104 indicating that the disk drive switching has been completed. FIG. 3 is a timing chart showing control timing in the embodiment shown in FIG. FIG. 4 shows the principle of clock switching of the clock switching circuit 12 in FIG. 1 for switching clocks having two asynchronous relationships without generating a glitch. FIG. 5 is a block diagram showing the configuration of the second embodiment of the present invention. This embodiment is also a control device for controlling four disk drives. Reference numeral 51 denotes a controller for controlling the selection of a disk drive and the accompanying switching of a reference clock. 52, a clock switching circuit for switching between two asynchronous clocks without generating a glitch. 53, a 4-input / 1-output clock. The multiplexers 54-57 are
It is a disk drive. 501 is an external disk drive selection request signal, 502 is a disk drive selection signal output by the controller 51, 503 is
A disk drive switching period display signal, 504 is an output clock of the clock switching circuit 52, 505 is an output signal of the multiplexer 53, 506 is a clock that is stably supplied in the disk controller, and 507 to 510 are disks.・
This is a clock serving as a reference for data transfer output from each of the drives 54 to 57. Hereinafter, the operation of this embodiment will be described with respect to the disk drive 55.
The case where the disk drive is switched from the disk drive to the disk drive 57 will be described. When the disk drive selection signal 501 transits to select the disk drive 57 while the disk drive 55 is selected, the controller 51 activates the disk drive switching period display signal 503.
When the disk drive switching period display signal 103 becomes active, the clock switching circuit 52
The reference clock selected from the drive 55 by the multiplexer 53 and supplied through the multiplexer output 505 is switched to the clock 506 stably supplied in the disk controller without glitches, and is output to the reference clock 504. Next, the controller 51 outputs a disk drive selection signal 502 to select the disk drive 57. At the same time, the multiplexer 53 switches the reference clock output to 505 from 508 to 510 according to the instruction of the disk drive selection signal 502. There is a possibility that a glitch may occur in the multiplexer output 505 at the timing of switching the disk drive. In this case, the clock 506 selected by the clock switching circuit 52 may be used.
Is output to the reference clock 504 and there is no problem. After the controller 51 outputs the disk drive selection signal 502 and the reference clock output from the disk drive 57 output to the multiplexer output 505 becomes stable after a certain time has elapsed, the controller 51 displays the disk drive switching period. The signal 503 is made inactive. Then, the clock switching circuit 52 switches the reference clock output to 504 from the clock 506 to the multiplexer output 505 without glitch. Switching from the disk drive 55 to the disk drive 57 is performed as described above. FIG. 6 shows an example of the configuration of the controller 51 shown in FIG. 61 is a CPU for processing a disk drive selection request, 62 is a memory for storing the program and control data of the CPU 61, 63 is an input port, and 64 is an output port. 501 is a disk drive switching request signal, 502 is a disk drive selection signal, 503 is a disk drive switching period display signal, and 601 is an internal C
It is a PU bus. The operation of the controller 51 having the configuration shown in FIG. 6 is as follows.
Disk drive switching request signal from input port 63
When 501 is read, the output port 64 is accessed, and the disk drive switching period display signal 503 is set. Next, a disk drive selection signal 502 is output from the output port 64. Then, after a lapse of time sufficient for switching the disk drive, the disk drive switching period display signal is reset to indicate that the switching of the disk drive is completed. FIG. 7 is a timing chart showing control timing in the embodiment shown in FIG. FIG. 8 is a flowchart showing an operation flow of the controller having the configuration of FIG. It is needless to say that the present invention is not limited to the above-described embodiment, but can be realized by other appropriate configurations. [Effects of the Invention] As described above, according to the present invention, in a disk control device that selects and controls an arbitrary disk drive from among a plurality of disk drives, the disk control device interlocks with selection switching of each disk drive. Thus, when selecting and controlling a clock serving as a reference for data transfer with each disk drive, a disk controller having a simple and highly reliable clock switching circuit can be provided. Also,
The reduction in the amount of hardware of the clock switching circuit by applying the present invention has a great effect particularly when the number of disk drives to be controlled and the number of clocks used as a reference for data transfer increase.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. 11: Selection / switching controller, 12: Glitch-less clock switching circuit, 13: 4-input, 1-output multiplexer, 14
... 17: Disk drive, 101: External disk drive selection signal, 102: Disk drive selection signal, 103: Disk drive switching notice signal, 1
04: Disk drive switching completion signal, 105: Clock switching output, 106: Multiplexer output, 107: Clock, 108 to 111: Data transfer reference clock for drives 14 to 17. FIG. 2 shows an example of the configuration of the controller 11 of FIG. 21 delay means, 22 signal transition detection means, 23 delay means, 101 disk drive selection signal from outside, 102 disk drive selection signal, 103 disk drive switching notice signal , 104 ... disk
Drive switching completion signal. FIG. 3 is a timing chart showing control timing in the embodiment shown in FIG. FIG. 4 shows the principle of clock switching of the clock switching circuit 12 in FIG. 1 for switching clocks having two asynchronous relationships without generating a glitch. FIG. 5 is a block diagram showing the configuration of the second embodiment of the present invention. 51: selection / switching controller, 52: glitch-less clock switching circuit, 53: 4-input 1-output multiplexer, 54
... 57 disk drive; 501 external disk drive selection request signal; 502 disk drive selection signal; 503 disk drive switching period display signal; 504 clock switching output; … Multiplexer output, 506 …… Clock, 507-510 …… Drive 54
~ 57 data transfer reference clock. FIG. 6 shows an example of the configuration of the controller 51 in FIG. 61 …… CPU, 62 …… Memory, 63 …… Input port, 64 ……
Output port, 501: Disk drive switching request signal, 502: Disk drive selection signal, 503: Disk drive switching period display signal, 601: Internal CPU bus. FIG. 7 is a timing chart showing control timing in the embodiment shown in FIG. FIG. 8 is a flowchart showing an operation flow of the controller having the configuration of FIG.

Claims (1)

(57) [Claims] A disk drive corresponding to an external selection signal is selected from a plurality of disk drives supplying a first reference clock for defining a data transfer rate, and the selected disk drive is selected. A disk control device for controlling data transfer of a disk drive using a first reference clock supplied by the drive, wherein the disk control device selects a first reference clock output from the plurality of disk drives. A multiplexer for selectively outputting a first reference clock output by the disk drive selected by the selection signal; a second reference clock supplied to the disk drive control device; an output of the multiplexer; Switching circuit for switching a second reference clock and outputting it as a reference clock for the disk control device The switching circuit switches its output from the output of the multiplexer to the second reference clock in response to a change in the select signal, and the multiplexer receives a change in the select signal and the corresponding disk Upon receiving a signal indicating that the reference clock for the drive has been selected, the second
A disk control device for switching from the reference clock to the output of the multiplexer.