JPH03254152A - Semiconductor circuit device - Google Patents

Semiconductor circuit device

Info

Publication number
JPH03254152A
JPH03254152A JP2052496A JP5249690A JPH03254152A JP H03254152 A JPH03254152 A JP H03254152A JP 2052496 A JP2052496 A JP 2052496A JP 5249690 A JP5249690 A JP 5249690A JP H03254152 A JPH03254152 A JP H03254152A
Authority
JP
Japan
Prior art keywords
bonding pad
signal line
bonding
fuse
bonding pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2052496A
Other languages
Japanese (ja)
Inventor
Katsunori Yanase
柳瀬　克典
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2052496A priority Critical patent/JPH03254152A/en
Publication of JPH03254152A publication Critical patent/JPH03254152A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To enable fast operation in case a plurality of bonding pads are provided to the same input/output signal by providing a bonding pad selecting circuit to each inner signal line of each bonding pad. CONSTITUTION:Bonding pad selecting circuit 81 to 83 are constituted of a switch 9, a just 10, etc., of MOS type field effect transistor. Here, a bonding pad 51 is in use and bonding pads 52, 53 are not in use; therefore, the fuse 10 of bonding pad selecting circuits 82, 83 is disconnected while keeping the fuse 10 of the bonding pad selecting circuit 81 as it is. Accordingly, a switch 9 of bonding pad selecting circuits 82, 83 wherein the fuse 10 is disconnected is not conductive and capacities C2, C3 are cut off from an inner signal line 3; a capacity element of the inner signal line 3 is a capacity C1 alone and a capacity of the inner signal line 3 can be reduced. Thereby, bluntness of input/output signal is reduced and rapid operation is realized.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は多種のパッケージに対応できるように同一の入
出力信号に対して複数個のボンディングパットを有する
半導体回路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor circuit device having a plurality of bonding pads for the same input/output signal so as to be compatible with various types of packages.

従来の技術 近年、半導体回路装置は１チツプで多種のパッケージに
対応できるように、同一の入出力信号に対して複数個の
ボンディングパットが設けられている。2. Description of the Related Art In recent years, semiconductor circuit devices have been provided with a plurality of bonding pads for the same input/output signal so that one chip can be used in a variety of packages.

第２図に示すように、内部回路１とパッケージの入出力
ピン２とを接続するために、従来では内部回路１につな
がる内部信号ライン３にはそれぞれ保護回路４１，４□
、４３を介して接続されたボンディングパット５１，５
２．５３が設けられており、使用するパッケージに応じ
て、ここではボンディングパット５１だけが入出力ピン
２にワイヤ６でワイヤボンディングで接続され、ボンデ
ィングパット５□、５３は不使用の状態でパッケージさ
れている。As shown in FIG. 2, in order to connect the internal circuit 1 and the input/output pins 2 of the package, conventionally, the internal signal line 3 connected to the internal circuit 1 has protection circuits 41 and 4□, respectively.
, 43, bonding pads 51, 5 connected via
2.53 is provided, and depending on the package used, only the bonding pad 51 is connected to the input/output pin 2 by wire bonding with the wire 6, and the bonding pads 5□ and 53 are not used when the package is installed. has been done.

ここでは各ボンディングパット５１〜５３と基板７の間
で発生する浮遊容量と各保護回路４１〜４３の内部の接
合容量が容量Ｃ１〜Ｃ３で等価的に表現されている。Here, the stray capacitance generated between each of the bonding pads 51 to 53 and the substrate 7 and the junction capacitance inside each of the protection circuits 41 to 43 are equivalently expressed by capacitances C1 to C3.

発明が解決しようとする課題 このような従来の構成では、内部信号ライン３には前記
の容量（Ｃｔ　＋ＣＱ　＋Ｃ３）が付加された状態にな
っているため、入出力信号を著しく鈍らせるしまうこと
になり、動作の高速化を妨げている問題がある。Problems to be Solved by the Invention In such a conventional configuration, since the above-mentioned capacitance (Ct + CQ + C3) is added to the internal signal line 3, the input/output signal is significantly dulled. There is a problem that prevents faster operation.

本発明は１チツプで多種のパッケージに対応できるよう
に同一の入出力信号に対して複数個のボンディングパッ
トを設けた場合であっても、動作の高速化を実現できる
半導体回路装置を提供することを目的とする。An object of the present invention is to provide a semiconductor circuit device that can realize high-speed operation even when a plurality of bonding pads are provided for the same input/output signal so that one chip can be compatible with various types of packages. With the goal.

課題を解決するための手段 本発明の半導体回路装置は、同一の入出力信号に対して
複数個のボンディングパットを設け、前記ボンディング
パットの一つの特定のボンディングパットと外部入出力
ピンを接続するとともに、各ボンディングパットの内部
信号ラインにそれぞれボンディングパット選択回路を設
け、内部設定に応じて前記特定のボンディングパットを
内部信号ラインに接続し、その他のボンディングパット
を内部信号ラインから分離するよう前記ボンディングパ
ット選択回路を切り換えることを特徴とする。Means for Solving the Problems The semiconductor circuit device of the present invention provides a plurality of bonding pads for the same input/output signal, connects one specific bonding pad of the bonding pads to an external input/output pin, and , a bonding pad selection circuit is provided for each internal signal line of each bonding pad, and the bonding pad is configured to connect the specific bonding pad to the internal signal line and separate the other bonding pads from the internal signal line according to internal settings. It is characterized by switching the selection circuit.

作用 この構成によると、ボンディングパット選択回路によっ
て不使用のボンディングパットが内部信号ラインから切
り離され、内部信号ラインの容量成分が低減される。Effect: According to this configuration, unused bonding pads are separated from the internal signal line by the bonding pad selection circuit, and the capacitance component of the internal signal line is reduced.

実施例 以下、本発明の一実施例を第１図に基づいて説明する。Example An embodiment of the present invention will be described below with reference to FIG.

なお、従来例を示す第２図と同様の作用をなすものには
、同一の符号を付けて説明する。Components having the same functions as those in FIG. 2 showing the conventional example will be described with the same reference numerals.

本発明の半導体回路装置は、第１図に示すように内部信
号ライン３とボンディングパット５□〜５３の間にはボ
ンディングパット選択回路８１〜８３が介装されている
。具体的には、各ボンディングパット選択回路８．〜８
３はＭＯ８型電界効果形トランジスタによるスイッチ９
とヒユーズ１０などで構成されており、ここではボンデ
ィングパット５１が使用状態でボンディングパット５□
。In the semiconductor circuit device of the present invention, as shown in FIG. 1, bonding pad selection circuits 81-83 are interposed between internal signal line 3 and bonding pads 5□-53. Specifically, each bonding pad selection circuit 8. ~8
3 is a switch 9 using an MO8 type field effect transistor.
It consists of a fuse 10 and a fuse 10, and here, the bonding pad 51 is in use and the bonding pad 5□
.

５３が不使用の状態であるため、ボンディングパット選
択回路８．のヒユーズ１Ｇをそのままにして、ボンディ
ングパット選択回路５□と５３のヒユーズＩＯを切断し
ておく。Since the bonding pad selection circuit 8.53 is not in use, the bonding pad selection circuit 8. The fuse 1G of the bonding pad selection circuit 5□ and the fuse IO of the bonding pad selection circuit 53 are cut off while leaving the fuse 1G as it is.

このように構成したため、ヒユーズ１０が切断されたボ
ンディングパット選択回路８゜、８３のスイッチ９が非
導通状態となって容量Ｃ２と０３が内部信号ライン３か
ら切り離され、内部信号ライン３の容量成分は容量Ｃ１
だけになり、内部信号ライン３の容量を（Ｃ２＋Ｃ３）
だけ低減することができる。Because of this configuration, the switch 9 of the bonding pad selection circuit 8° and 83 with the fuse 10 cut off becomes non-conductive, and the capacitors C2 and 03 are separated from the internal signal line 3, and the capacitive component of the internal signal line 3 is the capacity C1
The capacitance of internal signal line 3 is (C2+C3)
can only be reduced.

したがって、入出力信号の鈍りが低減されて高速動作を
実現できる。Therefore, the dullness of input/output signals is reduced, and high-speed operation can be realized.

発明の効果 以上のように本発明によれば、同一の入出力信号に対し
て複数個のボンディングパットを設け、前記ボンディン
グパットの一つの特定のボンディングパットと外部入出
力ピンを接続するとともに、各ボンディングパットの内
部信号ラインにそれぞれボンディングパット選択回路を
設け、内部設定に応じて前記特定のボンディングパット
を内部信号ラインに接続し、その他のボンディングパッ
トを内部信号ラインから分離するよう前記ボンディング
パット選択回路を切り換えるため、１チツプで多種のパ
ッケージに対応できるように同一の入出力信号に対して
複数個のボンディングパットを設けた場合であっても、
付加容量を低減して動作の高速化を実現できる。Effects of the Invention As described above, according to the present invention, a plurality of bonding pads are provided for the same input/output signal, and one specific bonding pad of the bonding pads is connected to an external input/output pin, and each A bonding pad selection circuit is provided for each internal signal line of the bonding pad, and the bonding pad selection circuit connects the specific bonding pad to the internal signal line and separates other bonding pads from the internal signal line according to internal settings. Even if multiple bonding pads are provided for the same input/output signal so that a single chip can support various types of packages,
It is possible to reduce the additional capacitance and achieve faster operation.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の半導体回路装置の一実施例の構成図、
第２図は従来の半導体回路装置の構成図である。 １・・・内部回路、２・・・入出力ピン、３・・・内部
信号ライン、４１−４□、４３・・・保護回路、５．．
５２．５３・・・ボンディングパット、８１，８゜、８
３・・・ボンディングパット選択回路。FIG. 1 is a configuration diagram of an embodiment of a semiconductor circuit device of the present invention;
FIG. 2 is a block diagram of a conventional semiconductor circuit device. 1... Internal circuit, 2... Input/output pin, 3... Internal signal line, 41-4□, 43... Protection circuit, 5. ．．
52.53...Bonding pad, 81.8°, 8
3...Bonding pad selection circuit.

Claims (1)

【特許請求の範囲】[Claims] １、同一の入出力信号に対して複数個のボンディングパ
ットを設け、前記ボンディングパットの一つの特定のボ
ンディングパットと外部入出力ピンを接続するとともに
、各ボンディングパットの内部信号ラインにそれぞれボ
ンディングパット選択回路を設け、内部設定に応じて前
記特定のボンディングパットを内部信号ラインに接続し
、その他のボンディングパットを内部信号ラインから分
離するよう前記ボンディングパット選択回路を切り換え
る半導体回路装置。1. Provide multiple bonding pads for the same input/output signal, connect one specific bonding pad of the bonding pads to an external input/output pin, and select a bonding pad for each internal signal line of each bonding pad. A semiconductor circuit device including a circuit, and switching the bonding pad selection circuit to connect the specific bonding pad to an internal signal line and separate other bonding pads from the internal signal line according to internal settings.
JP2052496A 1990-03-02 1990-03-02 Semiconductor circuit device Pending JPH03254152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2052496A JPH03254152A (en) 1990-03-02 1990-03-02 Semiconductor circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2052496A JPH03254152A (en) 1990-03-02 1990-03-02 Semiconductor circuit device

Publications (1)

Publication Number Publication Date
JPH03254152A true JPH03254152A (en) 1991-11-13

Family

ID=12916328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2052496A Pending JPH03254152A (en) 1990-03-02 1990-03-02 Semiconductor circuit device

Country Status (1)

Country Link
JP (1) JPH03254152A (en)

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