JPH03252726A - Instruction queue - Google Patents

Abstract

PURPOSE:To accelerate the transfer of an instruction code from an instruction fetching part to an instruction decoder by directly sending the instruction code transferred from the instruction fetching part to the instruction decoder when non or small number of effective instruction codes exists in a memory part on an instruction queue. CONSTITUTION:A bypass circuit 7(connected to an input bus 7a and an output bus 7b) which becomes a transfer means performs the bypass transfer of a variable length instruction with a second word length on the input bus 7a to the output bus 7b when no effective variable length instruction exists in the instruction queue 1 which becomes a storage means. When one effective variable length instruction with a first word length exists in the instruction queue 1, a part of the variable length instruction with the second word length on the input bus 7a following the variable length instruction with the first word length in the storage means is transferred to the output bus 7b simultaneously with the readout of the effective variable length instruction with the first word length from the storage means. In such a manner, the transfer of the instruction code from the instruction fetching part to the instruction decoder can be accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an instruction queue that temporarily stores variable-length instructions, and particularly to an instruction queue that improves the efficiency of transferring instruction codes.

[Prior Art] A conventional data processing device (U
(See the specification of SP4,449,184, etc.) has been proposed.

A conventional instruction queue is a halfword (2 bytes, hereinafter referred to as H).
It is used in data processing devices that process variable-length instructions in units (referred to as W).

Note that, as shown in FIG. 3, for example, the data processing device includes an instruction fetch unit that fetches instructions from a memory or an instruction cache external to the device, an instruction decode unit that decodes the fetched instructions, and an instruction decode unit that performs operations instructed by the instructions. The instruction queue 1 is located between the instruction fetch section and the instruction decode section, and buffers the instructions transferred from the instruction fetch section to the instruction decode section. Instructions are written from a word (4 bytes) of memory address or HW boundary.

The data processing of the instruction fetch section will be explained below.

The instruction fetch unit fetches an instruction code word by word from the word boundary of the memory or instruction cache and inputs it to the instruction queue 1. At the time of input, a control signal QIN is output to the instruction queue 1. If the beginning of the instruction code immediately after the branch instruction is not on a word boundary, the instruction fetch unit outputs a control signal JMPHW to the instruction queue 1 to notify that the HW in the one-word instruction code is invalid. When the instruction execution section executes a branch instruction, when the instruction decoding section determines that it is a branch instruction, or after reset, the instruction fetch section outputs a queue clear control signal QCLR to the instruction queue 1. The instruction queue 1 receives control signals QFULL, QEMPO,
Output QEMPI. Control signals QEMPO, QEMP
I is output to the instruction decoding section, and in response to this, the instruction decoding section returns control signals QINCI and QINC2 indicating the amount of instruction code used to the instruction queue 1. Control signal QI
NCI indicates that HW's worth of instruction code has been used, and control signal QINC2 indicates that word's worth of instruction code has been used. Further, the instruction queue 1 outputs a control signal QFULL to the instruction fetch section. While this signal is valid, the instruction fetch section stops transferring the instruction code to the instruction queue 1.

FIG. 3 is a block diagram illustrating the configuration of the conventional instruction queue 1, and the configuration and operation will be explained with reference to the timing chart shown in FIG. 4.

In the figure, 1 is an instruction queue, 2 is a queue memory, and H
It has a capacity of WX8 entries. Input is performed in word units from word boundaries, and output is performed in HW or word units from HW boundaries. Reference numeral 3 denotes a 2-bit input pointer which indicates the entry of the queue memory 2 in which the next instruction code is to be stored in units of words. The input pointer value takes a value from "0" to "3", and rOJ heave around from "3". In addition, the input pointer value is cleared to "0" and "1"
Can be incremented. If the input pointer value is "0" or "1"
”, “2J,” and “3”, entries 1 and 2 of queue memory 2 are respectively entered. Entries 3 and 4, entries 5 and 6. Point to entries 7 and 8.

A 3-bit output pointer 4 indicates the entry position of the queue memory 2 in which the next instruction code to be output is stored in units of HW. The output pointer value ranges from "O" to "
The value of ``7'' is taken, and rQJ slashes around from ``7''. The output pointer value can be cleared by "O", incremented by "1", or incremented by "2". When the output pointer values are from "O" to "7", they indicate entries 1 to 8 of the queue memory 2, respectively. The entry in the queue memory 2 pointed to by the output pointer (PO) 4 and the instruction code for a total of one word stored in the entry are output to the instruction decoding section. 5 is a counter section; The amount of valid instruction codes in 2 is counted in HW units, and a control signal indicating the state of the instruction queue, which will be described later, is output based on the counter value.The counter is cleared by rOJ.

"1" increment, "2" increment.

It can be decremented by "1" or "2", and the counter value can take values from "0" to "8".

The counter unit 5 outputs a queue empty QEMPO when the counter value is rOJ, and the counter unit 5 outputs a queue empty QEMPO when the counter value is “1”.
When the counter value is "7" or "8", the counter section 5 transmits the queue empty signal (QEMP1).
A control signal QFULL is output. Queue empty (control signal) signals QEMPO and QEMPI are output to an instruction decoding section and an instruction queue control section 6 to be described later, and a queue full signal QFULL is output to an instruction fetch section. 6 is an instruction queue control unit, which receives a control signal Q from the instruction fetch unit.
IN, QCLR, JMPHW, receiving control signals QINCI, QINC2 from the instruction decoding section and control signals QEMPO, QEMPI from the counter section 5, input pointer 3. Output pointer 4. It controls the counter value of the counter section 5 and the input/output of the queue memory 2.

Note that in the above data processing device, a non-overlapping two-phase clock φ1. Operates in synchronization with φ2. Writing and reading of the instruction code to queue memory 2 is done using clock φ1.
It will be done at the timing of.

Input pointer 3. Output pointer 4. The counter value of the counter section 5 changes with the clock φ2. control signal QCLR,
QINCI, QINC2, QEMPO, QEMPI, Q
FULL is a signal synchronized with clock φ1, and control signal Q
IN is a signal synchronized with clock φ2.

When the control signal QCLR becomes valid, the instruction queue control unit 6 changes the input pointer 3° and the output pointer 4 at the next clock φ2.
．． The counter value of the counter section 5 is cleared to "0".

When the control signal QIN is input, the instruction code is written to the queue memory 2 pointed by the input pointer 3 at the next clock φl, and the input pointer value is set to "1" at the next clock φ2.
Increment. When the control signal QINCI is input, the value of the output pointer 4 is incremented by "1" at the next clock φ2, and when the control signal QINC2 is input,
The value of the output pointer 4 is incremented by "2" at the next clock φ2. In addition, the value of the counter of the counter section 5 is changed to r+24 at the next clock φ2 to which the control signal QIN is input.
, "-1" at the next clock φ2 to which the control signal QINCI is input, and "-2" at the next clock φ2 to which the control signal QINC2 is input.

Next, the operation of the instruction queue 1 will be explained according to the timing chart of FIG.

First, in synchronization with clock φ1, the input pointer 3. Output pointer 4. The counter value of the counter section 5 is cleared by rOJ.

At this time, the input pointer 3 points to entries 1 and 2 of the queue memory 2 where the instruction code will be written next, and the output pointer 4 points to entry 1.

At this time, since the counter value is rOJ, the control signal QEMPO becomes valid and the control signal QEMPI and the control signal QFULL become invalid at the next clock φ2. Since the control signal QEMPO becomes valid, the instruction decoding section recognizes that no instruction code exists in the instruction queue 1. At the next clock ψ2, the control signal QCQIN becomes valid, and at the next clock φ1, one word of instruction code is transferred from the instruction fetch unit to the instruction queue 1, and the entry 1.0 indicated by the input pointer 3 of the queue memory 2 is transferred. Written to entry 2. At the next clock φ2, the value of the input pointer 3 is incremented by 1, and the entry 3 and entry 4 of the queue memory 2 to which the next instruction code is input are indicated, and the input of one word of the instruction code is indicated. In order to indicate this, the counter value of the counter section 5 is incremented by "+2". Next clock φ1
Then, the instruction code stored in the entry 1 of the queue memory 2 indicated by the output pointer 4 and the entry 2 following the entry 1 is output to the instruction decoding section. Reflecting the fact that the counter value becomes "2" at the same clock φ1, the control signal QEMPO becomes invalid. In response to this, the instruction decoding section returns a control signal QINCI to notify that the instruction code of the HW has been decoded using this clock φ1. When the control signal QINCI is returned, it is determined that the instruction code has been used in HW, and at the next clock φ2, the value of the output pointer 4 is incremented by 1, and the entry 2 in which the instruction code to be output to the instruction decoding section is located is pointed to. ,
The counter value of the counter unit 5 is r-IJL, and the number of valid instruction codes in the queue memory 2 is HW. Here, the control signal QIN becomes valid with the same clock φ2. At the next clock φ1, the control signal QEMPI indicating that the counter value is "1" is enabled. In response to the second control signal QIN, the 1-word instruction code transferred from the instruction fetch unit at clock φ1 is written to entry 3 and entry 4 of queue memory 2 indicated by input pointer 3. At the next clock φ2, the input pointer 3 is incremented by 1, and then the queue memory 2 is instructed to write an instruction code into entries 5 and 6, and the counter value of the counter unit 5 is incremented by 2. In response to the counter value becoming "3" at the next clock φ1, the control signal QEMP is
1 becomes invalid and notifies the instruction decoding unit that an instruction code of one word or more is present in instruction queue 1. In response to this, the instruction decoding section returns a control signal QINC2 for decoding one word worth of instruction code using the same clock φ1. At the next clock φ2, the value of output pointer 4 is changed to “
2" is incremented to indicate entry 4 of queue memory 2 where the instruction code to be output next exists, and the counter value is "-2" because a 1-word instruction code was output from queue memory 2 at the previous clock φ1. It becomes "1". In response to this, the control signal QEMP 1 becomes valid at the next clock φ1.

[Problems to be Solved by the Invention] As described above, the conventional instruction queue 1 is arranged with the expectation of buffering the transfer of instruction codes from the instruction fetch section to the instruction decoding section. The conventional instruction queue 1 stores the instruction code output by the instruction fetch section and then outputs it to the instruction decoding section.
There is a problem in that the transfer of instructions is delayed if there is no valid instruction code in the instruction code or if the word length is less than the word length required by the instruction decoding section.

This invention was made to solve the above problems, and when there is no valid instruction code in the instruction queue or when the valid instruction code is less than the word length required by the instruction decoding section, the instruction fetch It is an object of the present invention to provide an instruction queue which stores instruction codes sent from a section in an instruction queue and which can also be bypass-transferred to an instruction decoding section.

[Means for Solving the Problems] An instruction queue according to the present invention stores variable-length instructions whose basic unit is a first word length, and whose unit is a second word length consisting of a plurality of first word lengths. a storage means for reading the first or second word length as a unit; an input bus connected to the storage means having a second word length width; and a second word length width connected to the storage means; is connected to the output bus and the input bus, and when there is no valid variable length instruction in the storage means, the variable length instruction of the second word length is bypass-transferred to the output bus, and the output bus is connected to the input bus. When there is one first word length variable length instruction valid in the input bus, one of the second word length variable length instructions following the first word length variable length instruction in the storage means on the input bus. and transfer means for reading out the effective variable length instruction of the first word length from the storage means and transferring it to the output bus at the same time.

[Operation] In this invention, the transfer means is connected to the input bus and the output bus, and when there is no valid variable length instruction in the storage means, outputs the variable length instruction of the second word length on the input bus. When there is a valid first word length variable length instruction in the storage means, a second word length instruction on the input bus following the first word length variable length instruction in the storage means is bypass transferred to the input bus. A part of the word length variable length instruction is transferred to the output bus at the same time as a valid first word length variable length instruction is read from the storage means.

[Embodiment] FIG. 1 is a block diagram illustrating the structure of an instruction queue showing an embodiment of the present invention, and the same parts as in FIG. 3 are given the same reference numerals.

In the figure, 1 is an instruction queue, 2 is a queue memory, and H
It has a capacity of WX8 entries. Input is performed in word units from word boundaries, and output is performed in HW or word units from HW boundaries.

Reference numeral 3 is a 2-bit input point ink, which instructs the entry of the queue memory 2 in which the next instruction code is to be stored in units of words. The input pointer value takes the value "3" from rOJ,
Wraps around from "3" to "0". Furthermore, the input pointer value can be cleared to "0" and incremented by "1". Input pointer value is "O", "l", "2", "3"
, entries 1 and 22 . of queue memory 2 respectively. Entries 3 and 4. Entries 5 and 6. Point to entries 7 and 8.

A 3-bit output pointer 4 indicates the entry position of the queue memory 2 in which the next instruction code to be output is stored in units of HW. The output pointer value changes from "0" to "
It takes a value of ``7'' and wraps around from ``7'' to rOJ. The output pointer value is cleared to "0" and incremented by "1".

It can be incremented by "2". The output pointer value is r
When OJ is "7", entries 1 to 8 of the queue memory 2 are respectively indicated. This output pointer (PO)
A total of one word of instruction codes stored in the entry of the queue memory 2 indicated by No. 4 and the subsequent entry are output to the instruction decoding section.

A counter section 5 counts the amount of valid instruction codes in the queue memory 2 in HW units, and outputs a control signal indicating the state of the instruction queue 1, which will be described later, based on the counter value. The counter can be cleared by rOJ, incremented by "1", incremented by "2", decremented by "1", and decremented by "2", and the counter value can take values from "0" to "8".

The counter unit 5 outputs a queue empty QEMPO when the counter value is rOJ, and the counter unit 5 outputs a queue empty QEMPO when the counter value is rOJ.
When , the counter section 5 outputs a queue empty signal QEMP1, and when the counter value is "7" or "8", the counter section 5 outputs a queue full signal QFULL. However, the control signal QEMPO,
QEMPI is set to a counter value of "0" by an instruction queue control unit 6, which will be described later, when the control signal QIN is input.

It is canceled for one clock regardless of "1".

Reference numeral 7 denotes a bypass circuit constituting a bypass means, one of which is connected to input bus flow a and the other connected to output bus flow b, and when there is no instruction code in queue memory 2, the second word length on input bus flow a is connected. A variable length instruction (32 bits in this embodiment) is bypass-transferred to output bus buffer b as the second word length, and if one instruction code exists in queue memory 2, it is written to queue memory 2. Following the instruction code <HW, the instruction code <HW is simultaneously transferred to the output bus b. Queue empty signal QEMPO,
QEMPI is output to an instruction decode unit and an instruction queue control unit 6, which will be described later, and a queue full signal QFULL is output to an instruction fetch unit. 6 is an instruction queue control unit which receives control signals QIN, QCLR, JMPHW,
Control signals QINCI and QINC2 from the instruction decoding section
and control signals QEMPO and QEM from the counter section 5
Receive PI and input pointer 3. It controls the output pointer 4, the counter value of the counter section 5, and the input/output control of the queue memory 2.

In addition, in the data processing device equipped with the above-mentioned instruction queue 1,
It operates in synchronization with non-overlapping two-phase clocks φ1 and φ2. Writing and reading of instruction codes to and from the queue memory 2 are performed at the timing of clock φ1. Input pointer 3. Output pointer 4. The counter value of the counter section 5 changes with the clock φ2. Control signal QCLR, QIN
C1, QINC2, QEMPO, QEMPI, QFIL
L is a signal synchronized with clock φ1, and control signal QIN is a signal synchronized with clock φ2.

In the instruction queue 1 configured in this way, the bypass circuit 7 (in this embodiment, connected to the input bus a and the output bus b) serving as a transfer means stores valid information in the instruction queue 1 serving as a storage means. When there are no variable length instructions,
When a variable-length instruction with a second word length on input bus a is bypass-transferred to output bus b, and there is one valid variable-length instruction with a first word length in instruction queue 1, the instruction in the storage means is 1st
Subsequently to the variable-length instruction with the word length of Transfer to b.

Specifically, the instruction queue control unit 6 uses the control signal QCLR
becomes valid, the input pointer 3. is activated at the next clock φ2.
Output pointer 4. The counter value of the counter section 5 is cleared rOJ. When the control signal QIN is input, an instruction code is written into the queue memory 2 pointed by the input pointer 3 at the next clock φ1, and the input pointer value is incremented by "1" at the next clock φ2. When the control signal QINCI is input, the value of the output pointer 4 is incremented by "1" at the next clock φ2, and when the control signal QINC2 is input, the value of the output pointer 4 is incremented by "1" at the next clock φ2.
2” increment.

Also, at the next clock φ2 to which the control signal QIN is input, the counter value of the counter section 5 is set to "+2", and the control signal QI
r-IJ at the next clock φ2 inputted from NCI, and "--IJ" at the next clock φ2 inputted from control signal QINC2.
2”. However, when the control signal QIN and the control signal QINCI are valid at the same time at the timing of the corresponding clock φ2, the counter value is changed to r+IJl, and when the control signal QIN and the control signal QINC2 are valid at the same time, the counter value is not changed.

Next, the operation of the instruction queue 1 shown in FIG. 1 will be explained with reference to FIG.

First, in synchronization with clock φ1, the input pointer 3. Output pointer 4. The counter value of the counter section 5 is cleared rOJ. At this time, the input pointer 3 points to entries 1 and 2 of the queue memory 2 into which the instruction code is written, and the output pointer 4 points to entry 1. At this time, since the counter value is rOJ, the control signal QEMP is output at the next clock φ2.
O is valid, control signal QEMP 1 and control signal QFULL
becomes invalid. Since the control signal QEMPO becomes valid, the instruction decoding section recognizes that no instruction code exists in the instruction queue 1. At the next clock φ2, the control signal QIN becomes valid, and at the next clock φ1, one word of instruction code is transferred from the instruction fetch section to the instruction queue 1, and the end point 1. Write the instruction code to entry 2. This clock φ1 invalidates the control signal QEMPO to indicate the existence of the instruction code to the instruction decoding section, and also enables the bias circuit 7 to transfer the instruction code to the instruction decoding section. In response to the control signal QEMPO becoming invalid, the instruction decoding section returns a control signal QINCI to notify that the instruction code of the HW has been decoded using this clock φ1.

At the next clock φ2, the value of input pointer 3 is incremented by "1", and the next instruction code is written to queue memory 2.
The entry for entry 3. At the same time, the value of the output pointer 4 is incremented by "1" to point to the entry 2 in which the instruction code to be outputted to the instruction decoding section next exists.

Further, the counter value of the counter unit 5 is set to "+1", indicating that the number of valid instruction codes in the queue memory 2 is HW. At the next clock φ1, the control signal QEMP 1 indicating that the counter value is "1" is enabled. clock φ
When the second control signal QIN is input in synchronization with 2, one word of instruction code is transferred from the instruction fetch unit to the instruction queue 1 at the next clock φ1, and the entry of the queue memory 2 pointed to by the input pointer 3 is transferred to the instruction queue 1. 3. Written to entry 4. At this clock φ1, the HW instruction code indicated by the counter value "1" from the entry 2 of the queue memory 2 indicated by the output pointer 4, and the instruction code of the entry 2 via the bypass circuit 7, the <HW instruction code A total of one word is transferred to the instruction decoder, and the control signal QEMP1 is invalidated to inform the instruction decoding section that an instruction code of Ⅰ words or more exists in the instruction queue 1. In response to this, the instruction decoding section returns a control signal QINC2 for decoding one word worth of instruction code.

At the next clock φ2, the value of the input pointer 3 is incremented by "1", and the next input entry of the queue memory 2 is set to entry 5. At the same time, the value of the output pointer 4 is incremented by 2 to point to the entry 4 of the queue memory 2 where the instruction code to be output next exists. Further, the counter value remains at "1" and does not change because the input and output of the instruction code to and from the queue memory 2 are both 1 word at the previous clock φ1.

In this way, the bypass circuit 7 is placed in parallel with the queue memory 2, and the one-word instruction code transferred from the instruction fetch unit to the instruction queue 1 in units of words is stored in the queue memory 2 once. , instead of sending it to the instruction decoding section, when the valid instruction code in the queue memory 2 is "0", all <HW> is directly transferred to the instruction decoder when the valid instruction code is HW.

In the above embodiment, instruction queue 1 having a second word length width of 32 bits was explained as an example, but the instruction queue 1 is not limited to this bit width, and other bit widths may be used as the second word length width. It can also be easily applied to an instruction queue with a word length width of 2.

[Effects of the Invention] As explained above, the present invention stores variable-length instructions whose basic unit is a first word length, and stores variable-length instructions whose basic unit is a second word length consisting of a plurality of first word lengths. or a storage means for reading in units of second word length, an input bus connected to the storage means and having a second word length width, and an output bus connected to the storage means and having a second word length width; This output bus is connected to the input bus, and when there is no valid variable length instruction in the storage means, bypass transfer is made to the output bus of the variable length instruction of the second word length, and one valid variable length instruction in the storage means is connected. When a variable length instruction with one word length exists, a part of the variable length instruction with a second word length following the variable length instruction with the first word length in the storage means on the input bus is transferred from the storage means. Since a transfer means is provided that reads a valid variable-length instruction of the first word length and simultaneously transfers it to the output bus, when there is no valid instruction code or only a small amount exists in the memory portion on the instruction queue, the instruction is read. The instruction code transferred from the fetch section can be sent directly to the instruction decoder,
This has the effect of speeding up the transfer of instruction codes from the instruction fetch unit to the instruction decode unit.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the configuration of an instruction queue showing an embodiment of the present invention, FIG. 2 is a timing chart explaining the operation of FIG. 1, and FIG. 3 illustrates the configuration of a conventional instruction queue. FIG. 4 is a timing chart explaining the operation of FIG. 3. In the figure, 1 is an instruction queue, 2 is a queue memory, 3 is an input pointer, 4 is an output pointer, 5 is a counter section, and 6
7 is an instruction queue control unit, and 7 is a via bus circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] An instruction queue provided between an instruction fetch section and an instruction decoding section, wherein variable length instructions whose basic unit is a first word length are transferred into units of a second word length consisting of a plurality of first word lengths. a storage means for storing and reading out the first or second word length as a unit; an input bus having a second word length width connected to the storage means; an output bus having a word length width, the output bus being connected to the output bus and the input bus, and when the valid variable length instruction does not exist in the storage means, the output bus for variable length instructions having the second word length; bypass transfer to a valid one in said storage means.
When there are two variable length instructions of the first word length, a portion of the variable length instructions of the second word length following the variable length instructions of the first word length in the storage means on the input bus. and transfer means for reading out the effective variable length instruction of the first word length from the storage means and transferring it to the output bus at the same time.