JPH0797319B2 - Microcomputer system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer system, and more particularly, to a microcomputer system in which instruction execution by a microprocessor is made efficient.

[Conventional technology]

The conventional microcomputer system shown in FIG.
16-bit wide input / output terminal 80 for controlling data input / output processing, arithmetic processing, and the entire microcomputer system
A microprocessor 800 having 0-1 and an address latch 101 for demultiplexing multiplexed address information, instruction code and input / output data input / output from the input / output terminal 800-1 of the microprocessor 800, A program memory 801 in which a program executed by the microprocessor 800 is stored, a data memory 103 in which processing data of the microprocessor 800 is stored, and a peripheral input / output device 104 that interfaces data input / output between the outside and the microprocessor 800. These units 800, 101, 801, 103, 104 are 16 units in which address information, instruction code and input / output data are multiplexed.
It is connected by a bit-width address / data bus 106 (hereinafter referred to as an AD bus) and a 16-bit width address bus 107 (hereinafter referred to as an A bus) demultiplexed from the AD bus 106 by the address latch 101. .

The input / output terminal 800-1 of the microprocessor 800 sends the multiplexed address information, instruction code, and input / output data to the AD bus 106 as described above. Since the microprocessor 800 has an address width of 16 bits, it has a memory space of 64 Kbytes, and reads an instruction code and reads / writes data in units of 8 bits or 16 bits through the AD bus 106.

An input control signal to the microprocessor 800 is a reset signal 800-2 for initializing hardware in the microprocessor 800, and an output control signal from the microprocessor 800 is an address latch 1
01 is an address latch enable signal 800-3 (hereinafter referred to as ALE signal) that gives a timing for latching address information on the AD bus 106, and the microprocessor 800 reads data from the data memory 103 and the peripheral input / output device 104 and executes a program. There are a read signal 800-4 for fetching an instruction code from the memory 801, and a write signal 800-5 for writing data to the data memory 103 and the peripheral input / output device 104. Here, the peripheral input / output device 104 is assumed to be mapped in the memory space, and a signal for distinguishing the data memory 103 from the peripheral input / output device 104 when the microprocessor 800 accesses the data is not required.

Next, the hardware configuration in the microprocessor 800 shown in FIG. 9 will be described.

The microprocessor 800 pre-reads from a program counter 900 (hereinafter referred to as a PC) that points to an address in the program memory 801 in which an instruction code to be executed next, an incrementer 901 that increments the PC 900, and the program memory 801. An instruction queue 902 that stores instruction codes, an instruction register 903 (hereinafter referred to as IR) that holds the instruction code read from the instruction queue 902, and various controls related to instruction execution by decoding the instruction code stored in the IR903. Instruction decoder 904 that outputs signals and instruction decoder 9
It is composed of a process execution unit 905 which receives a control signal from 04 and executes an instruction process, and an execution control unit 906 which controls the overall operation of the microprocessor 800.

From the process execution unit 905 to the execution control unit 906, a bus request signal 905-1 (hereinafter referred to as a BRQ signal) requesting activation of a data read / write cycle with the data memory 103 or the peripheral input / output device 104 accompanying instruction execution. Is output. When the execution control unit 906 receives a data read / write cycle activation request from the process execution unit 905 by the BRQ signal 905-1, the execution control unit 906 sends an acknowledge signal 906-1 (hereinafter referred to as an acknowledge signal) to the process execution unit 905.
ACK signal). In addition, from the instruction queue 902 to the execution control unit 906, a queue ready signal 902-1 indicating that the instruction queue 902 contains an appropriate number of instruction codes and a queue full signal 902-indicating that the instruction queue 902 is full.
2 is output. Next, the bus cycle operation of the microcomputer system shown in FIG. 8 will be described.

The bus cycle of the microprocessor 800 is composed of three basic operation states consisting of a plurality of clocks and an empty state, and the execution control unit 906 has three operation signals B1, B2, B3 which are the basic timing signals of the bus cycle. By outputting the B1 signal indicating that the bus cycle is empty, the data read / write cycle with the data memory 103 or the peripheral input / output device 104 by the instruction execution and the instruction code fetch cycle from the program memory 801 can be performed. It controls the bus cycle.

Next, a timing chart of two basic bus cycles of (1) instruction code fetch cycle (2) data read / write cycle will be shown to explain the operation of each unit. A timing chart of the instruction code fetch cycle is shown in FIG. 10, a timing chart of the data read cycle is shown in FIG. 11 (A), and a timing chart of the data write cycle is shown in FIG. 11 (B).

(1) Instruction code fetch cycle The instruction code fetch cycle consists of three timings B1, B2 and B3. Microprocessor 800 is A at B1 timing
The 16-bit address information of the instruction code to be read next stored in the program memory 801 is output through the D bus 106, and the ALE signal 800-3 is set to active high. As a result, the address latch 101 latches the address information on the AD bus 106 and outputs it on the A bus 107.

At the B2 timing and the B3 timing, 16-bit address information is output to the A bus 107 via the address latch 101. The microprocessor 800 uses the AD bus 106 to prepare for the fetch cycle in the first half of the B2 timing.
After floating the
Set the read signal 800-4 to active high at the B3 timing. As a result, the instruction code starts to be output on the AD bus 106 from the program memory 801 pointed to by the address information on the A bus 107. And a microprocessor 800
Captures the instruction code on the AD bus 106 in the instruction queue 902 at a predetermined clock within the B3 timing when the instruction code on the AD bus 106 becomes valid.

(2) Data read / write cycle The data read / write cycle consists of three timings B1, B2, and B3. Microprocessor 800 with B1 timing
16 for data read / write through AD bus 106
Bit address information is output and ALE signal 800-
Set 3 to active high. This enables address latch
101 latches the address information on the AD bus 106 and outputs it on the A bus 107. At the B2 timing and the B2 timing, 16-bit address information is output to the A bus 107 via the address latch 101.

Microprocessor for data read cycles
800 A to prepare for read cycle in the first half of B2 timing
After the floating state on the D bus 106, the read signal 800-4 is set to active high in the latter half of B2 timing and B3 timing. As a result, the data memory 103 or the peripheral input / output device 104 pointed to by the address information on the A bus 107
Starts outputting data from AD bus 106. And
The microprocessor 800 uses the predetermined clock within the B3 timing when the data on the AD bus 106 becomes valid.
Capture the above data.

Microprocessor for data write cycle
The 800 sets the write signal 800-5 to active high at the latter half of the B2 timing and the B3 timing, and outputs the write data on the AD bus 106. Then, at the specified clock within B3 timing when the data on AD bus 106 becomes valid, AD
The data on the bus 106 is written to the data memory 103 or the peripheral input / output device 104 designated by the address information on the A bus 107.

In this way, the data read / write cycle with the data memory 103 or the peripheral I / O device 104 by the instruction execution and the instruction code fetch cycle from the program memory 801 are executed with the same number of bus cycles, and B1, B2, B3
Any one of data read, data write, and instruction code fetch is performed in one bus cycle consisting of.

The execution control unit 906 uses the queue ready signal from the instruction queue 902.
902-1, cue full signal 902-2, and the output timing of the basic timing signals of B1, B2, B3, ..., BI according to the state of the BRQ signal 905-1 from the processing execution unit 905, and
The start priority of the data read / write cycle and the instruction code fetch cycle is controlled, and the control of the execution control unit 906 will be described with reference to a timing chart.

FIG. 12 shows the case where the cue ready signal 902-1 is active, and FIG. 13 shows the case where the cue ready signal 902-1 is inactive.

(1) When the queue ready signal 902-1 is active When the BRQ signal 905-1 is inactive, the instruction queue
Queue full signal 902-2 is output from 902
The instruction code fetch cycle is continuously activated until the instruction code in 902 is full. When the cue full signal 902-2 from the instruction queue 902 becomes active, the execution control unit 906 outputs BI until the BRQ 905-1 becomes active or the cue full signal 902-2 becomes inactive again. And keep the bus cycle idle. As shown in FIG. 12, when the BRQ signal 905-1 becomes active, the start priority of the data read / write cycle is higher than the start priority of the instruction code fetch cycle, so A data read / write cycle is activated immediately after the end of the bus cycle (if any).

FIG. 12 shows the case where the data write cycle in the BI cycle is accepted.

(2) When the queue ready signal 902-1 becomes inactive The instruction code fetch cycle is continuously activated regardless of the state of the BRQ signal 905-1. In this case, the start priority of the instruction code fetch cycle is data read / read.
BRQ signal 905 because it is higher than the start priority of the write cycle.
Even if -1 becomes active, the activation of the data read / write cycle is delayed until the queue ready signal 902-1 becomes active by the instruction code fetch.

FIG. 13 shows the case where the activation of the data write cycle is kept waiting until the queue ready signal 902-1 becomes active.

[Problems to be solved by the invention]

In the above-described conventional microcomputer system, instruction code fetch and data read / write are sequentially performed on one data bus, so that the delay of one bus cycle becomes a bus neck, and the performance of the entire system is improved. I will drop it. Further, if the number of times of data access between the microprocessor and the memory or the peripheral input / output device becomes frequent, the data bus is occupied by the data read / write processing each time as described with reference to FIG. 12, and the instruction code is transferred to the instruction queue. The number of empty bus cycles to be read into will be reduced. As a result, not only the instruction code prefetching effect due to the provision of the instruction queue cannot be obtained, but also the lack of the instruction code in the instruction queue as described with reference to FIG. 13 causes the microprocessor to start the instruction code fetch cycle. In order to give priority to, the start of the data read / write cycle accompanying the instruction execution is delayed, and as a result, the instruction execution time becomes long.

[Means, Actions and Effects for Solving Problems]

A microcomputer system of the present invention is a microprocessor, a data memory, a program memory, a first bus connecting the microprocessor and the data memory, and a second bus connecting the microprocessor and the program memory. Bus and a third bus that connects the data memory and the program memory in common via the first bus and an address latch, and the microprocessor reads a program read from the program memory. A queue memory that stores the data is included, and an incrementer that increments the address transferred through the address latch as an initial value is included in the program memory to access the data memory and read the data. / Said first bus for writing The second bus for transferring the program read from the program memory is used in parallel according to the content of the incrementer, and the program read from the program memory is stored in the queue memory. It is characterized by In the microcomputer system having such a structure, when the information processing of the data is executed in association with the data information means by using the first transfer means based on the program command already accepted by the data processing means. But
In parallel with this, new program instructions can be sequentially accepted from the program supply means. Therefore, it is not necessary to interrupt the processing of the data information associated with the data information means for receiving the program instruction, and it is necessary to process the data information associated with the data information means during the acceptance of the program instruction. The acceptance of will not be interrupted. As a result, the waiting time is eliminated during the execution of the program instruction, and the processing speed of the data information can be improved.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a microcomputer system according to the present invention.

The microcomputer system shown in FIG. 1 is a 16-bit wide input / output terminal 100-1 for controlling data input / output processing, arithmetic processing, and the entire microcomputer system.
And a microprocessor 100 having an 8-bit wide input / output terminal 100-8, and an input / output terminal 10 of the microprocessor 100.
0-1, an address latch 101 for demultiplexing multiplexed address information and input / output data, a memory unit 102-1 in which a program executed by the microprocessor 100 is stored, A program memory including an instruction pointer 102-2 (hereinafter referred to as IP) that points to an address of a memory unit 102-1 in which an instruction code executed by the microprocessor 100 is stored, and an incrementer 102-3 that increments the IP 102-2. 102, a data memory 103 for storing processing data of the microprocessor 100, and a peripheral input / output device 104 for interfacing data input / output between the outside and the microprocessor 100, and these units output an instruction code. 8-bit wide instruction bus 105 (hereinafter referred to as I-bus) and multiple 16-bit wide address / data bus 106 (hereinafter referred to as AD bus) for transmitting the address information and input / output data, and demultiplexed latched by address latch 101 via AD bus 106. 16-bit wide address bus 107 (hereinafter referred to as A bus)
Connected by.

16-bit wide input / output terminal 100 of microprocessor 100-
1 is connected to an AD bus 106 in which address information and input / output data are multiplexed, and an 8-bit wide input terminal 100-8 is connected to an I bus 105 for outputting an instruction code. The microprocessor 100 has an address width of 1
Since it is 6 bits, it has a memory space of 64 Kbytes and I bus 10
5 and the AD bus 106 are used to read an instruction code in 8-bit units and read / write data in 8-bit or 16-bit units.

An input control signal to the microprocessor 100 is a reset signal 100-2 for initializing the hardware in the microprocessor 100, and an output control signal from the microprocessor 100 is an address latch 1
When 01 is an address latch enable signal 100-3 (hereinafter referred to as an ALE signal) that gives a timing for latching address information on the AD bus 106, the microprocessor 100 reads data from the data memory 103 and the peripheral input / output device 104. Read signal 100-4, a write signal 100-5 for writing data to the data memory 103 and the peripheral input / output device 104, and an instruction from the memory unit 102-2 in the program memory 102 for instruction code fetching. Instruction read signal 100-6 (hereinafter referred to as IRD signal) for reading the code and instruction pointer write signal 100-7 for writing the read address of the instruction code to the IP 102-2 in the program memory 102 at the time of branch processing etc.
(Hereinafter referred to as IPWR signal). Here, the peripheral input / output device 104 is assumed to be mapped in the memory space, and a signal for distinguishing the data memory 103 and the peripheral input / output device 104 at the time of data access of the microprocessor 100 is not required.

Next, FIG. 2 shows a hardware configuration in the microprocessor 100.

The microprocessor 100 prefetches from the program memory 102, a program counter 200 (hereinafter referred to as a PC) that points to an address in the program memory 102 in which an instruction code to be executed next is stored, an incrementer 201 that increments the PC 200, and the program memory 102. An instruction queue 202 that stores instruction codes, an instruction register 203 (hereinafter referred to as IR) that holds the instruction code read from the instruction queue 202, and various controls related to instruction execution by decoding the instruction code stored in the IR 203 Instruction decoder 204 for outputting signals and instruction decoder 2
It is composed of a process execution unit 205 which receives a control signal from 04 and executes an instruction process, and an execution control unit 206 which controls the overall operation of the microprocessor 100.

From the process execution unit 205 to the execution control unit 206, a bus request signal 205-1 (hereinafter referred to as BRQ) requesting activation of a data read / write cycle with the data memory 103 or the peripheral input / output device 104 accompanying instruction execution, , A branch signal 205-2 (hereinafter referred to as a BRCH signal) requesting activation of a branch processing cycle is output, and the execution control unit 206 receives a data read / write cycle activation request or a branch approximate cycle activation request, An acknowledge signal 206-1 (hereinafter referred to as an ACK signal) is output to the processing execution unit 205. Also,
From the instruction queue 202 to the execution control unit 206, the instruction queue 202
A cue ready signal 202-1 indicating that an appropriate number of instruction codes are stored in and a cue full signal 202-2 indicating that the instruction queue 202 is full are output.

Next, the bus cycle operation of the microcomputer system shown in FIG. 1 will be described.

The bus cycle of the microprocessor 100 is composed of three basic operation states consisting of a plurality of clocks and an empty state, and the execution control unit 206 has three operation signals of T1, T2 and T3 which are the basic timing signals of the bus cycle. Also, by outputting a TI signal indicating that the bus cycle is empty, a data read / write cycle with the data memory 103 or the peripheral I / O device 104 by instruction execution and an instruction code fetch cycle from the program memory 102 can be performed. It controls the bus cycle.

Next, a timing chart of three basic bus cycles of (1) instruction code fetch cycle, (2) data read / write cycle, and (3) branch branch cycle will be shown to explain the operation of each unit. The timing chart of the instruction code fetch cycle is shown in FIG. 3, the timing chart of the data read cycle is shown in FIG. 4 (A), the timing chart of the data write cycle is shown in FIG. 4 (B), and the timing chart of branch processing is shown. Each is shown in FIG.

(1) Instruction code fetch cycle The instruction code fetch cycle consists of two timings T2 and T3. The microprocessor 100 makes the IRD signal 100-6 active high from the latter half of the T2 timing to the T3 timing. The IP 102-2 uses the result incremented by the incrementer 102-3 at the falling edge of the IRD signal 100-6 and the memory unit 102-1 at the rising edge of the IRD signal 100-6.
Output to. As a result, the program memory 102 becomes the memory unit 102 pointed to by the incremented IP 102-2.
Instruction code from -1, I bus from the latter half of T2 timing
Output to 105. In the microprocessor 100, the instruction code read out from the program memory 102 onto the I bus 105 is
I bus with a predetermined clock within the valid T3 timing
The instruction code on 105 is fetched into the instruction queue 202.

(2) Data read / write cycle The data read / write cycle consists of three timings T1, T2 and T3. Microprocessor 100 at T1 timing
16 for data read / write through AD bus 106
Bit address information is output and ALE signal 100-
Set 3 to active high. This enables address latch
101 latches the address information on the AD bus 106 and outputs it on the A bus 107. At the T2 timing and the T3 timing, 16-bit address information is output to the A bus 107 via the address latch.

Microprocessor for data read cycles
100 sets the AD bus 106 to a floating state in preparation for a read cycle in the first half of T2 timing, and then sets the read signal 100-4 to active high in the second half of T2 timing and T3 timing. As a result, the data memory 103 or the peripheral input / output device 104 pointed to by the address information on the A bus 107 starts to output data on the AD bus 106. Then, the microprocessor 100 reads the data on the AD bus 106 at a predetermined clock within T3 timing when the data read on the AD bus 106 becomes valid.

Microprocessor for data write cycle
100 sets the write signal 100-5 to active high at the latter half of T2 timing and T3 timing, and outputs write data on the AD bus 106. Then, at a predetermined clock within the T3 timing when the data on the AD bus 106 becomes valid,
The data on the AD bus 106 is written to the data memory 103 or the peripheral input / output device 104 designated by the address information on the A bus 107.

Further, in the data read / write cycle, when the queue full signal 202-2 is inactive and there is a margin in the instruction code in the instruction queue 202, (1 is set at the timing of T2 and T3 in parallel with the data read / write cycle. The instruction code fetch cycle described in 1) is activated, the instruction code is read from the program memory 102, and is stored in the instruction queue 202. When the cue full signal 202-2 is active, only the data read / write cycle is activated.

(3) Branch processing cycle The branch processing cycle consists of three timings T1, T2, and T3.

At the T1 timing, the microprocessor 100 outputs 16-bit address information of the branch destination through the AD bus 106 and activates the IPWR signal 100-7 and the ALE signal 100-3. As a result, the address latch 101 latches the branch destination address on the AD bus 106 and outputs it on the A bus 107,
The program memory 102 reads the 16-bit branch destination address output on the A bus 107 and stores it in the IP 102-2.

The next microprocessor 100 starts from the second half of T2 timing to T
IRD signal 100-6 is activated at 3 timings. IP1
02-2 shows the stored branch destination address as IRD signal 100-
At the rising edge of 6, the data is output to the memory unit 102-1. At this time, the signal that latches the output from the incrementer 102-3 to the IP 102-2 is suppressed by the IPWR signal 100-7. As a result, the program memory 102 outputs the instruction code from the memory unit 102-1 designated by the IP 102-2 to the I bus 105 from the latter half of the T2 timing. The microprocessor 100 fetches the instruction code on the I bus 105 into the instruction queue 202 at a predetermined clock within the T3 timing when the instruction code read from the program memory 102 onto the I bus 105 becomes valid.

Next, the execution control unit 206 actually receives T1, T2, T3, depending on the states of the queue ready signal 202-1, the queue full signal 202-2 from the instruction queue 202 and the BRQ signal 205-1 from the processing execution unit 205.
How to control the output timing of the TI basic timing signal will be described by showing a timing chart.

Fig. 6 shows the case where the BRQ signal 205-1 is inactive.
FIG. 7 shows the case where the Q signal 205-1 becomes active.

(1) When the BRQ signal 205-1 is inactive The instruction code fetch cycle is continuously activated until the instruction queue 202 outputs the queue full signal 202-2 and the instruction code in the instruction queue 202 becomes full. Instruction queue
When the cue full signal 202-2 from 202 becomes active, the execution control unit 206 outputs TI until the BRQ 205-1 becomes active or the cue full signal 202-2 becomes inactive again, Keep the bus cycle idle.

(2) When the BRQ signal 205-1 becomes active After the currently executed bus cycle (if any) is completed, the ACK signal 206-1 is generated regardless of the state of the queue ready signal 202-1.
Is activated to notify the processing execution unit 205 that the data read / write cycle activation request has been received, and immediately activates the data read / write cycle. In this way, since the data read / write and the instruction code fetch are executed in parallel, the execution control unit 206 sets the queue ready signal 202
A data read / write cycle activation request is received by the BRQ signal 205-1 regardless of the state of -1.

FIG. 7 shows a case in which a data write cycle activation request is accepted during an instruction code fetch cycle, and data writing and instruction code fetch are performed in parallel.

Next, the overall operation including the bus cycle operation of the microcomputer system of FIG. 1 will be described in the case of (1) operation during reset (2) operation during normal instruction execution (3) operation during branch processing.

(1) Operation at reset Microprocessor 100 by external reset input
When the reset signal 100-2 is activated, the execution control unit 206 initializes the PC 200. For bus cycle control, the TI signal is output until the reset signal 100-2 becomes inactive, and the bus cycle becomes idle. The instruction queue 202 has been flushed and is empty, and the queue ready signal 202-1 is inactive.

When the reset signal 100-2 is inactive, the execution control unit 206 activates the branch processing cycle including the instruction code fetch of the branch destination. At this time, the initial value of the PC 200 as the branch destination address is output to the AD bus 106 through the input / output terminal 100-1. After the branch processing cycle ends, the execution control unit 206 continuously activates instruction code fetch cycles to read the instruction code in the instruction queue.

(2) Operation during normal instruction execution When the queue ready from the instruction queue 202 becomes active, the microprocessor 100 reads the instruction code from the head of the instruction queue 202 and fetches it into the IR203. PC200
The value of is incremented by the incrementer 201 by reading the instruction code from the instruction queue 202. The instruction code fetched by the IR 203 is decoded by the instruction decoder 204, and the processing execution unit 205 executes the instruction by the control signal output from the instruction decoder 204.

When it is necessary to read / write processing data from / to the data memory 103 or the peripheral input / output device 104 in executing the instruction, the processing execution unit 205 finishes the address calculation and then outputs the BRQ signal 205-
1 is activated and the execution control unit 206 is requested to activate the data read / write cycle.

The execution control unit 206 activates the ACK signal 206-1 and accepts the activation request after the end of the currently executed bus cycle (if any), and immediately activates the data read / write cycle including the instruction code fetch cycle. .

(3) Operation during branch processing The processing execution unit 205 calculates the branch destination address and determines the branch to the branch destination in the case of a branch instruction, and writes the branch destination address to the PC 200 when it determines that the branch is taken. BRCH
The signal 205-2 is activated to request the execution control unit 206 to start the branch processing cycle. After the end of the currently executed bus cycle (if any), the execution control unit 206 activates the ACK signal 206-1 to accept the start request of the branch processing cycle, and immediately receives the branch processing cycle including the instruction code fetch of the branch destination. To start.

Further, since the instruction queue 202 is flushed and becomes empty, the queue ready signal 202-1 becomes inactive.

After the end of the branch processing cycle, the execution control unit 206 continuously activates the instruction code fetch cycle and fetches the instruction code of the branch destination into the instruction queue 202.

As described above, in the normal operation at the time of executing an instruction, the parallel processing of the data read / write with the data memory 103 or the peripheral input / output device 104 by the instruction execution and the parallel processing of the instruction code fetch from the program memory 102 is reset. In the operation at the time or at the time of branching, the parallel processing of the writing to the IP 102-2 in the program memory 102 and the instruction code fetch from the memory unit 102-1 pointed to by the written IP 102-2 is performed. Be done.

In the case of the data read / write cycle and the branch processing cycle, since the address information on the A bus 107 is required, three timings of T1, T2, and T3 are required, but the instruction code fetch cycle is the instruction code fetch. Since the IP 102-2 in the program memory 102 retains the previous address information, it ends at two timings T2 and T3.

As described above, according to one embodiment of the present invention, in a microcomputer system including a microprocessor, a memory, and a peripheral input / output device, in addition to a bus in which address information and data are multiplexed, a dedicated instruction code read By providing a reading counter for the bus and the memory storing the instruction code, the following effects can be obtained.

(1) Since the counter for reading the memory storing the instruction code is provided, the microprocessor does not need to start the bus cycle for outputting the address of the fetch destination in the instruction code fetch cycle. This reduction in the number of bus cycles speeds up the instruction code fetch cycle and improves the instruction execution speed of the entire system.

(2) In the same bus cycle, data read / write between the microprocessor and the memory or the peripheral input / output device accompanying instruction execution and instruction code fetch of the microprocessor are performed in parallel, so data read associated with instruction execution Even when the / write cycle is activated frequently, the instruction code is always fetched, and the instruction code prefetching effect by providing the instruction queue becomes very effective.

(3) Since the data read / write and the instruction code fetch are performed in parallel, the microprocessor waits for the activation of the data read / write cycle due to the shortage of the instruction code in the instruction queue, and the instruction code is forcibly fetched. Start the cycle. There is no need to control. As a result, the data read / write cycle activation request accompanying instruction execution is always accepted regardless of the state in the instruction queue, and the average execution time of instructions involving bus cycles is shortened. Further, depending on the state of the instruction queue, hardware for controlling the priority of the data read / write cycle activation request and the instruction code fetch cycle activation request becomes unnecessary.

(4) During normal instruction processing, parallel processing of data read / write by instruction execution and instruction code fetch is performed, and at the time of reset or branch processing, a read counter for the memory storing the instruction code. Is performed and the instruction code fetch from the memory pointed to by the written counter is performed in parallel, so the bus access efficiency is improved and the bus neck is reduced, improving the overall performance of the microcomputer system. .

As described above, the present invention improves the memory access efficiency of the bus and executes the apparent memory access time by executing the data read / write cycle and the instruction code fetch cycle in parallel without significantly increasing the load on the hardware. It has a high practical importance because it speeds up the process and improves the prefetching effect of the instruction code used in the pipeline system.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the microprocessor of FIG. 1, FIG. 3, FIG. 4 (A), and FIG. 4 (B). ), Fig. 5,
FIGS. 6 and 7 are timing charts in each mode of one embodiment, FIG. 8 is a block diagram of a conventional example, FIG. 9 is a block diagram showing the microprocessor in FIG.
FIG. 11, FIG. 11 (A), FIG. 11 (B), FIG. 12 and FIG. 13 are timing charts in each mode of the conventional example. 100 ... Data processing means (microprocessor), 102 ...
... Program supply means (program memory), 103, 104
... data information means (data memory, peripheral input / output device), 105 ... second transfer means (I bus), 106,107 ... first transfer means (AD bus, A bus).

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-60-33634 (JP, A) JP-A-58-139386 (JP, A) JP-A-55-123739 (JP, A) JP-A-55- 160382 (JP, A) JP 58-225440 (JP, A) Actual development 57-166241 (JP, U)

Claims (1)

[Claims] 1. A microprocessor, a data memory,
A program memory, a first bus connecting the microprocessor and the data memory, a second bus connecting the microprocessor and the program memory, the first bus and an address latch, and A third bus that connects the data memory and the program memory in common, the microprocessor has a queue memory for storing the program read from the program memory, and the program memory has the address latch By incorporating an incrementer that increments the address transferred via the address as an initial value, the contents of the first bus and the incrementer for accessing the data memory to read / write data are set. According to the program read from the program memory Microcomputer system the second uses a bus in parallel, the read program from the program memory, characterized in that so as to store in the queue memory to perform the transfer.