JPH03252131A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH03252131A
JPH03252131A JP4731590A JP4731590A JPH03252131A JP H03252131 A JPH03252131 A JP H03252131A JP 4731590 A JP4731590 A JP 4731590A JP 4731590 A JP4731590 A JP 4731590A JP H03252131 A JPH03252131 A JP H03252131A
Authority
JP
Japan
Prior art keywords
trench
film
reflow
composite film
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4731590A
Other languages
Japanese (ja)
Inventor
Seiichi Iwasa
誠一 岩佐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP4731590A priority Critical patent/JPH03252131A/en
Publication of JPH03252131A publication Critical patent/JPH03252131A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To provide the upper corner of a trench with curvature and form the trench, and to form the diameter of the trench in 0.8mum or less by forming the trench to a composite film using a reflow film and an upper layer, making the reflow film reflow, covering the side face of a lower layer film and forming the trench while employing the composite film as a mask. CONSTITUTION:A process in which two layers or more of a composite film 15 using a reflow film 14 as an upper layer is shaped onto a semiconductor substrate 1, a process in which a trench 17 is formed to the composite film 15, a process in which said reflow film 14 is made to reflow through heat treatment and the side faces of lower layer films 12, 13 are covered, and a process in which a trench 19 is shaped to the semiconductor substrate 11 while employing said composite film 15 as a mask are provided. The oxide film 12, the silicon nitride film 13 and the boron or phosphorus-containing oxide film 14 are formed onto the silicon substrate 11, and a trench 17 is formed to the composite film 15 while using a photo-resist 16 as a mask. The photo-resist 16 is removed, the boron or phosphorus-containing oxide film 14 is made to reflow through heat treatment, the lower layer films 12, 13 are covered, and a trench 18 having curvature is shaped. The trench 19 is formed while employing the trench 18 made to reflow as a mask.

Description

【発明の詳細な説明】 [発明の構成] (産業上の利用分野) 本発明は、半導体装置の製造方法に関し、特にトレンチ
形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Structure of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a trench.

(従来の技術) 半導体装置に用いられるトレンチは、DRAM (Dy
nastic Randam Access Mea+
ory)の容量電極面の増大や、各種デバイスの素子分
離等に使用される。
(Prior Art) A trench used in a semiconductor device is used for DRAM (Dy
nastic Random Access Mea+
It is used for increasing the capacitive electrode surface of 3D ory) and for element isolation of various devices.

以下図面を参照して従来の半導体装置の製造方法におけ
るトレンチ形成方法について説明する。
A trench forming method in a conventional semiconductor device manufacturing method will be described below with reference to the drawings.

第2図の(a)〜(c)は、従来のトレンチ形成方法を
説明する断面図である。
FIGS. 2(a) to 2(c) are cross-sectional views illustrating a conventional trench forming method.

まず、第2図(a)に示すように、シリコン基板21の
上に熱酸化法で約1000人の酸化膜22を成長させ、
前記酸化膜22の上に減圧CVD法で約1500人の窒
化珪素膜23を堆積させ、前記窒化珪素膜23上に常圧
CVD法で、約6000人のアンドープ酸化膜24を堆
積させて、複合膜25を形成させる。
First, as shown in FIG. 2(a), about 1000 oxide films 22 are grown on a silicon substrate 21 by thermal oxidation.
A silicon nitride film 23 of about 1,500 layers is deposited on the oxide film 22 by a low pressure CVD method, and an undoped oxide film 24 of about 6,000 layers is deposited on the silicon nitride film 23 by a normal pressure CVD method to form a composite. A film 25 is formed.

次に、第2図(b)に示すように、所望のトレンチを形
成するために、フォトリソグラフィ技術を用いて被エツ
チング領域のフォトレジスト26を除去上、反応性イオ
ンエツチング技術を用いて、複合膜25を異方的にエツ
チングし、シリコン基板21にトレンチを形成するため
に溝27を形成する。
Next, in order to form a desired trench, as shown in FIG. Film 25 is anisotropically etched to form grooves 27 to form trenches in silicon substrate 21.

次に、第2図(C)に示すように、フォトレジスト26
を酸素プラズマアッシング法と硫酸−過酸化水素混合液
で除去した後、反応性イオンエツチング技術を用いて前
記複合膜25をマスクとしシリコン基板21にトレンチ
28を形成する。
Next, as shown in FIG. 2(C), the photoresist 26
After removing the etching using an oxygen plasma ashing method and a sulfuric acid-hydrogen peroxide mixture, a trench 28 is formed in the silicon substrate 21 using the composite film 25 as a mask using a reactive ion etching technique.

このように、従来のトレンチ形成方法でトレンチを形成
すると、第2図の(e)及び、第3図の拡大図に示すよ
うにトレンチの形状が垂直であるので、トレンチの上部
コーナー35が鋭角の形状となる。このため、鋭角の上
部コーナー35において電界が集中し、リーク電流の増
大が起こり、キャパシタとしての電気的特性を著しく劣
化させる。
As described above, when a trench is formed using the conventional trench forming method, the shape of the trench is vertical as shown in FIG. 2(e) and the enlarged view of FIG. The shape will be . For this reason, the electric field concentrates at the acute upper corner 35, causing an increase in leakage current and significantly deteriorating the electrical characteristics of the capacitor.

また、現在、ICチップの高集積化が進む中、トレンチ
径が0.8μm以下のトレンチが必要となってきている
。しかし、従来のトレンチ形成方法では、トレンチ径を
決定するのは、現状のフォトリソグラフィ技術で、0,
8μm以下のトレンチ径を形成するのが困難である。
Furthermore, as IC chips are currently becoming more highly integrated, trenches with a trench diameter of 0.8 μm or less are becoming necessary. However, in the conventional trench forming method, the trench diameter is determined using current photolithography technology.
It is difficult to form a trench diameter of 8 μm or less.

(発明が解決しようとする課題) このように、従来の半導体装置の製造方法におけるトレ
ンチ形成方法では、トレンチの上部コーナーが鋭角の形
状となり、上部コーナーに、電界が集中してしまい、リ
ーク電流の増大をきたし、キャパシタとしての電気的特
性を著しく劣化させていた。
(Problems to be Solved by the Invention) As described above, in the trench forming method in the conventional semiconductor device manufacturing method, the upper corner of the trench has an acute angle shape, and the electric field is concentrated at the upper corner, resulting in a leakage current. This caused a significant increase in the electrical characteristics of the capacitor.

また、現在、トレンチ径を決定するフォトリソグラフィ
技術では、0.8μm以下のトレンチ径を形成すること
ができなかった。
Furthermore, with the current photolithography technology that determines the trench diameter, it has not been possible to form a trench diameter of 0.8 μm or less.

本発明では、トレンチの上部コーナーに曲率を持たせて
トレンチを形成することを目的とし、さらに、トレンチ
径を0.8μm以下に形成することを目的とする半導体
装置の製造方法を提供するものである。
The present invention provides a method for manufacturing a semiconductor device, the purpose of which is to form a trench by giving a curvature to the upper corner of the trench, and further to form a trench with a diameter of 0.8 μm or less. be.

[発明の構成コ (課題を解決するための手段) 上記目的を達成するために本発明においては、半導体基
板上にリフロー膜を上層とする2層以上の複合膜を形成
する工程と、前記複合膜に溝を形成する工程と、熱処理
により前記リフロー膜をリフローさせて、下層膜の側面
を覆う工程と、前記複合膜をマスクとし、半導体基板に
溝を形成する工程とを具備した半導体基板の製造方法で
ある。
[Configuration of the Invention (Means for Solving the Problem) In order to achieve the above object, the present invention includes a step of forming a composite film of two or more layers with a reflow film as an upper layer on a semiconductor substrate; A semiconductor substrate comprising the steps of: forming a groove in the film; reflowing the reflow film through heat treatment to cover the side surfaces of the underlying film; and forming a groove in the semiconductor substrate using the composite film as a mask. This is the manufacturing method.

(作 用) 本発明のトレンチ形成方法においては、半導体基板上に
リフロー膜を上層とする2層以上の複合膜を形成し、そ
の複合膜に溝を形成し、熱処理によりリフロー膜をリフ
ローさせ、下層膜の側面を覆い、その結果できた複合膜
をマスクとして、半導体基板にトレンチを形成する。
(Function) In the trench forming method of the present invention, a composite film of two or more layers including a reflow film as an upper layer is formed on a semiconductor substrate, a groove is formed in the composite film, and the reflow film is reflowed by heat treatment. A trench is formed in the semiconductor substrate by covering the side surfaces of the lower layer film and using the resulting composite film as a mask.

反応性イオンエツチング技術を用いたトレンチ形成方法
では、マスクとなる複合膜の形状が、トレンチの形状に
反映する。本発明では、マスクとなる複合膜の上層膜に
リフロー膜を使用しており、そのリフロー膜をリフロー
させてから、トレンチのマスクとなる複合膜は、曲率を
持っているので、トレンチの上部コーナーに曲率を持た
せることができる。トレンチの上部コーナーに曲率を持
たせることができることによって、電界集中が緩和する
ことができ、第4図の従来技術と本発明の実施例に電気
的特性の比較図の従来技術の曲線42と本発明の曲線4
1を比較してわかるように、従来技術より、リーク電流
を減少することができ、キャパシタとしての電気的特性
を著しく向上させることができる。
In a trench forming method using reactive ion etching technology, the shape of the composite film serving as a mask is reflected in the shape of the trench. In the present invention, a reflow film is used as the upper layer film of the composite film that serves as a mask, and after the reflow film is reflowed, the composite film that serves as a mask for the trench has a curvature, so the upper corner of the trench is can have curvature. By allowing the upper corner of the trench to have a curvature, electric field concentration can be alleviated. Invention curve 4
1, it is possible to reduce the leakage current and significantly improve the electrical characteristics as a capacitor compared to the conventional technology.

また、マスクとなる複合膜の溝の側面をリフロー膜で覆
い、その分だけ溝が狭くなるので、トレンチ径が0.8
μm以下のトレンチを形成することができる。
In addition, since the sides of the groove of the composite film that serves as a mask are covered with a reflow film, the groove becomes narrower by that much, so the trench diameter is reduced to 0.8
A trench of μm or less can be formed.

(実施例) 実施例について、図面を参照して説明する。(Example) Examples will be described with reference to the drawings.

まず、第1図(a)に示すように、シリコン基板11上
に熱酸化法で約1000人の酸化膜12を成長させ、前
記酸化膜12上に、減圧CVD法で約1500人の窒化
珪素膜13を堆積し、前記窒化珪素膜13上に常圧CV
D法で、約6000人の燐硼素含有膜(リフロー膜)1
4を堆積させ、前記酸化膜12と窒化珪素膜13と燐硼
素含有膜14とを複合膜15とする。
First, as shown in FIG. 1(a), an oxide film 12 of about 1,000 layers is grown on a silicon substrate 11 by a thermal oxidation method, and a silicon nitride film of about 1,500 layers is grown on the oxide film 12 by a low-pressure CVD method. A film 13 is deposited on the silicon nitride film 13 by normal pressure CV.
Approximately 6,000 people used phosphorus-boron-containing film (reflow film) 1 using D method.
4 is deposited to form a composite film 15 of the oxide film 12, silicon nitride film 13, and phosphorus-boron containing film 14.

次に、第1図(b)に示すように、前記燐硼素含有膜1
4の上にフォトレジスト16を塗布し、所望のトレンチ
を形成するため、被エツチング領域のフォトレジスト1
6をフォトリソグラフィ技術を用いて除去する。除去後
、反応性イオンエツチング技術で、複合膜15を異方エ
ツチングをし、溝17を形成する。
Next, as shown in FIG. 1(b), the phosphorus-boron containing film 1
A photoresist 16 is applied on top of the photoresist 16 in the area to be etched to form the desired trench.
6 is removed using photolithography technology. After removal, the composite film 15 is anisotropically etched using a reactive ion etching technique to form grooves 17.

次に、第1図(C)に示すように、前記フォトレジスト
16を酸素プラズマアッシング法と、硫酸−過水素混合
液で除去した後、熱処理を行ない前記燐硼素含有酸化膜
14をリフローさせて、下層膜(酸化膜12と窒化珪素
膜13)を覆い、曲率のある溝18を形成する。
Next, as shown in FIG. 1C, after removing the photoresist 16 using an oxygen plasma ashing method and a sulfuric acid-perhydrogen mixture, heat treatment is performed to reflow the phosphorus-boron-containing oxide film 14. , a groove 18 with curvature is formed by covering the lower layer film (oxide film 12 and silicon nitride film 13).

最後に、第2図の(d)に示すようにリフローさせた複
合膜15で形成した溝18をマスクとして、複合膜15
とシリコン基板11とを反応性イオンエツチング技術に
より異方的にエツチングを行ない、トレンチ19を形成
する。
Finally, as shown in FIG. 2(d), using the grooves 18 formed in the reflowed composite film 15 as a mask, the composite film 15 is
and silicon substrate 11 are anisotropically etched using reactive ion etching technology to form trenches 19.

以上のような、トレンチの形成方法を用いてトレンチを
形成すると、第1図の(C)に示すように、リフローさ
せた複合膜がトレンチのマスクとなる。
When a trench is formed using the trench forming method as described above, the reflowed composite film serves as a mask for the trench, as shown in FIG. 1C.

トレンチの形状は、マスクとなる複合膜の形状に反映す
るので、トレンチの上部コーナーに曲率を持たせること
ができる。ゆえに、トレンチの上部コーナーにおける電
界集中を緩和することができ、リーク電流を減少するこ
とができた。よって、キャパシタとしての電気的特性著
しく改善するとかできた。
Since the shape of the trench is reflected in the shape of the composite film serving as a mask, the upper corner of the trench can have a curvature. Therefore, electric field concentration at the upper corner of the trench could be alleviated, and leakage current could be reduced. Therefore, it was possible to significantly improve the electrical characteristics as a capacitor.

また、マスクとなる複合膜の溝の側面をリフロー膜で覆
い、その分だけ溝が狭くなるので、トレンチ径0.8μ
m以上のトレンチを形成することができる。
In addition, since the sides of the groove of the composite film that serves as a mask are covered with a reflow film, the groove becomes narrower by that amount, so the trench diameter is 0.8μ.
m or more trenches can be formed.

本実施例では、トレンチ形成の時のリフロー膜に、常圧
CVD法で堆積させた燐硼素含有酸化膜を用いた場合に
ついて説明をしたが、燐、硼素。
In this embodiment, a case has been described in which a phosphorus-boron-containing oxide film deposited by atmospheric pressure CVD is used as a reflow film when forming a trench.

砒素などの不純物を少なくとも1つ含んだ酸化膜であれ
ば、同様な効果が得られる。
A similar effect can be obtained using an oxide film containing at least one impurity such as arsenic.

[発明の効果] 以上、詳述したように、本発明の半導体装置のトレンチ
形成方法によれば、トレンチの形成するためのマスクと
なる複合膜の上層膜に、リフロー膜を用いることにより
、マスクの上部コーナーに曲率を持ったトレンチを形成
でき、トレンチの上部コーナーの電界集中を緩和でき、
リーク電流を減少することができる。また、トレンチ径
0.8μm以下のトレンチを形成できた。
[Effects of the Invention] As described above in detail, according to the trench forming method for a semiconductor device of the present invention, a reflow film is used as the upper layer film of the composite film that serves as a mask for forming the trench. A trench with curvature can be formed at the upper corner of the trench, which can alleviate the electric field concentration at the upper corner of the trench.
Leakage current can be reduced. Moreover, a trench with a trench diameter of 0.8 μm or less could be formed.

【図面の簡単な説明】 第1図(a)〜(d)は、本発明の半導体装置の製造工
程を示す断面図。 第2図(a)〜(c)は、従来の半導体装置の製造工程
を示す断面図。 第3図は、従来技術の問題点を示す断面図。 第4図は、従来技術と本発明の実施例の電気的特性比較
図である。 11.21.31・・・・・・シリコン基板12.22
.32・・・・・・酸化膜 13.23.33・・・・・・窒化珪素膜14    
  ・・・・・・燐硼素含有膜15.25    ・・
・・・・複合膜6、26 7、27 9、28 4、34 ・・・・・・フォトレジスト ・・・・・・溝 ・・・・・・リフローさせた溝 ・・・・・・トレンチ ・・・・・・アンドープ酸化膜 ・・・・・・トレンチ上部コーナ ・・・・・・本発明の電気的特性 ・・・・・・従来技術の電気的特性 坏 1 丼 区 q 茅 不 貫ヲ1→ 齋 神 鎚
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1(a) to 1(d) are cross-sectional views showing the manufacturing process of a semiconductor device of the present invention. FIGS. 2(a) to 2(c) are cross-sectional views showing the manufacturing process of a conventional semiconductor device. FIG. 3 is a sectional view showing problems in the prior art. FIG. 4 is a diagram comparing the electrical characteristics of the prior art and the embodiment of the present invention. 11.21.31... Silicon substrate 12.22
.. 32...Oxide film 13.23.33...Silicon nitride film 14
... Phosphorous boron containing film 15.25 ...
...Composite film 6, 26 7, 27 9, 28 4, 34 ...Photoresist ... Groove ... Reflow groove ... Trench ......Undoped oxide film...Trench top corner...Electrical characteristics of the present invention...Electrical characteristics of conventional technologyヲ1→ Saishin Hammer

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上のリフロー膜を上層とする2層以上
の複合膜を形成する工程と、 前記複合膜に溝を形成する工程と、 熱処理により前記リフロー膜をリフローさせて下層膜の
側面を覆う工程と、 前記複合膜をマスクとし、半導体基板に溝を形成する工
程とを具備した半導体装置の製造方法。
(1) A step of forming a composite film of two or more layers including a reflow film on a semiconductor substrate as an upper layer, a step of forming a groove in the composite film, and a step of reflowing the reflow film by heat treatment to form a side surface of the lower layer film. A method of manufacturing a semiconductor device, comprising: a step of covering the semiconductor substrate; and a step of forming a groove in a semiconductor substrate using the composite film as a mask.
(2)前記リフロー膜が燐、硼素、砒素、ゲルマニュー
ムの不純物を少なくとも1種類含んだシリコン酸化膜で
あることを特徴とする請求項1記載の半導体装置の製造
方法。
(2) The method of manufacturing a semiconductor device according to claim 1, wherein the reflow film is a silicon oxide film containing at least one type of impurity such as phosphorus, boron, arsenic, or germanium.
JP4731590A 1990-03-01 1990-03-01 Manufacture of semiconductor device Pending JPH03252131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4731590A JPH03252131A (en) 1990-03-01 1990-03-01 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4731590A JPH03252131A (en) 1990-03-01 1990-03-01 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03252131A true JPH03252131A (en) 1991-11-11

Family

ID=12771856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4731590A Pending JPH03252131A (en) 1990-03-01 1990-03-01 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03252131A (en)

Cited By (9)

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US6482701B1 (en) 1999-08-04 2002-11-19 Denso Corporation Integrated gate bipolar transistor and method of manufacturing the same
US6521538B2 (en) 2000-02-28 2003-02-18 Denso Corporation Method of forming a trench with a rounded bottom in a semiconductor device
KR100399944B1 (en) * 1996-12-30 2003-12-31 주식회사 하이닉스반도체 Method for forming isolation layer of semiconductor device
KR100417574B1 (en) * 1996-08-30 2004-04-13 주식회사 하이닉스반도체 Method for fabricating semiconductor device
US6864532B2 (en) 2000-01-14 2005-03-08 Denso Corporation Semiconductor device and method for manufacturing the same
JP2006024932A (en) * 2004-07-06 2006-01-26 Samsung Electronics Co Ltd Method for forming tunneling insulating layer of nonvolatile memory device
JP2012002802A (en) * 2010-05-17 2012-01-05 Hitachi Metals Ltd Magnetic sensor, magnetic type encoder, and method of manufacturing magnetic sensor
JP2021100093A (en) * 2019-12-20 2021-07-01 東京エレクトロン株式会社 Etching method, substrate processing device, and substrate processing system

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100417574B1 (en) * 1996-08-30 2004-04-13 주식회사 하이닉스반도체 Method for fabricating semiconductor device
KR100399944B1 (en) * 1996-12-30 2003-12-31 주식회사 하이닉스반도체 Method for forming isolation layer of semiconductor device
US6482701B1 (en) 1999-08-04 2002-11-19 Denso Corporation Integrated gate bipolar transistor and method of manufacturing the same
US6469345B2 (en) 2000-01-14 2002-10-22 Denso Corporation Semiconductor device and method for manufacturing the same
US6864532B2 (en) 2000-01-14 2005-03-08 Denso Corporation Semiconductor device and method for manufacturing the same
US7354829B2 (en) 2000-01-14 2008-04-08 Denso Corporation Trench-gate transistor with ono gate dielectric and fabrication process therefor
US6521538B2 (en) 2000-02-28 2003-02-18 Denso Corporation Method of forming a trench with a rounded bottom in a semiconductor device
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