JP2715581B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed, highly-integrated, high-yield semiconductor device and a method of manufacturing the same, and more particularly to a structure of an element isolation region of a semiconductor device and a method of forming the same.

2. Description of the Related Art Conventionally, as a structure of an element isolation region using a groove of a semiconductor device and a method for forming the same, a portion to be an element isolation region is etched to form a groove, and then the inside of the groove is oxidized and After the polycrystalline silicon film is embedded, there is a method in which an insulating film is formed on the surface of the groove to form an element isolation region. An example of the prior art will be described with reference to FIG.

An isolation groove 42 is formed on the semiconductor substrate around the active region 41 where a semiconductor device (for example, a MOS transistor, a bipolar transistor, a resistor, etc.) is formed by using an insulating film, a resist or the like as a mask (FIG. 6). (A)). Thereafter, the surface of the semiconductor substrate is oxidized to form an oxide film 43 on the surface in the groove, and a polycrystalline silicon film 44 is buried in the groove (FIG. 6B). FIG. 6C is a sectional view taken along line AA '. After that, an insulating film is formed on the surface of the groove to complete the structure of the element isolation region.

SUMMARY OF THE INVENTION In such a conventional method, a polycrystalline silicon film is used.
When the polycrystalline silicon film is deposited in the groove when the polycrystalline silicon film is deposited, when the polycrystalline silicon film other than the groove portion is removed, the concave portion 45 particularly deeply remains at the corner of the groove. This situation is shown in FIGS. 6 (b) and 6 (c). The occurrence of the depression 45 has caused a problem of disconnection and short circuit of the Al wiring.

Further, as shown in FIG. 7, in the structure in which the grooves intersect, a very deep dent 46 is generated at the intersection of the grooves, which causes disconnection of the AL wiring and the like, which lowers the yield of the integrated circuit. There was a problem.

Furthermore, at the corners of the grooves, stress concentration due to oxidation occurs, and crystal defects occur in the active region. As the size of the semiconductor device becomes smaller, the characteristics of the semiconductor device deteriorate.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and can prevent the occurrence of a depression at a corner portion of a separation groove, can further reduce the influence of stress at the corner portion, and can provide a high-speed and highly integrated semiconductor device. It is an object of the present invention to provide a semiconductor device which can be formed with a yield and a manufacturing method thereof.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides (1) a groove having an arbitrary planar shape formed on a semiconductor substrate, an oxide film formed on an inner wall of the groove, and the groove A structure including a semiconductor film or an insulating film embedded in a substrate is defined as a basic unit structure, a plurality of the basic unit structures are arranged in an element isolation region, and an oxide film in an adjacent groove portion contacts each other to form an isolation structure. Things.

According to the present invention, in addition to the configuration (1), (2) the shape of the groove is cylindrical.

According to the present invention, since the structure in which the inside of the groove formed in the semiconductor is oxidized and buried with the semiconductor film or the insulating film becomes the basic isolation structure according to the above configuration (1), the basic isolation structure is formed as a unit. An element isolation structure of an arbitrary shape that can be formed can be formed as a uniformly flat structure with good controllability without a step at a specific portion. Therefore, it is possible to form a narrow isolation region and a wide isolation region flat with good controllability in the same process.

Further, according to the above configuration (2), by changing the shape of the groove, the influence of insulation separation applied to the semiconductor device can be reduced. For example, when the isolation region is formed by a square-shaped groove, stress is increased at the corner of the groove, which may affect the semiconductor device as the semiconductor device becomes finer. Thus, the influence of stress concentration at the corner on the semiconductor device can be reduced.

Example (Example 1) FIG. 1 is a process chart showing a method for manufacturing an element isolation region in a first example of the present invention. FIG. 1 (b),
(D), (f), and (h) correspond to FIGS.
It is sectional drawing in the AA 'line of the top view shown to (c), (e), and (g). Hereinafter, a method for manufacturing the element isolation region will be described with reference to FIG.

An oxide film 2 is formed on a semiconductor substrate 1 to a thickness of 600 nm, and an isolation region 4 around an active region 3 on which a semiconductor element is to be formed has a side length of 1.5 μm using a normal photolithography technique.
m square grooves are formed at intervals of 0.5 μm.
Thereafter, a groove 5 is formed on the semiconductor substrate 1 by using an anisotropic etching technique such as dry etching (FIGS. 1A and 1B).

Next, high-concentration boron ions are implanted into the bottom of the groove 5 using the oxide film 2 as a mask, and then the oxide film 2 is removed by wet etching. Thereafter, the groove 5 and the surface of the semiconductor substrate 1 are oxidized to form an oxide film 6 having a thickness of 300 nm. At this time, the portion of the semiconductor between the trenches 5 is oxidized from both sides of the trench 5, so that it can be completely changed to an oxide film, and the isolation region 4 is formed around the active region 3. At the same time as the oxidation step, a channel stopper region 7 is formed at the bottom of the groove 5 (FIG. 1C).
(D)).

Thereafter, a polycrystalline silicon film is deposited to a thickness of 2 μm, and portions other than the groove are removed by a method such as etch-back, and the polycrystalline silicon film 8 is left only in the groove. At this time, the grooves are buried with the polycrystalline silicon film 8 from the four walls, so that the occurrence of depressions is reduced. Further, since the grooves are buried in the same manner, steps may be generated at corners and the like. And a separation region having a uniform buried shape is formed (first
Figures (e) and (f)).

Finally, an element isolation region is completed by forming a surface insulating film 9 (FIGS. 1 (g) and 1 (h)).

As described above, in the present embodiment, by arranging the grooves having a certain size, a uniform and flat separation region can be formed, and problems such as disconnection and short circuit of the AL wiring can be solved.

(Embodiment 2) FIGS. 2A and 2B are a plan view and a plan view showing a structure of an element isolation region in a second embodiment of the present invention, respectively.
It is sectional drawing in the A 'line. Hereinafter, a method for manufacturing the element isolation region will be described with reference to FIG.

In the isolation region around the active region 3 where the semiconductor element is formed, one side of the isolation region 10 having a narrow width is 1.times. Using photolithography technology and dry etching technology.
One row of 5 μm square grooves is formed at intervals of 0.5 μm, and five rows of grooves are formed in the wide separation region 11 with the same size and spacing. Thereafter, impurity ions for forming the channel stopper region 7 are implanted, and the groove and the surface of the semiconductor substrate are oxidized to form an oxide film 6 having a thickness of 300 nm. At the same time, the channel stopper region 7 is formed at the bottom of the groove. . The trench is filled with a polycrystalline silicon film, and the surface insulating film 9 is formed.
To complete the isolation region (FIG. 2 (a),
(B)).

As described above, in the present embodiment, it is possible to form both a wide isolation region and a narrow isolation region with good flatness in the same process, thereby realizing a high-speed, highly integrated semiconductor device with a high yield. It becomes possible.

Third Embodiment FIG. 3 is a process chart showing a method for manufacturing an element isolation region according to a third embodiment of the present invention. FIG. 3 (b), (d)
A- in the plan views shown in FIGS. 1 (a) and 1 (c), respectively.
It is sectional drawing in the A 'line. Also, FIG.
It is sectional drawing in the BB 'line of figure (d). Hereinafter, a method for manufacturing the element isolation region will be described with reference to FIG.

Using a photolithography technique and a dry etching technique, a cylindrical groove 12 having a diameter of 1.5 μm is formed in an isolation region 4 around an active region 3 on which a semiconductor element is formed on a semiconductor substrate 1.
Are formed at intervals of 0.5 μm (FIG. 3A,
(B)).

Next, impurity ions for forming the channel stopper region 7 are implanted to form the columnar groove 12 and the semiconductor substrate 1.
Is oxidized to form an oxide film 6 having a thickness of 300 nm.
At this time, in the semiconductor portion between the cylindrical grooves 12,
Since the oxidation proceeds from both sides, the vicinity of the center can be completely changed to an oxide film, and the isolation region 4 is formed around the active region 3.
Is formed.

At this time, if the groove is square, stress concentration occurs at the corner, and crystal defects are induced in the active region 3,
In some cases, the characteristics of the semiconductor device may be adversely affected, such as an increase in leakage current.However, by forming the cylindrical groove 12,
Stress concentration at the corner 13 of the active region caused by oxidation can be reduced. The adverse effects due to the stress appear more remarkably in the element characteristics as the semiconductor device becomes finer. By using this means, the influence of the stress can be reduced (FIG. 3 (c),
(D), (e)).

Fourth Embodiment FIG. 4 is a process chart showing a method for manufacturing an element isolation region according to a fourth embodiment of the present invention. FIG. 4 (d) is a plan view of FIG. 4 (c). Hereinafter, a method for manufacturing the element isolation region will be described with reference to FIG.

An oxide film 22 having a thickness of 600 nm and a silicon nitride film 23 having a thickness of 120 nm are formed on a semiconductor substrate 21, and a square groove a24 having a side length of 0.5 μm is formed by photolithography to form a 0.5 μm
(FIG. 4A).

Next, the oxide film 22 is etched by 0.2 μm in the lateral direction using a solution having a large etching selectivity between the oxide film 22 and the silicon nitride film 23, for example, a solution of HF: H ₂ O = 1: 50. Then, grooves b25 each having a side length of 0.9 μm are formed at intervals of 0.1 μm (FIG. 4B).

Thereafter, the silicon nitride film 23 is removed, and a mask for etching the silicon trench is formed around the active region 26 (FIGS. 4C and 4D).

As described above, the interval between the grooves can be narrower than the resolution limit of photolithography, and by forming the grooves on the semiconductor substrate 21 and then oxidizing to a thickness of 100 nm,
Since the region between the grooves can be completely changed to an oxide film, and the isolation region can be formed with a small oxide film thickness, the influence of stress on the semiconductor device due to oxidation can be reduced. Thereafter, similarly to the above-described embodiment, the polycrystalline silicon film is buried and a surface insulating film is formed to complete the isolation region.

Embodiment 5 FIG. 5 is a process chart showing a method for manufacturing an element isolation region according to a fifth embodiment of the present invention. FIG. 5 (c), (f)
FIGS. 4A and 4B are plan views of FIGS. 4B and 4E, respectively. Hereinafter, a method for manufacturing the element isolation region will be described with reference to FIG.

50 nm thick as a first insulating film on the semiconductor substrate 31 sequentially.
An oxide film 32 having a thickness of 400 nm as a second film and an oxide film having a thickness of 50 nm as a third film.
34, and a projection having a side length of 0.5 μm is formed by photolithography (FIG. 5A).

Next, a polycrystalline silicon film is deposited as a fourth film to a thickness of 200 nm, and dry etching is performed to leave the polycrystalline silicon film 35 only on the side walls. At this time, a polycrystalline silicon island having a side length of about 0.9 μm is formed around the active region 36. here,
The corner portion of the polycrystalline silicon island is rounded with the shape of the polycrystalline silicon film deposited on the side wall remaining (fifth part).
Figures (b) and (c)).

Next, a CVD oxide film is deposited as a fifth insulating film to a thickness of 1000 nm, a resist is uniformly applied on the entire surface, and then, using an etch back, the CVD oxide film 37 is formed in a region other than the polycrystalline silicon island.
Leave. At this time, the oxide film 34 on the polycrystalline silicon island is also removed (FIG. 5D).

Thereafter, the polycrystalline silicon island is removed by wet etching, and the oxide film 32 is dry-etched using the CVD oxide film 37 as a mask to form a groove 38 (FIG. 5E).
(F)).

Thereafter, the semiconductor substrate 31 located at the groove 38 is dry-etched to form a groove serving as an isolation region in the semiconductor substrate 31. When the inside of the groove is oxidized to completely form an oxide film between the adjacent grooves, the corner of the groove 38 is round, so that stress concentration generated at the corner can be reduced. Therefore, a fine semiconductor device can be formed.

In this embodiment, the second film is a polycrystalline silicon film, and the third film is an oxide film. However, the etching selectivity of the second film and the fourth film is equal, and the second and fourth films are equal. What is necessary is that the etching selectivity of the film and the fifth film is different,
For example, a CVD oxide film may be used as the second film, and a nitride film may be used as the third film.

Effect of the Invention As is apparent from the above description, according to the present invention, since a plurality of micro-shaped grooves are arranged at regular intervals to form a separation region, a step occurs at a corner of the separation region. The isolation region can be formed with good flatness without any problem and regardless of the width of the isolation region. Further, since the influence of stress generated when forming the isolation region can be suppressed, a fine semiconductor device can be formed, and a high-speed, highly integrated semiconductor device can be realized with a high yield.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a process chart showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and FIG. FIG. 4 is a process chart showing a method for manufacturing a semiconductor device in Example 3, FIG. 4 is a process chart showing a method for manufacturing a semiconductor device in Example 4 of the present invention, and FIG. 5 is a method for manufacturing a semiconductor device in Example 5 of the present invention. FIG. 6 is a process chart showing a conventional method for manufacturing a semiconductor device, and FIG. 7 is a structural plan view of the conventional semiconductor device. 1,21,31 …… Semiconductor substrate, 2,6,22,32,34 …… Oxide film, 3,2
6,36 active area, 4 isolation area, 5,38 groove, 7
... channel stopper region, 8, 33, 35 ... polycrystalline silicon film, 9 ... surface insulating film, 10 ... narrow width isolation region, 11
... wide separation region, 12 ... cylindrical groove, 13 ... corner of active region, 23 ... silicon nitride film, 24 ... groove a, 25 ... groove b, 37 ... CVD oxide film .

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Akihiro Kanda 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. (56) References JP-A-58-98942 (JP, A) JP-A-54- 43839 (JP, A)

Claims (4)

(57) [Claims] A cylindrical groove formed in a semiconductor substrate;
A structure including an oxide film formed on the inner wall of the groove and a semiconductor film or an insulating film embedded in the groove is defined as a basic unit structure, and a plurality of the basic unit structures are arranged in an element isolation region and are adjacent to each other. A semiconductor device, wherein an oxide film in a groove portion contacts each other to form an isolation structure. 2. A step of forming a columnar groove adjacent to a device isolation region on a semiconductor substrate at a predetermined interval, a step of oxidizing an inner wall of the groove, and a step of forming a semiconductor film in the groove.
Alternatively, a method of manufacturing a semiconductor device, further comprising a step of burying an insulating film, wherein a space between the adjacent grooves is completely changed to an oxide film. A step of forming a first insulating film on the semiconductor substrate; a step of forming a second insulating film having a different etching selectivity on the first insulating film; The insulating film is etched to form an arbitrary first shape in the element isolation region.
Forming the grooves at regular intervals;
Etching the side wall of the insulating film to widen the groove to form a second groove having an interval smaller than the limit of photolithography, and narrowing the interval between the adjacent second grooves;
Etching the second insulating film and removing the second insulating film; etching the semiconductor substrate using the first insulating film as a mask to form a third groove in the semiconductor substrate; And a step of burying a semiconductor film or an insulating film in the trench, and completely converting an adjacent trench into an oxide film. 4. A step of forming a first insulating film on a semiconductor substrate, a step of forming a second film having a different etching selectivity on the first insulating film, and etching the second film. Forming a third film having a different selectivity on the second film; and etching the second and third films to form a first projection having an arbitrary planar shape in the element isolation region. Forming a plurality of layers at intervals, leaving a fourth film identical to the second film on the side wall of the first protrusion, and leaving the fourth film on the side wall of the adjacent first protrusion. Forming a second projection at a predetermined interval from the fourth coating, and forming a fifth insulating film having an etching selectivity different from that of the second coating in a region other than the second projection. Forming, and removing the second and fourth coatings by etching, and forming a first coating having a columnar corner portion. Forming a part, after etching the first insulating film in the first groove, the fifth
Etching the semiconductor substrate using the insulating film as a mask, forming a second groove in the semiconductor substrate, oxidizing an inner wall of the groove, and embedding a semiconductor film or an insulating film in the groove. And a step of completely converting the space between the adjacent grooves into an oxide film.