KR100399944B1 - Method for forming isolation layer of semiconductor device - Google Patents
Method for forming isolation layer of semiconductor device Download PDFInfo
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- KR100399944B1 KR100399944B1 KR1019960076350A KR19960076350A KR100399944B1 KR 100399944 B1 KR100399944 B1 KR 100399944B1 KR 1019960076350 A KR1019960076350 A KR 1019960076350A KR 19960076350 A KR19960076350 A KR 19960076350A KR 100399944 B1 KR100399944 B1 KR 100399944B1
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- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000002955 isolation Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- 230000003064 anti-oxidating effect Effects 0.000 claims abstract description 6
- 239000003963 antioxidant agent Substances 0.000 claims description 7
- 230000003078 antioxidant effect Effects 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims description 4
- 241000293849 Cordylanthus Species 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 210000003323 beak Anatomy 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 241000257303 Hymenoptera Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
본 발명은 반도체 장치의 소자 분리막 형성방법에 관한 것으로, 특히 LOCOS(LOCal Oxidation of Silicon) 공정에 의해 형성된 필드 산화막에 의한 실리콘 기판과의 단차 및 버즈 비크를 최소화하여 반도체 소자의 고집적화를 꾀하기 위한 반도체 장치의 소자 분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a device isolation film of a semiconductor device. In particular, a semiconductor device for minimizing step differences and buzz bees with a silicon substrate by a field oxide film formed by a LOCOS (LOCal Oxidation of Silicon) process to achieve high integration of semiconductor devices. It relates to a device isolation film forming method of.
일반적으로, 소자 분리막은 집적소자를 구성하는 개별소자를 전기적 및 구조적으로 서로 분리시켜, 각 소자가 인접한 소자의 간섭을 받지 않고 독자적으로 주어진 기능을 수행할 수 있도록 한다.In general, the device isolation layer electrically and structurally separates the individual elements constituting the integrated device, so that each device can perform its own function without interference from adjacent devices.
도1은 종래 기술에 따른 반도체 장치의 소자 분리막 형성 공정 단면도로, 실리콘 기판(1)상에 패드 산화막(2) 및 질화막(3)을 차례로 형성하고, 활성영역(5)과 오버랩되는 소자 분리 마스크를 사용하여 소정부위의 실리콘 기판(1)이 노출될때까지 상기 질화막(3)을 제거한 다음, 이를 산화방지 마스크로 열산화(Thermal Oxidation)공정을 진행하여 5000Å 정도 두께의 필드 산화막(4)(Field Oxide)을 형성시킨 것을 도시한 것이다.1 is a cross-sectional view of a device isolation film forming process of a semiconductor device according to the prior art, in which a pad oxide film 2 and a nitride film 3 are sequentially formed on a silicon substrate 1, and a device isolation mask overlapping the active region 5 is shown. The nitride film 3 is removed until the silicon substrate 1 of the predetermined portion is exposed, and then subjected to a thermal oxidation process using an anti-oxidation mask to obtain a field oxide film 4 having a thickness of about 5000 s (Field). Oxide) is formed.
그러나, 상기 필드 산화막(4)은 2000Å 정도 두께의 상기 실리콘 기판(10)을 산화시키면서 성장한 것으로, 상기 실리콘 기판(10) 표면을 기준으로 했을 때 상기 실리콘 기판(10)과 3000Å 이상의 단차를 유발시키게 되며, 이에 따라 후속 공정인 게이트 전극 형성을 위한 폴리실리콘막 형성시 패턴의 나칭(Notching) 및 붕괴(Collapse) 현상을 유발하게 될 뿐만 아니라, 차후 공정진행시 계속해서 단차가 누적되어 국부적인 공정 변수를 유발하게 된다.However, the field oxide film 4 is grown while oxidizing the silicon substrate 10 having a thickness of about 2000 GPa, so that when the surface of the silicon substrate 10 is referenced, the field oxide film 4 causes a step of 3000 mV or more. As a result, notching and collapsing of the pattern may be caused when the polysilicon film is formed to form the gate electrode, which is a subsequent process. Will cause.
또한, 상기 필드 산화막(4)의 표면장력은 상기 질화막(3) 아래에 존재하는 패드 산화막(2)의 수평방향으로 작용하게 되고, 이에 따라 상기 패드 산화막(2)의 수평방향으로 산화가 진행되어 상기 질화막(3)와 측벽이 치켜 올라가면서 필드 산화막(4)이 형성되어 버즈 비크(Bird's Beak ; 도면부호 A) 현상을 일으키게 됨에 따라 활성영역(5)이 감소하게 되는 등의 문제점이 있었다. 미설명 부호 "6"은 소자분리 영역을 도시한 것이다.In addition, the surface tension of the field oxide film 4 acts in the horizontal direction of the pad oxide film 2 under the nitride film 3, and thus oxidation proceeds in the horizontal direction of the pad oxide film 2. As the nitride oxide film 3 and the sidewalls are raised, the field oxide film 4 is formed to cause a bird's beak phenomenon (A), thereby reducing the active region 5. Reference numeral 6 denotes an isolation region.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 반도체 기판과의 단차를 효과적으로 제거함과 동시에 버즈 비크의 발생으로 인한 활성영역의 감소를 억제하여 소자의 고집적화를 꾀할 수 있는 반도체 장치의 소자 분리막 형성방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems effectively removes the step with the semiconductor substrate and at the same time suppresses the reduction of the active area due to the occurrence of the buzz beak device isolation film forming method of the semiconductor device capable of high integration of the device The purpose is to provide.
도1은 종래기술에 따른 반도체 장치의 소자 분리막 형성 공정 단면도,1 is a cross-sectional view of a device isolation film forming process of a semiconductor device according to the prior art;
도2A 내지 도2C는 본 발명의 일실시예에 따른 반도체 장치의 소자 분리막 형성 공정 단면도.2A to 2C are cross-sectional views of a device isolation film forming process in a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 실리콘 기판 20 : 패드 산화막10 silicon substrate 20 pad oxide film
30 : 질화막 40 : 필드 산화막30: nitride film 40: field oxide film
50 : 포토레지스트 패턴 60 : 활성영역50: photoresist pattern 60: active area
70 : 소자분리 영역70: device isolation region
상기 목적을 달성하기 위하여 본 발명은 반도체 기판상에 산화방지막을 형성하는 단계; 상기 산화방지막상에 포토레지스트를 형성하되, 이후의 리플로우 공정 타겟을 감안하여 소정 두께만큼 더 형성하는 단계; 소자분리 마스크를 사용하여 상기 포토레지스트를 노광 ·현상하는 단계; 상기 포토레지스트를 식각마스크로 상기 산화방지막을 식각하는 단계; 상기 포토레지스트의 융점에 가까운 온도에서 과다 형성된 만큼의 상기 포토레지스트를 리플로우시키는 단계; 상기 리플로우된 포토레지스트를 식각마스크로 소정 깊이의 반도체 기판을 식각하여 트랜치를 형성하는 단계; 상기 리플로우된 포토레지스트를 제거하는 단계; 및 열산화 공정에 의해 필드 산화막을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention comprises the steps of forming an antioxidant film on a semiconductor substrate; Forming a photoresist on the anti-oxidation layer, and further forming the photoresist by a predetermined thickness in consideration of a subsequent reflow process target; Exposing and developing the photoresist using an isolation mask; Etching the antioxidant layer using the photoresist as an etching mask; Reflowing the photoresist as much as formed at a temperature near the melting point of the photoresist; Etching the semiconductor substrate having a predetermined depth using the reflowed photoresist as an etching mask to form a trench; Removing the reflowed photoresist; And forming a field oxide film by a thermal oxidation process.
이하, 본 발명을 첨부된 도면을 참조하여 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.
도2A 내지 도2C는 본 발명의 일실시예에 따른 반도체 장치의 소자 분리막 형성 공정 단면도이다.2A to 2C are cross-sectional views of a device isolation film forming process of a semiconductor device according to an embodiment of the present invention.
먼저, 도2A는 실리콘 기판(10)상에 패드 산화막(20) 및 2000℃ 정도 두게의 질화막(30)을 차례로 형성한 후, 상기 질화막(30) 상부에 15000Å 내지 30000Å 정도 두께의 포토레지스트를 도포하고, 활성영역(60)과 오버랩되는 소자분리 마스크를 사용하여 노광 ·현상한 다음, 이를 식각마스크로 상기 질화막(30) 및 패드 산화막(20)을 선택식각한 것을 도시한 것이다.First, FIG. 2A sequentially forms a pad oxide film 20 and a nitride film 30 having a thickness of about 2000 ° C. on a silicon substrate 10, and then applies a photoresist having a thickness of about 15000 GPa to 30000 GPa on the nitride film 30. After exposure and development using an element isolation mask overlapping the active region 60, the nitride layer 30 and the pad oxide layer 20 are selectively etched using an etching mask.
이때, 상기 포토레지트의 두께는 상기 리플로우(Reflow) 처리시의 두께를 감안하여 1000Å 내지 10000Å 정도 더 형성한 것이며, 상기 소자분리 마스크를 사용한 질화막의 식각 공정시 발생하는 손상분은 포토레지스트의 전체 두께에 비해 극소하므로 무시한다.In this case, the thickness of the photoresist is about 1000 kPa to about 10000 kPa in consideration of the thickness during the reflow treatment, and the damage generated during the etching process of the nitride film using the device isolation mask is performed by the photoresist. Ignore it because it is very small compared to the overall thickness
이어서, 도2B는 상기 포토레지스트의 융점 130℃ 정도의 핫 오븐에서 과다 형성된 두께만큼의 상기 포토레지스트(50)를 리플로우(Reflow)시킨 다음, 상기 리플로우된 포토레지스트(50)를 식각마스크로 200Å 내지 3000Å 정도 깊이의 실리콘 기판(10)을 식각하여 트랜치를 형성한 것을 도시한 것으로, 상기 포토레지스트(50)의 리플로우 공정은 상기 포토레지스트(50)에 의해 노출된 질화막(30)을 덮을 정도로 한다.Subsequently, in FIG. 2B, the photoresist 50 is reflowed by an excessive thickness in a hot oven having a melting point of about 130 ° C., and then the reflowed photoresist 50 is used as an etching mask. The trench is formed by etching the silicon substrate 10 having a depth of about 200 to 3000 microseconds. The reflow process of the photoresist 50 may cover the nitride layer 30 exposed by the photoresist 50. It is enough.
이때, 상기 포토레지스트를 리플로우 시키기 위한 온도는 포토레지스트의 종류별 특성에 따라 포토레지스트의 융점이 다르므로 대략 130℃를 기준으로한다.At this time, the temperature for reflowing the photoresist is about 130 ℃ because the melting point of the photoresist is different depending on the characteristics of the type of photoresist.
마지막으로, 도2C는 상기 포토레지스트(50)를 제거하고, 상기 질화막(30)을 산화방지막으로한 열산화(Thermal Oxidation) 공정에 의해 필드 산화막(40)을 성장시킨 것을 도시한 것으로, 이때 트랜치된 깊이만큼 상기 실리콘 기판(10)과 필드 산화막(40)간의 단차가 현저히 줄어들고, 상기 필드 산화막(40)의 성장을 위한 열산화 공정시 상기 필드 산화막(40) 내부의 표면장력이 트랜치 하부로 분산됨으로써실리콘 기판(10)과 질화막(20) 계면 사이의 패드 산화막(20)의 수평방향으로 작용하는 표면장력이 상대적으로 줄어들어 버즈 비크(도면부호, A) 현상이 줄어든 것을 알수 있다. 미설명 부호 "70"은 활성영역을 나타낸다.Finally, FIG. 2C shows that the field oxide film 40 is grown by a thermal oxidation process in which the photoresist 50 is removed and the nitride film 30 is an antioxidant film. The step difference between the silicon substrate 10 and the field oxide film 40 is significantly reduced by the increased depth, and the surface tension inside the field oxide film 40 is dispersed below the trench during the thermal oxidation process for the growth of the field oxide film 40. As a result, it can be seen that the surface tension acting in the horizontal direction of the pad oxide film 20 between the silicon substrate 10 and the nitride film 20 interface is relatively reduced, thereby reducing the phenomenon of the buzz beak (reference numeral A). Reference numeral 70 denotes an active region.
본 발명은 본 발명의 일실시예에 한정되지 않으며 상기 포토레지스트의 리플로우(Reflow) 처리 방식은 각 층(Layer)간의 정확한 중첩도(Overlay Accuracy)를 실현할 수 있으므로, 정확한 중첩도를 요하는 공정 특히, 고집적 소자의 미세 콘택홀 형성 공정에 유용하게 응용될 수 있다.The present invention is not limited to one embodiment of the present invention, and the reflow processing method of the photoresist can realize an accurate overlay degree between each layer, and thus a process requiring accurate overlap degree In particular, it can be usefully applied to the process of forming a fine contact hole of a highly integrated device.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
상기와 같이 이루어지는 본 발명은 산화방지막 패턴 형성을 위한 포토레지스트를 이후의 리플로우 공정 타겟을 감안하여 과증착한 후, 산화방지막 패턴 형성을 위한 식각 공정을 진행하고, 과증착된 만큼의 포토레지스트를 리플로우시킨 다음, 이를 식각마스크로 소정 깊이의 실리콘 기판을 식각하여 트랜치를 형성한 후, 열산화하여 필드 산화막을 형성함으로써, 트랜치된 깊이만큼 실리콘 기판과 필드 산화막간의 단차를 현저히 줄일 수 있어 단차에 의한 페일을 방지할 수 있을 뿐만 아니라, 상기 필드 산화막의 성장을 위한 열산화 공정시 상기 필드 산화막 내부의 표면장력이 트랜치 하부로 분산됨으로써 실리콘 기판과 질화막 계면 사이의 패드 산화막의 수평방향으로 작용하는 표면장력이 줄어들어 이에 따른 버즈 비크 현상을 최소화할 수 있어 소자의 고집적이 용이하게 한다.According to the present invention made as described above, the photoresist for forming the antioxidant film pattern is over-deposited in consideration of the subsequent reflow process target, and then the etching process for forming the antioxidant film pattern is performed, After reflowing, the trench is formed by etching a silicon substrate having a predetermined depth with an etching mask, and then thermally oxidized to form a field oxide film, thereby significantly reducing the step difference between the silicon substrate and the field oxide film by the trench depth. In addition, the surface tension of the pad oxide film between the silicon substrate and the nitride film interface between the silicon substrate and the nitride film interface can be prevented, as well as the surface tension of the inside of the field oxide film is dispersed below the trench during the thermal oxidation process for the growth of the field oxide film. The tension is reduced, so the buzz beak can be minimized. It's easy to be integrated.
또한, 포토레지스트의 리플로우 처리 공정에 의해 트랜치 형성을 위한 별도의 마스킹 공정을 진행하지 않아도되며, 특히 상기 포토레지스트의 리플로우(Reflow) 처리 공정은 각 층(Layer)간의 정확한 중첩도(Overlay Accuracy)를 실현할 수 있어 정확한 중첩도를 요하는 반도체 소자 제조 공정에 유용하게 응용할 수 있다.In addition, a separate masking process for trench formation is not required by the reflow processing process of the photoresist, and in particular, the reflow processing process of the photoresist may include accurate overlay accuracy between layers. ) Can be usefully applied to a semiconductor device manufacturing process requiring an accurate degree of overlap.
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| JPH03252131A (en) * | 1990-03-01 | 1991-11-11 | Toshiba Corp | Manufacture of semiconductor device |
| KR0140845B1 (en) * | 1993-12-29 | 1998-07-15 | 김주용 | Forming method of isolation film on semiconductor device |
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| JPH03252131A (en) * | 1990-03-01 | 1991-11-11 | Toshiba Corp | Manufacture of semiconductor device |
| KR0140845B1 (en) * | 1993-12-29 | 1998-07-15 | 김주용 | Forming method of isolation film on semiconductor device |
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